Large-area perovskite battery module with ultrahigh geometric filling rate as well as preparation method and application of large-area perovskite battery module

Abstract

The invention provides a large-area perovskite battery module with an ultrahigh geometric filling rate and a preparation method and application thereof, and the preparation method of the large-area perovskite battery module with the ultrahigh geometric filling rate comprises the following steps: 1) P1 process: coating photoresist on a substrate comprising an electron transport layer, and carrying out exposure, development and etching according to a required pattern; 2) P2 process: sequentially coating a perovskite layer and a hole transport layer on the upper surface of the electron transport layer from the direction far away from the electron transport layer, then depositing an injection layer, and performing overlay exposure slotting and etching on the surface of the injection layer; and 3) P3 process: sequentially depositing a metal electrode and a protective layer in a direction far away from the electron transport layer, and performing overlay exposure slotting and etching on the surface of the protective layer. The geometric filling factor (GFF) of the effective area of the prepared large-area perovskite battery module reaches 99.7% or above, and the yield is 90% or above.

Description

Technical Field

[0001] The present invention relates to the research field of new energy technology, and in particular to a method for preparing a perovskite battery module and a perovskite battery module prepared by the method. Background Art

[0002] Perovskite solar cells have attracted great attention due to their high efficiency and multiple photovoltaic (PV) application scenarios. At present, the photoelectric conversion efficiency of 5*5cm perovskite cell modules has exceeded 23%, and it is difficult to improve it further.

[0003] Currently, large-area perovskite battery modules in academia and industry are realized through the P1-P2-P3 process scheme, which is basically completed by using laser physical ablation to control the geometric fill factor (GFF) of the effective area of ​​the battery. Physical laser ablation brings several problems: 1. The ablation edge is jagged; 2. The ablation thickness is not easy to control, especially the damage of the P2 layer to the FTO, which will cause the series resistance to increase; 3. The ablation hot spot can affect the efficiency of the adjacent sub-battery; 4. The ablation line is thick, resulting in a relatively low GFF, which in turn affects the overall power generation of the battery.

[0004] An important indicator for evaluating the quality of large-area perovskite battery modules is the effective power per unit area, which is also one of the criteria for judging commercial batteries. There are two ways to increase the power per unit area of ​​perovskite batteries. One is to improve the photoelectric conversion efficiency, and the other is to increase the GFF of the effective surface of the battery, that is, to minimize the dead area. At present, the GFF of perovskite battery modules prepared by traditional laser physical etching methods is typically in the range of 90-97%, and it is difficult to increase it further. Therefore, it is of great significance to develop and prepare large-area perovskite battery modules. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a large-area perovskite battery module with an ultra-high geometric filling rate to solve the problems in the prior art.

[0006] To achieve the above-mentioned purpose and other related purposes, the present invention provides a method for preparing a large-area perovskite battery module with an ultra-high geometric filling rate, the method comprising the following steps:

[0007] 1) P1 process: coating a photoresist on a substrate including an electron transport layer, and performing exposure, development, and etching according to a desired pattern;

[0008] 2) P2 process: on the upper surface of the electron transport layer, a perovskite layer and a hole transport layer are sequentially coated in a direction away from the electron transport layer, and then an injection layer is deposited, and an overlay exposure groove is performed and an etching is performed on the surface of the injection layer;

[0009] 3) P3 process: metal electrodes and protective layers are deposited in sequence from a direction away from the electron transport layer, and the surface of the protective layer is overlaid, exposed, grooved and etched.

[0010] The present invention also provides a large-area perovskite battery module with ultra-high geometric filling rate, and the large-area perovskite battery module with ultra-high geometric filling rate is prepared by the above method.

[0011] The present invention also provides the use of large-area perovskite cells with ultra-high geometric filling rate in the preparation of photovoltaic modules.

[0012] The present invention also provides a photovoltaic module, which contains the perovskite battery module prepared by the above method.

[0013] As described above, the large-area perovskite battery module with ultra-high geometric filling rate and its preparation method and use of the present invention have the following beneficial effects:

[0014] 1) The introduction of a new process can enable the GFF of large-area perovskite battery modules to reach 99.7% or above, breaking through the limit of the original method that was difficult to exceed 97%;

[0015] 2) A new process has been introduced, which allows the etching thickness to be precisely controlled within ±1nm, and the etching sidewall is smooth, with a smoothness of ≤±

[0016] 1nm), the etching angle can be controlled (the angle can be controlled within ±0.1°), which greatly reduces the impact of ablation hot spots on perovskite cells, thereby increasing the power density of perovskite cells per unit area;

[0017] 3) Significantly improve the yield rate of perovskite cells from 50%-60% to more than 90%;

[0018] 4) Combining the chip manufacturing process with the P1-P2-P3 process of perovskite cells, achieving cross-integration of the two fields, which is highly original;

[0019] 5) The photolithography and etching processes used in the present invention are conventional processes in the chip manufacturing process, which makes the present invention highly compatible and universal with the chip manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Shown are a cross-sectional view (above) and a top view (below) of the structure of the perovskite battery module of the present invention.

[0021] Figure 2 It shows an optical schematic diagram of the perovskite battery module P1 process of the present invention after 5μm line width etching and development.

[0022] Figure 3It shows a SEM schematic diagram of 5μm line width etching in the P1 process of the perovskite battery module of the present invention.

[0023] Figure 4 Shown is a schematic diagram of the groove structure of the P2 process of the perovskite battery module of the present invention.

[0024] Figure 5 Shown is a schematic diagram of the groove structure of the P3 process of the perovskite battery module of the present invention.

[0025] Figure 6 Shown is a SEM schematic diagram of the groove opening process P2 and P3 of the perovskite battery module of the present invention. DETAILED DESCRIPTION

[0026] The present invention provides a method for preparing a large-area perovskite battery module with an ultra-high geometric filling rate, the method comprising the following steps:

[0027] 1) P1 process: coating a photoresist on a substrate including an electron transport layer, and performing exposure, development, and etching according to a desired pattern;

[0028] 2) P2 process: on the upper surface of the electron transport layer, a perovskite layer and a hole transport layer are sequentially coated in a direction away from the electron transport layer, and then an injection layer is deposited, and an overlay exposure groove is performed and an etching is performed on the surface of the injection layer;

[0029] 3) P3 process: metal electrodes and protective layers are deposited in sequence from a direction away from the electron transport layer, and the surface of the protective layer is overlaid, exposed, grooved and etched.

[0030] The ultra-high geometric filling rate refers to a geometric filling rate of the perovskite battery module exceeding 99.5%.

[0031] The geometric filling ratio represents the ratio between the active area of ​​the cell and the aperture area.

[0032] The large-area perovskite battery module refers to a perovskite battery module with an area exceeding 1 square centimeter (cm2).

[0033] In certain embodiments of the present invention, in process P1, P2 or P3, the exposure equipment is a laser direct writing lithography machine.

[0034] In certain embodiments of the present invention, in process P1, P2 or P3, the type of laser used for exposure is nanosecond pulse laser or continuous laser.

[0035] In certain embodiments of the present invention, in process P1, P2 or P3, the exposure is mask exposure, holographic exposure, direct writing exposure or other exposure methods in the prior art.

[0036] In some embodiments of the present invention, the direct-write exposure is a direct-write exposure controlled by a DMD (digital micromirror) array.

[0037] In certain embodiments of the present invention, in the P2 or P3 process, the equipment for forming the grooves is a laser direct writing lithography machine.

[0038] In certain embodiments of the present invention, in the P2 or P3 process, the type of laser used for the grooving is nanosecond pulse laser or continuous laser.

[0039] The average pulse width of the nanosecond pulse laser is in the range of 1 to 100 ns. The average pulse width of the nanosecond pulse laser is selected from any of the following ranges: 1 to 20 ns, 20 to 40 ns, 40 to 60 ns, 60 to 80 ns, and 80 to 100 ns.

[0040] The laser power of the nanosecond pulse laser is 1 to 100 W. The laser power of the nanosecond pulse laser is selected from any of the following ranges: 1 to 20 W, 20 to 40 W, 40 to 60 W, 60 to 80 W, and 80 to 100 W.

[0041] In certain embodiments of the present invention, in step P1, the thickness of the substrate is 0.05 mm to 3 mm. The thickness of the substrate is selected from any of the following ranges: 0.05 mm to 0.1 mm, 0.1 mm to 0.5 mm, 0.5 mm to 1 mm, 1 mm to 1.5 mm, 1.5 mm to 2 mm, 2 mm to 2.5 mm, 2.5 mm to 3 mm.

[0042] In certain embodiments of the present invention, in step P1, the etching is plasma etching.

[0043] In certain embodiments of the present invention, in the P1 process, the etching depth is to penetrate the electron transport layer or penetrate the electron transport layer and over-etch on the substrate within 100 nm. The etching depth is selected from any of the following ranges: penetrate the electron transport layer, penetrate the electron transport layer and over-etch on the substrate by 0 to 20 nm, penetrate the electron transport layer and over-etch on the substrate by 20 to 40 nm, penetrate the electron transport layer and over-etch on the substrate by 40 to 60 nm, penetrate the electron transport layer and over-etch on the substrate by 60 to 80 nm, penetrate the electron transport layer and over-etch on the substrate by 80 to 100 nm.

[0044] In certain embodiments of the present invention, in step P1, the etching line width is 0.5-10 μm. The etching line width is selected from any of the following ranges: 0.5-2 μm, 2-4 μm, 4-6 μm, 6-8 μm, 8-10 μm.

[0045] In certain embodiments of the present invention, in the P1 process, the etching depth is precisely controlled to be ≤±1 nm.

[0046] In certain embodiments of the present invention, in step P1, the etching angle α is 45 to 90°, that is, the etching shape is rectangular or trapezoidal, so that a rectangular groove or a trapezoidal groove is formed. The etching angle α is selected from any of the following ranges: 45 to 60°, 60 to 75°, and 75 to 90°. In the present invention, the etching angle refers to the angle between the etching direction perpendicular to the surface and the horizontal line of the surface during the etching process. The etching angle α is Figure 3 as shown in .

[0047] In certain embodiments of the present invention, in the P1 process, the etching angle accuracy is ≤0.1°.

[0048] In certain embodiments of the present invention, in the P1 process, the side wall smoothness after etching is ≤±1 nm.

[0049] In certain embodiments of the present invention, in step P1, the width L1 of the rectangular groove or trapezoidal groove on the surface of the electron transport layer is 0.5 to 10 μm. The width of the rectangular groove or trapezoidal groove on the surface of the electron transport layer is selected from any of the following ranges: 0.5 to 2 μm, 2 to 4 μm, 4 to 6 μm, 6 to 8 μm, 8 to 10 μm. In the present invention, the width L1 of the rectangular groove on the surface of the electron transport layer is as follows: Figure 3 shown.

[0050] In certain embodiments of the present invention, in step P1, the number of rectangular grooves or trapezoidal grooves is 5 to 500. The number of rectangular grooves or trapezoidal grooves is selected from any of the following ranges: 5 to 100, 100 to 200, 200 to 300, 300 to 400, 400 to 500.

[0051] In certain embodiments of the present invention, in the P1 process, the rectangular grooves or trapezoidal grooves formed are adjacent to each other with a gap of 0 to 0.1 mm.

[0052] In certain embodiments of the present invention, the P1 process further includes marking an alignment mark for overlay on the electron transport layer.

[0053] In certain embodiments of the present invention, in step P1, the thickness of the electron transport layer is 50-650 nm. The thickness of the electron transport layer is selected from any of the following ranges: 50-150 nm, 150-250 nm, 250-350 nm, 350-450 nm, 450-550 nm, 550-650 nm.

[0054] In certain embodiments of the present invention, in step P1, the thickness of the photoresist is 0.1-10 μm. The thickness of the photoresist is selected from any of the following ranges: 0.1-2 μm, 2-4 μm, 4-6 μm, 6-8 μm, 8-10 μm.

[0055] In certain embodiments of the present invention, in step P1, the photoresist is a positive photoresist or a negative photoresist.

[0056] In certain embodiments of the present invention, in step P1, the development time is 10 to 100 s. The development time is selected from any of the following ranges: 10 to 20 s, 20 to 40 s, 40 to 60 s, 60 to 80 s, and 80 to 100 s.

[0057] In certain embodiments of the present invention, the P1 process further includes cleaning the photoresist after the etching is completed.

[0058] In certain embodiments of the present invention, in step P2, the groove depth is 40-400 nm, and the groove depth is selected from any of the following ranges: 40-100 nm, 100-160 nm, 160-220 nm, 220-280 nm, 280-340 nm, 340-400 nm.

[0059] In certain embodiments of the present invention, in step P2, the groove width is 0.5-10 μm. The groove width is selected from any of the following ranges: 0.5-2 μm, 2-4 μm, 4-6 μm, 6-8 μm, 8-10 μm.

[0060] In certain embodiments of the present invention, in the P2 process, the etching is plasma etching.

[0061] In certain embodiments of the present invention, in the P2 process, the etching line width is 0.5-10 μm. The etching line width is selected from any of the following ranges: 0.5-2 μm, 2-4 μm, 4-6 μm, 6-8 μm, 8-10 μm.

[0062] In certain embodiments of the present invention, in the P2 process, the etching depth is through the injection layer, the hole transport layer and the perovskite layer or through the injection layer, the hole transport layer and the perovskite layer and over-etching to 0% to 20% of the thickness of the electron transport layer. The etching depth is selected from any of the following ranges: through the injection layer, the hole transport layer and the perovskite layer; through the injection layer, the hole transport layer and the perovskite layer and over-etching to 0% to 5% of the thickness of the electron transport layer; through the injection layer, the hole transport layer and the perovskite layer and over-etching to 5% to 10% of the thickness of the electron transport layer; through the injection layer, the hole transport layer and the perovskite layer and over-etching to 10% to 15% of the thickness of the electron transport layer; through the injection layer, the hole transport layer and the perovskite layer and over-etching to 15% to 20% of the thickness of the electron transport layer.

[0063] In certain embodiments of the present invention, in the P2 process, the etching depth is precisely controlled to be ≤±1 nm.

[0064] In certain embodiments of the present invention, in the P2 process, the etching angle β is 45 to 90°, that is, the etching shape is rectangular or trapezoidal, so that a rectangular groove or a trapezoidal groove is formed. The etching angle β is selected from any of the following ranges: 45 to 60°, 60 to 75°, 75 to 90°. The etching angle β is not marked in the figure, but its specific value and direction can be determined by the same measurement method as the etching angle α.

[0065] In certain embodiments of the present invention, in the P2 process, the etching angle accuracy is ≤0.1°.

[0066] In certain embodiments of the present invention, in the P2 process, the side wall smoothness after etching is ≤±1 nm.

[0067] In certain embodiments of the present invention, in step P2, the width L2 of the rectangular groove or trapezoidal groove on the surface of the injection layer is 0.5-10 μm. The width of the rectangular groove or trapezoidal groove on the surface of the injection layer is selected from any of the following ranges: 0.5-2 μm, 2-4 μm, 4-6 μm, 6-8 μm, 8-10 μm. The width L2 of the rectangular groove or trapezoidal groove on the surface of the injection layer is not indicated in the figure, but its determination method is the same as L1.

[0068] In certain embodiments of the present invention, in step P2, the number of rectangular grooves or trapezoidal grooves is 5 to 500. The number of rectangular grooves or trapezoidal grooves is selected from any of the following ranges: 5 to 100, 100 to 200, 200 to 300, 300 to 400, 400 to 500.

[0069] In certain embodiments of the present invention, the rectangular grooves or trapezoidal grooves formed in the P2 process are adjacent to each other, and the gap between them is 0 to 0.1 mm.

[0070] In certain embodiments of the present invention, in step P2, the thickness of the perovskite layer is 200-1000 nm. The thickness of the perovskite layer is selected from any of the following ranges: 200-400 nm, 400-600 nm, 600-800 nm, 800-1000 nm.

[0071] In certain embodiments of the present invention, in the P2 process, the deposition method is evaporation or sputtering.

[0072] In certain embodiments of the present invention, in step P2, the implantation layer is a metal oxide layer or a nitride layer.

[0073] The metal oxide in the metal oxide layer is selected from molybdenum oxide, aluminum oxide, nickel oxide or silicon oxide.

[0074] The nitride in the nitride layer is a nitrogen-silicon compound, and the nitrogen-silicon ratio in the nitrogen-silicon compound is 5:1 to 1:5.

[0075] In certain embodiments of the present invention, in step P2, the thickness of the injection layer is 50 to 500 nm.

[0076] In certain embodiments of the present invention, the injection layer also functions as a hard mask to protect the underlying perovskite layer and hole transport layer from being affected by subsequent processes.

[0077] In certain embodiments of the present invention, in step P3, the groove depth is 40-400 nm, and the groove depth is selected from any of the following ranges: 40-100 nm, 100-160 nm, 160-220 nm, 220-280 nm, 280-340 nm, 340-400 nm.

[0078] In certain embodiments of the present invention, in step P3, the groove width is 0.5-10 μm. The groove width is selected from any of the following ranges: 0.5-2 μm, 2-4 μm, 4-6 μm, 6-8 μm, 8-10 μm.

[0079] In certain embodiments of the present invention, in the P3 process, the etching is plasma etching.

[0080] In certain embodiments of the present invention, in the P3 process, the etching line width is 0.5-10 μm. The etching line width is selected from any of the following ranges: 0.5-2 μm, 2-4 μm, 4-6 μm, 6-8 μm, 8-10 μm.

[0081] In certain embodiments of the present invention, in the P3 process, the etching depth is through the protective layer, the metal electrode, the injection layer, the hole transport layer and the perovskite layer or through the protective layer, the metal electrode, the injection layer, the hole transport layer and the perovskite layer and over-etching to 0% to 20% of the thickness of the electron transport layer. The etching depth is selected from any of the following ranges: through the protective layer, the metal electrode, the injection layer, the hole transport layer and the perovskite layer; through the protective layer, the metal electrode, the injection layer, the hole transport layer and the perovskite layer and over-etching to 0% to 5% of the thickness of the electron transport layer; through the protective layer, the metal electrode, the injection layer, the hole transport layer and the perovskite layer and over-etching to 5% to 10% of the thickness of the electron transport layer; through the protective layer, the metal electrode, the injection layer, the hole transport layer and the perovskite layer and over-etching to 10% to 15% of the thickness of the electron transport layer; through the protective layer, the metal electrode, the injection layer, the hole transport layer and the perovskite layer and over-etching to 15% to 20% of the thickness of the electron transport layer.

[0082] In certain embodiments of the present invention, in the P3 process, the etching depth is precisely controlled to be ≤±1 nm.

[0083] In certain embodiments of the present invention, in the P3 process, the etching angle γ is 45 to 90°, that is, the etching shape is rectangular or trapezoidal, so that a rectangular groove or a trapezoidal groove is formed. The etching angle γ is selected from any of the following ranges: 45 to 60°, 60 to 75°, 75 to 90°. The etching angle γ is not marked in the figure, but its specific value and direction can be determined by the same measurement method as the etching angle α.

[0084] In certain embodiments of the present invention, in the P3 process, the etching angle accuracy is ≤0.1°.

[0085] In certain embodiments of the present invention, in the P3 process, the side wall smoothness after etching is ≤±1 nm.

[0086] In certain embodiments of the present invention, in the P3 process, the width L3 of the rectangular groove or trapezoidal groove on the surface of the protective layer is 0.5-10 μm. The width of the rectangular groove or trapezoidal groove on the surface of the protective layer is selected from any of the following ranges: 0.5-2 μm, 2-4 μm, 4-6 μm, 6-8 μm, 8-10 μm. The width L3 of the rectangular groove or trapezoidal groove on the surface of the protective layer is not indicated in the figure, but its determination method is the same as L1.

[0087] In certain embodiments of the present invention, in the P3 process, the number of rectangular grooves or trapezoidal grooves is 5 to 500. The number of rectangular grooves or trapezoidal grooves is selected from any of the following ranges: 5 to 100, 100 to 200, 200 to 300, 300 to 400, 400 to 500.

[0088] In certain embodiments of the present invention, the rectangular grooves or trapezoidal grooves formed in the P3 process are adjacent to each other with a gap of 0 to 0.1 mm.

[0089] In certain embodiments of the present invention, the P2 and P3 steps are overlaid relative to the P1 step, and the overlay accuracy is 100-500 nm. The overlay accuracy is selected from any of the following ranges: 100-200 nm, 200-300 nm, 300-400 nm, 400-500 nm.

[0090] In certain embodiments of the present invention, in step P3, the protective layer is a metal oxide layer or a nitride layer.

[0091] The metal oxide in the metal oxide layer is selected from molybdenum oxide, aluminum oxide, nickel oxide or silicon oxide.

[0092] The nitride in the nitride layer is a nitrogen-silicon compound, and the nitrogen-silicon ratio in the nitrogen-silicon compound is 5:1 to 1:5.

[0093] In certain embodiments of the present invention, in step P3, the thickness of the protective layer is 50-500 nm. The thickness of the protective layer is selected from any of the following ranges: 50-100 nm, 100-200 nm, 200-300 nm, 300-400 nm, 400-500 nm.

[0094] In certain embodiments of the present invention, the protective layer is used to block water and oxygen and is used as a hard mask layer. The present invention also provides a large-area perovskite battery module with an ultra-high geometric filling rate, and the large-area perovskite battery module with an ultra-high geometric filling rate is prepared by the above method.

[0095] The yield rate of the large-area perovskite battery module with ultra-high geometric filling rate prepared by the above method is above 90%, and the dead zone width can be accurately controlled, with the dead zone width ranging from 1.5 to 30 μm. The GFF is between 99.70% and 99.99%.

[0096] The large-area perovskite battery module with an ultra-high geometric filling rate includes an electron transport layer, a perovskite layer, a hole transport layer, an injection layer, a metal electrode, and a protective layer in sequence from the substrate in a direction away from the substrate.

[0097] In certain embodiments of the present invention, the length of the large-area perovskite battery module ranges from 2.0 to 200 cm.

[0098] In certain embodiments of the present invention, the width of the large-area perovskite battery module ranges from 2.0 to 200 cm.

[0099] In certain embodiments of the present invention, the number of sub-batteries in the large-area perovskite battery module is 5 to 100.

[0100] In certain embodiments of the present invention, the width of the sub-cells of the large-area perovskite battery module is 3 to 10 mm.

[0101] The present invention also provides the use of a large-area perovskite battery module in the preparation of a photovoltaic module.

[0102] The present invention also provides a photovoltaic module, which contains the large-area perovskite battery module prepared by the above method.

[0103] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0104] Before further describing the specific embodiments of the present invention, it should be understood that the scope of protection of the present invention is not limited to the specific embodiments described below; it should also be understood that the terms used in the examples of the present invention are for describing the specific embodiments rather than for limiting the scope of protection of the present invention; in the present specification and claims, unless otherwise expressly stated herein, the singular forms "a", "an" and "the" include plural forms.

[0105] When the embodiments give numerical ranges, it should be understood that, unless otherwise specified in the present invention, the two endpoints of each numerical range and any numerical value between the two endpoints can be selected. Unless otherwise defined, all technical and scientific terms used in the present invention have the same meaning as those generally understood by those skilled in the art. In addition to the specific methods, equipment, and materials used in the embodiments, according to the grasp of the prior art by those skilled in the art and the record of the present invention, any methods, equipment, and materials of the prior art similar or equivalent to the methods, equipment, and materials described in the embodiments of the present invention can also be used to realize the present invention.

[0106] Any technology not specifically disclosed in the embodiments may adopt existing technology.

[0107] Example 1

[0108] The preparation method of a large-area perovskite battery module with ultra-high geometric filling rate comprises the following steps:

[0109] 1) P1 process: a layer of photoresist with a thickness of 1.5 μm is coated on a substrate with an electron transport layer with a thickness of 550 nm, and a laser direct writing lithography machine is used to expose the desired pattern. The laser source of the laser direct writing lithography machine is a nanosecond pulse laser with an average pulse width of 20 ns and a laser power of 10 W. It is controlled by a DMD (digital micromirror) array. The photoresist is then developed for 60 seconds and plasma etched. The etching line width is 5 μm, the depth is 600 nm, the etching angle α is 78.0°, and the side wall smoothness is 1 nm. Then, the photoresist is removed and cleaned;

[0110] 2) P2 process: After the completion of P1 process, a 350nm perovskite layer and a 100nm hole transport layer are coated on the substrate in sequence, and then 300nm MoO3 is evaporated as an injection layer, and then a laser direct writing photolithography machine is used to perform overlay exposure and grooving according to the pattern, with an overlay accuracy of 250nm, a grooving depth of 200nm, and a width of 5μm; then plasma etching is performed to etch to the upper surface of the electron transport layer, with an etching line width of 5μm, an etching depth accuracy of 1nm, a side wall smoothness of 1nm, and an etching angle β of 78.0°;

[0111] 3) P3 process: Based on the P2 process, a gold electrode with a thickness of 80nm and a protective layer of silicon oxide with a thickness of 400nm are deposited, and then a laser direct writing lithography machine is used to open a groove with a depth of 350nm and a width of 5μm; then plasma etching is performed to etch to the upper surface of the electron transport layer, the etching line width is 5μm, and the etching depth accuracy is controlled to 1nm.

[0112] The side wall smoothness is 1 nm and the etching angle γ is 78.0°.

[0113] The large-area perovskite battery module obtained by the above preparation method has a size of 100x100mm, a series structure including 13 sub-batteries, a sub-battery width of 7.6785mm, a single rectangle length of 100mm, a width of 5μm, a dead zone width of 15μm, forming 12 dead zones, and a GFF of 99.82%.

[0114] Example 2

[0115] 1) P1 process: a layer of photoresist with a thickness of 1 μm is coated on a substrate with an electron transport layer with a thickness of 450 nm, and a laser direct writing lithography machine is used to expose the desired pattern. The laser source of the laser direct writing lithography machine is a nanosecond pulse laser with an average pulse width of 40 ns and a laser power of 10 W. It is controlled by a DMD (digital micromirror) array. The photoresist is then developed for 40 seconds and plasma etched. The etching line width is 4 μm, the depth is 450 nm, the etching angle α is 85.0°, and the side wall smoothness is 1 nm. Then, the photoresist is removed and cleaned;

[0116] 2) P2 process: After the completion of P1 process, a 500nm perovskite layer and a 200nm hole transport layer are coated on the substrate in sequence, and then 200nm MoO3 is sputtered as an injection layer, and then a laser direct writing lithography machine is used to perform overlay exposure and grooving according to the pattern, with an overlay accuracy of 250nm, a grooving depth of 200nm, and a width of 4μm; then plasma etching is performed to etch to the upper surface of the electron transport layer, with an etching line width of 4μm, an etching depth accuracy of 1nm, a side wall smoothness of 1nm, and an etching angle β of 85.0°;

[0117] 3) P3 process: Based on the P2 process, 80nm thick gold electrode deposition and 400nm protective layer silicon oxide deposition are carried out, and then a laser direct writing photolithography machine is used to open the groove, with a groove depth of 200nm and a width of 4μm; then plasma etching is performed to etch to the upper surface of the electron transport layer, the etching line width is 4μm, and the etching depth accuracy is controlled to 1

[0118] nm, the side wall smoothness is 1 nm, and the etching angle γ is 85.0°.

[0119] The large-area perovskite battery module obtained by the above preparation method has a size of 100x100mm, a series structure including 13 sub-batteries, a sub-battery width of 7.6785mm, a single rectangle length of 100mm, a width of 5μm, a dead zone width of 15μm, forming 12 dead zones, and a GFF of 99.82%.

[0120] Example 3

[0121] 1) P1 process: a layer of photoresist with a thickness of 1.5 μm is coated on a substrate with an electron transport layer with a thickness of 350 nm, and a laser direct writing lithography machine is used to expose the desired pattern. The laser source of the laser direct writing lithography machine is a nanosecond pulse laser with an average pulse width of 30 ns and a laser power of 10 W. It is controlled by a DMD (digital micromirror) array. The photoresist is then developed for 30 seconds and plasma etched. The etching line width is 5 μm, the depth is 350 nm, the etching angle α is 88.0°, and the side wall smoothness is 1 nm. Then, the photoresist is removed and cleaned;

[0122] 2) P2 process: After the completion of P1 process, a 350nm perovskite layer and a 100nm hole transport layer are coated on the substrate in sequence, and then 300nm MoO3 is evaporated as an injection layer, and then a laser direct writing lithography machine is used to perform overlay exposure and grooving according to the pattern, with an overlay accuracy of 250nm, a grooving depth of 200nm, and a width of 5μm; then plasma etching is performed to etch to the upper surface of the electron transport layer, with an etching line width of 5μm, an etching depth accuracy of 1nm, a side wall smoothness of 1nm, and an etching angle β of 88.0°;

[0123] 3) P3 process: Based on the P2 process, a gold electrode with a thickness of 80nm and a protective layer of silicon oxide with a thickness of 400nm are deposited, and then a laser direct writing lithography machine is used to open a groove with a depth of 100nm and a width of 5μm; then plasma etching is performed to etch to the upper surface of the electron transport layer, the etching line width is 5μm, and the etching depth accuracy is controlled to 1nm.

[0124] The sidewall smoothness is 1 nm and the etching angle γ is 88.0°.

[0125] The large-area perovskite battery module obtained by the above preparation method has a size of 100x100mm, a series structure including 13 sub-batteries, a sub-battery width of 7.6785mm, a single rectangle length of 100mm, a width of 5μm, a dead zone width of 15μm, forming 12 dead zones, and a GFF of 99.82%.

[0126] The above examples are for the purpose of illustrating the embodiments disclosed by the present invention and are not to be construed as limiting the present invention. In addition, the various modifications listed herein and the variations of the methods in the invention are obvious to those skilled in the art without departing from the scope and spirit of the present invention. Although the present invention has been specifically described in conjunction with various specific preferred embodiments of the present invention, it should be understood that the present invention should not be limited to these specific embodiments. In fact, various modifications as described above that are obvious to those skilled in the art to obtain the invention should be included within the scope of the present invention.

Claims

1. A method for preparing a large-area perovskite battery module with ultra-high geometric filling rate, characterized in that: The method comprises the following steps: 1) P1 process: coating a photoresist on a substrate including an electron transport layer, and performing exposure, development, and etching according to a desired pattern; 2) P2 process: on the upper surface of the electron transport layer, a perovskite layer and a hole transport layer are sequentially coated in a direction away from the electron transport layer, and then an injection layer is deposited, and an overlay exposure groove is performed and an etching is performed on the surface of the injection layer; 3) P3 process: metal electrodes and protective layers are deposited in sequence from a direction away from the electron transport layer, and the surface of the protective layer is overlaid, exposed, grooved and etched.

2. The method for preparing a large-area perovskite battery module according to claim 1, characterized in that: In the P1, P2 or P3 process, the laser type for exposure and / or grooving is a nanosecond pulse laser or a continuous laser; and / or, in the P1 process, an alignment mark for overlay is marked on the electron transport layer; and / or, in the P1 process, the photoresist is cleaned after etching is completed.

3. The method for preparing a large-area perovskite battery module according to claim 2, characterized in that: When the exposure and / or grooving laser is a nanosecond pulse laser, the average pulse width of the nanosecond pulse laser is in the range of 1 to 100 ns, and / or the laser power of the nanosecond pulse laser is in the range of 1 to 100 W.

4. The method for preparing a large-area perovskite battery module according to claim 1, characterized in that: The P1 process includes any one or more of the following conditions: 11) The thickness of the substrate is 0.05 mm to 3 mm; 12) The etching is plasma etching; 13) The etching depth is to penetrate the electron transport layer or penetrate the electron transport layer and over-etch within 100 nm on the substrate; 14) The etching line width is 0.5 to 10 μm; 15) The etching angle α is 45 to 90°; 16) After the etching, a rectangular groove or a trapezoidal groove is formed; preferably, the width L1 of the trapezoidal groove or the rectangular groove on the surface of the electron transport layer is 0.5 to 10 μm; preferably, the number of the rectangular grooves or the trapezoidal grooves is 5 to 500; preferably, the gap between adjacent rectangular grooves or trapezoidal grooves is 0 to 0.1 mm; 17) The thickness of the electron transport layer is 50 to 650 nm; 18) The thickness of the photoresist is 0.1 to 10 μm; 19) The development time is 10 to 100 seconds; And / or, in the P2 process, any one or more of the following conditions are included: 201) The groove depth is 40 to 400 nm; 202) the groove width is 0.5 to 10 μm; 203) The etching is plasma etching; 204) The etching line width is 0.5 to 10 μm; 205) The etching depth is through the injection layer, the hole transport layer and the perovskite layer or through the injection layer, the hole transport layer and the perovskite layer and over-etched to 0% to 20% of the thickness of the electron transport layer; 206) the etching angle β is 45 to 90°; 207) After etching, a rectangular groove or a trapezoidal groove is formed; preferably, the width L2 of the trapezoidal groove or the rectangular groove on the surface of the injection layer is 0.5-10 μm; preferably, the number of the rectangular grooves or the trapezoidal grooves is 5-500; preferably, the gap between adjacent rectangular grooves or trapezoidal grooves is 0-0.1 mm; 208) The thickness of the perovskite layer is 200 to 1000 nm; 209) The deposition method is evaporation or sputtering; 210) The thickness of the injection layer is 50 to 500 nm; And / or, in the P3 process, any one or more of the following conditions are included: 31) The groove depth is 40 to 400 nm; 32) The groove width is 0.5 to 10 μm; 33) The etching is plasma etching; 34) The etching line width is 0.5 to 10 μm; 35) The etching depth is through the protective layer, metal electrode, injection layer, hole transport layer and perovskite layer or through the protective layer, metal electrode, injection layer, hole transport layer and perovskite layer and over-etched to 0% to 20% of the thickness of the electron transport layer; 36) The etching angle γ is 45 to 90°; 37) After etching, a rectangular groove or a trapezoidal groove is formed; preferably, the width L3 of the trapezoidal groove or the rectangular groove on the surface of the protective layer is 0.5 to 10 μm; preferably, the number of the rectangular grooves or the trapezoidal grooves is 5 to 500; preferably, the gap between adjacent rectangular grooves or trapezoidal grooves is 0 to 0.1 mm; 38) The thickness of the protective layer is 50 to 500 nm.

5. The method for preparing a large-area perovskite battery module according to claim 1, characterized in that: Also includes any one or more of the following conditions: A) In step P2, the injection layer is a metal oxide layer or a nitride layer; preferably, the metal oxide in the metal oxide layer is selected from molybdenum oxide, aluminum oxide, nickel oxide or silicon oxide; preferably, the nitride in the nitride layer is a silicon nitrogen compound; more preferably, the ratio of nitrogen to silicon in the silicon nitrogen compound is 5:1 to 1:5; B) In the P3 process, the protective layer is a metal oxide layer or a nitride layer; preferably, the metal oxide in the metal oxide layer is selected from molybdenum oxide, aluminum oxide, nickel oxide or silicon oxide; preferably, the nitride in the nitride layer is a nitrogen silicon compound; more preferably, the nitrogen-silicon ratio in the nitrogen silicon compound is 5:1 to 1:

5.

6. A large-area perovskite battery module with ultra-high geometric filling rate, characterized in that: The large-area perovskite battery module with ultra-high geometric filling rate is prepared by the method described in any one of claims 1 to 5.

7. The large-area perovskite battery module according to claim 6, characterized in that: The perovskite battery comprises an electron transport layer, a perovskite layer, a hole transport layer, an injection layer, a metal electrode, and a protective layer in sequence from the substrate in a direction away from the substrate.

8. The large-area perovskite battery module according to claim 6, characterized in that: The perovskite cell includes any one or more of the following conditions: 1) The length of the large-area perovskite battery module ranges from 2.0 to 200 cm; 2) The width of the large-area perovskite battery module ranges from 2.0 to 200 cm; 3) The number of sub-batteries in the large-area perovskite battery module is 5 to 100; 4) The width of the sub-cell of the large-area perovskite battery module is 3 to 10 mm; 5) The GFF of the large-area perovskite battery module is between 99.70% and 99.99%; 6) The yield rate of the large-area perovskite battery module is above 90%.

9. Use of the large-area perovskite battery module according to any one of claims 6 to 8 in the preparation of photovoltaic modules.

10. A photovoltaic module, characterized in that: The photovoltaic module contains the large-area perovskite battery module described in any one of claims 6 to 8.

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