Low-power-consumption power-on reset circuit applied to vehicle gauge chip

Abstract

The invention discloses a low-power-consumption power-on reset circuit applied to a vehicle gauge chip. The low-power-consumption power-on reset circuit comprises a biasing circuit, a starting circuit and a power-on reset circuit body. When the power-on reset circuit is powered on, the starting circuit starts to work, output of a fourth node in the power-on reset circuit is forcibly set to be high level through a starting signal, and the power-on reset circuit outputs a reset signal; after the biasing circuit is started, a first current source and a second current source in the power-on reset circuit are controlled to start working, a third node in the power-on reset circuit starts to be charged, and after the third node is charged to be higher than the break-over voltage, the power-on reset circuit starts to execute reset judgment logic.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a low-power power-on reset circuit applied to automotive chips. Background Art

[0002] During the chip startup process, the power supply voltage gradually rises from 0 to the rated value. In this process, the internal circuit of the chip may be unstable, causing the chip to work in an incorrect state or even damage the internal circuit of the chip. Therefore, the chip must generate a reset signal when powered on to reset the key circuit when the power supply does not reach the working threshold, so that the chip can work stably.

[0003] In automotive applications, the power supply conditions are more complex, and the requirements for automotive-grade chips are second only to military-grade chips, which place extremely high demands on safety and stability. In the face of possible large fluctuations in power supply, the chip must ensure high reliability and actively reset the circuit when the power supply voltage is too low to prevent the chip from entering an uncontrollable error state. Normally, this circuit must always work to ensure the functional safety of the chip, so low power consumption is also one of the important design indicators.

[0004] Figure 1 A power-on reset circuit in the prior art is shown, which is composed of a resistor, a MOS tube, a comparator, and a bias circuit. When the power supply voltage is low, due to the threshold voltage of the MOS tube, the voltage at point B will be lower than the voltage at point A, the comparator outputs a high level, and the circuit enters a reset state. However, in addition to the bias circuit that works at a low voltage, the power-on reset circuit also includes a comparator that works at a low voltage. Usually, the anti-interference ability of the comparator is weak, the calculation accuracy is easily affected by factors such as temperature, and the stability is poor. In addition, the circuit area of ​​the resistor network and the comparator of the power-on reset circuit is relatively large, which affects the miniaturization design of the chip, and the cost of the comparator is relatively high. In addition, the on-current in the circuit composed of the resistor and the MOS tube and the power consumption of the comparator always exist, resulting in relatively large power consumption. Therefore, when designing a chip, it is necessary to consider the power consumption and circuit area, which limits the chip performance. Summary of the invention

[0005] In order to solve the above defects in the prior art, the present invention proposes a low-power power-on reset circuit applied to automotive chips, which has the characteristics of low power consumption, low cost and high stability.

[0006] The technical solution of the present invention is as follows: The present invention proposes a low-power power-on reset circuit for automotive chips, comprising: a bias circuit, a startup circuit and a power-on reset circuit. When powered on, the startup circuit starts working, the startup circuit outputs a startup signal, the output of the fourth node in the power-on reset circuit is forced to be high, the logic output is high, and the power-on reset circuit outputs a reset signal; When the bias circuit is started up, the first current source and the second current source in the power-on reset circuit are controlled to start working, and the third node in the power-on reset circuit starts to charge. After the third node is charged to a voltage above the conduction voltage, the power-on reset circuit starts to execute the reset judgment logic.

[0007] The reset judgment logic includes: When the voltage of the third node in the power-on reset circuit is less than the predetermined voltage, the fourth node outputs a high level, the logic output is high, and the power-on reset circuit outputs a reset signal; When the voltage of the third node is higher than the predetermined voltage, the fourth node outputs a low level, and the logic output is low, indicating that the reset is completed.

[0008] When the startup circuit is working, it is determined whether to lower the voltage in the bias circuit according to the voltage of the first node in the startup circuit. When the voltage on the first node is 0, the pull-down branch in the startup circuit pulls down the voltage in the bias circuit, forcing current to flow into the bias circuit. When there is current in the bias circuit, when the voltage of the first node is charged to a predetermined startup level, it means that the bias circuit has completed startup and the startup circuit is turned off.

[0009] The bias circuit includes PMOS tubes PM5, PM6, NMOS tubes NM5, NM6, and a first resistor R1; The sources of PM5 and PM6 are connected to the power supply voltage Vdda, the gates of PM5 and PM6 are connected to the drain of PM5, the drains of PM5 and PM6 are connected to the drains of NM5 and NM6 respectively, the gates of NM5 and NM6 are connected to the drain of NM6, the source of NM5 is grounded through the first resistor R1, and the source of NM6 is grounded.

[0010] PM5 and PM6 form a P-type current mirror.

[0011] The startup circuit includes PMOS tubes PM7, PM8, NMOS tubes NM7, NM8, NM9, a second resistor R2, a first capacitor C1, and a first Schmitt trigger. The sources of PM7 and PM8 are connected to the power supply voltage Vdda, the gates of PM7 and PM8 are connected to the drain of PM7, the drains of PM7 and PM8 are connected to the drains of NM7 and NM8 respectively, the gate of NM7 is connected to the drain of NM6, the gate of NM8 is grounded, the sources of NM7 and NM8 are grounded, the drain of NM8 is also connected to the input of the first Schmitt trigger to form a first node, the output of the first Schmitt trigger is connected to the gate of NM9, the drain of NM9 is connected to the drain of PM5, the source of NM9 is grounded through the second resistor R2, and the drain of NM8 is also grounded through the first capacitor C1.

[0012] PM7 and PM8 form a P-type current mirror, and NM6 and NM7 form an N-type current mirror.

[0013] The power-on reset circuit includes PMOS tubes PM1, PM2, PM3, PM4, PM9, NMOS tubes NM1, NM2, NM3, NM4, a second capacitor C2, a first NOT gate NOT1, a second Schmitt trigger, a second NOT gate NOT2, and a third NOT gate NOT3. The source of PM9 is connected to the power supply voltage Vdda, the gate of PM9 is connected to the drain of PM7, the drain of PM9 is connected to the source of PM3, the gate of PM3 is connected to the drain of NM8, the input terminal of the first NOT gate NOT1 and the gate of NM3, the drain of PM3 is connected to the drain of NM3 to form a second node, the source of NM3 is grounded, and the drain of NM3 is also grounded through the second capacitor C2, the sources of PM1, PM2 and PM4 are connected to the power supply voltage Vdda, the gates of PM1 and PM2 are connected to the drain of PM2 and the gate of NM1 to form a third node, the drain of PM2 is connected to the The drain of PM1 is connected to the gate of NM2, the gate of NM2 is connected to the drain of NM3, the source of NM2 is grounded, the gate of PM4 is connected to the output of the first NOT gate NOT1, the output of the second Schmitt trigger is connected to the input of the second NOT gate NOT2, the output of the second NOT gate NOT2 is connected to the input of the third NOT gate NOT3, and the output of the third NOT gate NOT3 outputs a reset signal por.

[0014] NM6 and NM4 form an N-type current mirror, NM4 forms a first current source I1, and PM9 forms a second current source I2.

[0015] The sizes of the PMOS tubes PM1, PM2, PM5, PM6, PM7, PM8, and PM9 are proportional, and the sizes of the NMOS tubes NM1, NM4, NM5, NM6, and NM7 are proportional.

[0016] Compared with the traditional power-on reset circuit, the present invention reduces the use of large resistors and eliminates the comparator on the basis of achieving the same performance, thereby greatly reducing power consumption and cost while reducing the circuit area.

[0017] The features and advantages of the present invention will become clear through reference to the following drawings and detailed description of specific embodiments of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A circuit diagram of a conventional power-on reset circuit is shown.

[0019] Figure 2 The specific circuit diagram of the power-on reset circuit of the present invention is shown.

[0020] Figure 3 The schematic diagram of the power-on reset circuit of the present invention is shown.

[0021] Figure 4 The simulation waveform diagram of the power-on reset circuit of the present invention is shown. DETAILED DESCRIPTION

[0022] In order to make the technical solution of the present invention clearer and more understandable, the following will be further described in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. Figures 2 to 4 The present invention is described in detail.

[0023] Figure 2 The specific circuit diagram of the power-on reset circuit of the present invention is shown. The power-on reset circuit of the present invention comprises a bias circuit, a start-up circuit and a power-on reset circuit.

[0024] The bias circuit includes PMOS tubes PM5 and PM6, NMOS tubes NM5 and NM6, and a first resistor R1. The sources of PM5 and PM6 are connected to the power supply voltage Vdda, the gates of PM5 and PM6 are connected to the drain of PM5, the drains of PM5 and PM6 are respectively connected to the drains of NM5 and NM6, the gates of NM5 and NM6 are connected to the drain of NM6, the source of NM5 is grounded through the first resistor R1, and the source of NM6 is grounded. PM5 and PM6 form a P-type current mirror.

[0025] The startup circuit includes PMOS tubes PM7, PM8, NMOS tubes NM7, NM8, NM9, a second resistor R2, a first capacitor C1, and a first Schmitt trigger. The sources of PM7 and PM8 are connected to the power supply voltage Vdda, the gates of PM7 and PM8 are connected to the drain of PM7, the drains of PM7 and PM8 are connected to the drains of NM7 and NM8 respectively, the gate of NM7 is connected to the drain of NM6, the gate of NM8 is grounded, and the sources of NM7 and NM8 are grounded. The drain of NM8 is also connected to the input end of the first Schmitt trigger to form a first node D, the output end of the first Schmitt trigger is connected to the gate of NM9, the drain of NM9 is connected to the drain of PM5, and the source of NM9 is grounded through the second resistor R2. The drain of NM8 is also grounded through the first capacitor C1. PM7 and PM8 form a P-type current mirror, and NM6 and NM7 form an N-type current mirror.

[0026] The power-on reset circuit includes PMOS tubes PM1, PM2, PM3, PM4, PM9, NMOS tubes NM1, NM2, NM3, NM4, a second capacitor C2, a first NOT gate NOT1, a second Schmitt trigger, a second NOT gate NOT2, and a third NOT gate NOT3. The source of PM9 is connected to the power supply voltage Vdda, the gate of PM9 is connected to the drain of PM7, the drain of PM9 is connected to the source of PM3, and PM9 forms a second current source I2. The gate of PM3 is connected to the drain of NM8, the input end of the first NOT gate NOT1 and the gate of NM3, the drain of PM3 is connected to the drain of NM3 to form a second node A, and the source of NM3 is grounded. The drain of NM3 is also grounded through the second capacitor C2. The sources of PM1, PM2, and PM4 are connected to the power supply voltage Vdda, the gates of PM1 and PM2 are connected to the drain of PM2 and the gate of NM1 to form a third node B, the drain of PM2 is connected to the drain of NM4, the gate of NM4 is connected to the gate of NM6, and the source of NM4 is grounded. NM6 and NM4 form an N-type current mirror, and NM4 forms a first current source I1. The drain of PM1 is connected to the drains of NM1 and NM4 and the input of the second Schmitt trigger to form a fourth node C, the source of NM1 is connected to the drain of NM2, the gate of NM2 is connected to the drain of NM3, the source of NM2 is grounded, the gate of PM4 is connected to the output of the first NOT gate NOT1, the output of the second Schmitt trigger is connected to the input of the second NOT gate NOT2, the output of the second NOT gate NOT2 is connected to the input of the third NOT gate NOT3, and the output of the third NOT gate NOT3 outputs a reset signal por. The output end of the second NOT gate NOT2 also outputs a signal porb which is inverted from the reset signal, and can be provided to an external circuit for use when needed.

[0027] In the figure, the sizes of PMOS tubes PM1, PM2, PM5, PM6, PM7, PM8, and PM9 are proportional, and the sizes of NMOS tubes NM1, NM4, NM5, NM6, and NM7 are proportional.

[0028] The MOS tube NM6 in the bias circuit of the present invention and the MOS tube NM7 in the startup circuit form a bandgap reference mirror image, NM7 is a mirrored current source, PM7 and PM8 form a current mirror, and when the startup circuit is working, the first capacitor C1 is charged, and the voltage at point D is determined whether to pull down the gate / drain voltage of PM5 in the bias circuit. The bandgap reference mirror outputs a current to the startup circuit. When powered on, the bandgap reference mirror output current is 0, and the first capacitor C1 cannot be charged, and the voltage at point D is 0. At this time, in order to start, the gate / drain of PM5 is pulled down by the pull-down branch composed of NM9 and the second resistor R2 in the startup circuit, and current is forced to be injected into the bias circuit. When there is current in the bias circuit, the bandgap reference mirror outputs current, and the first capacitor C1 is slowly charged to a predetermined startup level. The voltage at point D follows the power supply voltage, indicating that the bias circuit has completed startup and the startup circuit is closed. After the startup circuit is closed, the power-on reset circuit starts to work, and the specific principle will be described below.

[0029] In addition, NM8 is a device with large leakage. Its function is to lower the voltage at point D when the bias circuit falls into a zero current state due to abnormal interference, restart the circuit, and improve the reliability of the circuit.

[0030] Figure 3 The schematic diagram of the power-on reset circuit of the present invention is shown. The working principle of the power-on reset circuit of the present invention is explained below.

[0031] When powered on, the startup circuit of the bias circuit starts working, and the node D in the startup circuit outputs a startup signal. The output of point C is forced to be high through MOS tubes PM3, PM4, and NM3, and the logic output is high, and a reset signal is output. When the bias circuit is started, the N-type current source I1 and the P-type current source I2 that control the same current start working, and node A starts charging. After node A is charged to a voltage above the conduction voltage Vth, NM2 is turned on, and the power-on reset circuit starts to execute the reset judgment logic.

[0032] PM2 is connected in the form of a diode, that is, the gate is connected to the drain, then the voltage at point B is (Vdda-Vgsp), where Vgsp is the gate-source voltage of the P-type current mirror. When the power supply voltage is low, the voltage at point B is less than Vgsn, where Vgsn is the gate-source voltage of the N-type current mirror. Then the current flowing through PM1 is greater than the current flowing through NM1, and point C outputs a high level, the logic output is high, and a reset signal is output. When the power supply voltage gradually rises to the point B voltage equal to Vgsn, the output at point C is in an intermediate state. Due to the characteristics of the Schmitt trigger, the logic output remains high. When the power supply voltage rises to a large enough level, the voltage at point B is higher than Vgsn. At this time, point C outputs a low level, and the logic output is low, indicating that the reset is over. At this time, the power supply voltage is sufficient to ensure the correct operation of the circuit logic.

[0033] Furthermore, when the power supply voltage suddenly decreases, there are two possible situations.

[0034] In the first case, the power supply voltage drops to a voltage where the logic circuit and bias circuit can still work, such as about 1V. At this time, the voltage at point B drops below Vgsn, and the output at point C is pulled up from a low level to a high level, outputting a reset signal. When the power supply voltage rises sufficiently, the voltage at point B is higher than Vgsn, and point C outputs a low level, and the reset ends.

[0035] The second situation is that the power supply voltage drops to a voltage where the logic circuit and bias circuit cannot work, such as about 500mV. At this time, all points may be in an unstable state, but when the power supply voltage rises again, the above power-on reset process is repeated. First, the startup circuit in the bias circuit starts to work, and the output of point C is forced to be high, and a reset signal is output. After the bias circuit is started, the voltage at point B gradually rises from less than Vgsn to higher than Vgsn, and point C changes from outputting high level to outputting low level, and the reset ends.

[0036] In the present invention, PM1 and PM2 are proportional to the size (channel width-to-length ratio) of the P-type current mirror in the bias circuit, and NM1 is proportional to the size of the N-type current mirror, thereby controlling the power supply voltage that meets the working conditions within a certain range, further reducing power consumption.

[0037] When the power supply voltage is stable, since the MOS tubes PM1 and PM2 are proportional to the size of the P-type current mirror in the bias circuit, the static currents of these two paths are stable and controllable, depending on the bias current of the bias circuit. In this way, the static current can be controlled within a smaller range, thereby reducing power consumption.

[0038] Compared with the resistors used in the power-on reset circuit in the prior art, the resistance values ​​of the resistors R1 and R2 in the present invention are smaller, which further reduces the power consumption.

[0039] Figure 4The simulation waveform of the power-on reset circuit of the present invention is shown. The simulation experiment results prove that the power-on reset effect is stable when the power supply voltage suddenly decreases. In addition, the circuit area of ​​the present invention is reduced by 40% compared with the traditional power-on reset circuit, and the static current is less than 200nA under standard conditions, which significantly reduces power consumption.

[0040] The power-on reset circuit of the present invention can be applied to automotive-grade chips, and has the advantages of low power consumption, low cost, and high stability, thereby effectively ensuring the safety and reliability of the automotive-grade chips from power-on to smoothly entering the normal working state and the subsequent working process, and can meet the relevant requirements of automotive-grade chips.

[0041] The above description is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the concept of the present invention, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A low-power power-on reset circuit for automotive chips, comprising: Bias circuit, startup circuit and power-on reset circuit, When powered on, the startup circuit starts working, the startup circuit outputs a startup signal, the output of the fourth node in the power-on reset circuit is forced to be high, the logic output is high, and the power-on reset circuit outputs a reset signal; When the bias circuit is started, the first current source and the second current source in the power-on reset circuit are controlled to start working, and the third node in the power-on reset circuit starts to charge. After the third node is charged to a voltage above the conduction voltage, the power-on reset circuit starts to execute the reset judgment logic, wherein: The power-on reset circuit includes PMOS tubes PM1, PM2, PM3, PM4, PM9, NMOS tubes NM1, NM2, NM3, NM4, a second capacitor C2, a first NOT gate NOT1, The source of PM9 is connected to the power supply voltage Vdda, the gate of PM9 is connected to the drain of PM7, the drain of PM9 is connected to the source of PM3, the gate of PM3 is connected to the drain of NM8, the input end of the first NOT gate NOT1 and the gate of NM3, the drain of PM3 is connected to the drain of NM3 to form a second node, the source of NM3 is grounded, and the drain of NM3 is also grounded through the second capacitor C2, the sources of PM1, PM2 and PM4 are connected to the power supply voltage Vdda, P The gates of M1 and PM2 are connected to the drain of PM2 and the gate of NM1 to form a third node, the drain of PM2 is connected to the drain of NM4, the gate of NM4 is connected to the gate of NM6, the source of NM4 is grounded, the drain of PM1 is connected to the drains of NM1 and NM4 to form a fourth node, the source of NM1 is connected to the drain of NM2, the gate of NM2 is connected to the drain of NM3, the source of NM2 is grounded, and the gate of PM4 is connected to the output end of the first NOT gate NOT1. The sizes of the PMOS tubes PM1, PM2, PM5, PM6, PM7, PM8, and PM9 are proportional, and the sizes of the NMOS tubes NM1, NM4, NM5, NM6, and NM7 are proportional.

2. The power-on reset circuit according to claim 1, wherein: The power-on reset circuit also includes a second Schmitt trigger, a second NOT gate NOT2, and a third NOT gate NOT3. The drain of PM1 is connected to the input of the second Schmitt trigger, the output of the second Schmitt trigger is connected to the input of the second NOT gate NOT2, the output of the second NOT gate NOT2 is connected to the input of the third NOT gate NOT3, and the output of the third NOT gate NOT3 outputs a reset signal por.

3. The power-on reset circuit according to claim 2, wherein: NM6 and NM4 form an N-type current mirror, NM4 forms a first current source I1, and PM9 forms a second current source I2.

4. The power-on reset circuit according to claim 1, wherein: The reset judgment logic includes: When the voltage of the third node in the power-on reset circuit is less than the predetermined voltage, the fourth node outputs a high level, the logic output is high, and the power-on reset circuit outputs a reset signal; When the voltage of the third node is higher than the predetermined voltage, the fourth node outputs a low level, and the logic output is low, indicating that the reset is completed.

5. The power-on reset circuit according to claim 1, wherein: When the startup circuit is working, it is determined whether to lower the voltage in the bias circuit according to the voltage of the first node in the startup circuit. When the voltage on the first node is 0, the pull-down branch in the startup circuit pulls down the voltage in the bias circuit, forcing current to flow into the bias circuit. When there is current in the bias circuit, when the voltage of the first node is charged to a predetermined startup level, it means that the bias circuit has completed startup and the startup circuit is turned off.

6. The power-on reset circuit according to claim 1, 4 or 5, wherein: The bias circuit includes PMOS tubes PM5, PM6, NMOS tubes NM5, NM6, and a first resistor R1; The sources of PM5 and PM6 are connected to the power supply voltage Vdda, the gates of PM5 and PM6 are connected to the drain of PM5, the drains of PM5 and PM6 are connected to the drains of NM5 and NM6 respectively, the gates of NM5 and NM6 are connected to the drain of NM6, the source of NM5 is grounded through the first resistor R1, and the source of NM6 is grounded.

7. The power-on reset circuit according to claim 6, wherein: PM5 and PM6 form a P-type current mirror.

8. The power-on reset circuit according to claim 7, wherein: The startup circuit includes PMOS tubes PM7, PM8, NMOS tubes NM7, NM8, NM9, a second resistor R2, a first capacitor C1, and a first Schmitt trigger. The sources of PM7 and PM8 are connected to the power supply voltage Vdda, the gates of PM7 and PM8 are connected to the drain of PM7, the drains of PM7 and PM8 are connected to the drains of NM7 and NM8 respectively, the gate of NM7 is connected to the drain of NM6, the gate of NM8 is grounded, the sources of NM7 and NM8 are grounded, the drain of NM8 is also connected to the input of the first Schmitt trigger to form a first node, the output of the first Schmitt trigger is connected to the gate of NM9, the drain of NM9 is connected to the drain of PM5, the source of NM9 is grounded through the second resistor R2, and the drain of NM8 is also grounded through the first capacitor C1.

9. The power-on reset circuit according to claim 8, wherein: PM7 and PM8 form a P-type current mirror, and NM6 and NM7 form an N-type current mirror.

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