Method and device for optimizing chip packaging design, storage medium and electronic equipment

Abstract

The invention discloses a chip packaging design optimization method and device, a storage medium and electronic equipment. The method comprises the steps that circuit and material parameter information, packaging parameter information and chip heat management parameter information are acquired; and performing thermal simulation and stress action simulation based on the circuit and material parameter information, the packaging parameter information, the chip thermal management parameter information and the actual function yield of the chip, so as to determine a circuit wiring design, a pin position and a target lamination or arrangement position of the chip according to simulation results of thermal simulation and stress simulation. According to the optimization method provided by the invention, the reliability and the quality of chip packaging can be improved.

Description

Technical Field

[0001] The present application relates to the field of chip packaging technology, and in particular to a chip packaging design optimization method, a computer-readable storage medium, an electronic device, and a chip packaging design optimization device. Background Art

[0002] In the field of semiconductor packaging, the matching of the protective layer circuit and material, the chip back process circuit and material, the circuit bump circuit and material, the carrier layer circuit and material, and the cooling system material is crucial. Mismatches between these components and materials may lead to a variety of problems. For example, the mismatch between the protective layer circuit and material may cause the protective layer to be unable to effectively disperse or absorb the heat generated by the chip, resulting in local overheating. The mismatch between the chip back process circuit and material may lead to low thermal conduction efficiency, making it impossible to evenly distribute heat, resulting in local hot spots. The circuit bump is the key to connecting the chip to the external circuit. Material mismatch may cause the thermal expansion between the bump and the chip or package substrate to be out of sync, causing mechanical stress. The carrier layer is the basis for supporting the entire chip structure. Material mismatch may cause the carrier layer to be unable to evenly disperse heat, affecting the thermal stability of the entire package. The mismatch between the cooling system material and the chip or other components may lead to low thermal conduction efficiency and inability to effectively conduct heat away from the heat source.

[0003] Due to the mismatch between the above materials and circuits, when the circuit is powered on, the difference in thermal expansion coefficients of different materials will cause internal thermal stress. Under the influence of thermal stress for a long time, the circuit may deform, break or degrade in performance, resulting in package failure or shortened life. Summary of the invention

[0004] The present application aims to solve at least one of the technical problems in the related art to a certain extent. To this end, the first purpose of the present application is to propose a chip packaging design optimization method, obtain circuit and material parameter information, packaging parameter information and chip thermal management parameter information, perform thermal simulation and stress simulation based on the circuit and material parameter information, packaging parameter information, chip thermal management parameter information and the actual functional yield of the chip, and determine the circuit wiring design and pin position and the target stacking or arrangement position of the chip according to the simulation results of the thermal simulation and stress simulation, thereby improving the reliability and quality of the chip packaging.

[0005] A second object of the present application is to provide a computer-readable storage medium.

[0006] The third objective of the present application is to provide an electronic device.

[0007] The fourth objective of the present application is to provide a device for optimizing chip packaging design.

[0008] To achieve the above-mentioned objectives, the first aspect of the present application proposes a method for optimizing chip packaging design, the method comprising: obtaining circuit and material parameter information, packaging parameter information and chip thermal management parameter information; performing thermal simulation and stress action simulation based on the circuit and material parameter information, the packaging parameter information, the chip thermal management parameter information and the actual functional yield of the chip, so as to determine the circuit wiring design and pin position and the target stacking or arrangement position of the chip according to the simulation results of the thermal simulation and stress simulation.

[0009] According to the chip packaging design optimization method of the embodiment of the present application, circuit and material parameter information, packaging parameter information and chip thermal management parameter information are obtained, and thermal simulation and stress action simulation are performed based on the circuit and material parameter information, packaging parameter information, chip thermal management parameter information and the actual functional yield of the chip, so as to determine the circuit wiring design and pin position and the target stacking or arrangement position of the chip according to the simulation results of the thermal simulation and stress simulation. Therefore, the method can improve the reliability and quality of chip packaging.

[0010] In addition, the chip package design optimization method according to the above embodiment of the present application may also have the following additional technical features:

[0011] According to an embodiment of the present application, the obtaining of circuit and material parameter information includes: obtaining protection layer circuit and material information, chip back side process circuit and material information, circuit bump circuit and material information, and carrier circuit and material information.

[0012] According to an embodiment of the present application, the obtaining of packaging parameter information includes: obtaining packaging material information, wafer stacking packaging information, and bottom filling material information.

[0013] According to an embodiment of the present application, obtaining chip thermal management parameter information includes: obtaining heat dissipation structure and packaging information.

[0014] According to one embodiment of the present application, the thermal simulation and stress action simulation are performed based on the circuit and material parameter information, the packaging parameter information, the chip thermal management parameter information and the actual functional yield of the chip to determine the circuit wiring design and pin position and the target stacking or arrangement position of the chip according to the simulation results of the thermal simulation and stress simulation, and also includes: based on the comparison result of the chip functional yield obtained after the simulation and the actual functional yield, the circuit wiring design and pin position and the target stacking or arrangement position of the chip are optimized.

[0015] According to one embodiment of the present application, the method also includes: obtaining the test probe chip probe point coordinates and test information; performing thermal simulation and stress action simulation based on the test probe chip probe point coordinates and test information, circuit and material parameter information, the packaging parameter information, the chip thermal management parameter information and the actual functional yield of the chip, so as to determine the circuit wiring design and pin position and the target stacking or arrangement position of the chip according to the simulation results of the thermal simulation and stress simulation.

[0016] According to one embodiment of the present application, the method further includes: optimizing the passivation layer, the redistribution layer, the type and material of the bumps, the packaging type and material, the position of the stacked integrated circuits, the material of the carrier or the interposer, and the heat dissipation device based on the simulation results.

[0017] To achieve the above objectives, a second aspect of the present application provides a computer-readable storage medium having a program stored thereon, which implements the above-mentioned chip packaging design optimization method when executed by a processor.

[0018] According to the computer-readable storage medium of the embodiment of the present application, by implementing the above-mentioned chip packaging design optimization method during execution, the reliability and quality of the chip packaging can be improved.

[0019] To achieve the above-mentioned purpose, an electronic device proposed in the third aspect embodiment of the present application includes a memory, a processor, and a program stored in the memory and executable on the processor, and when the processor executes the program, the above-mentioned chip packaging design optimization method is implemented.

[0020] According to the electronic device of the embodiment of the present application, the reliability and quality of the chip packaging can be improved by executing the above-mentioned chip packaging design optimization method.

[0021] To achieve the above-mentioned objectives, the fourth aspect embodiment of the present application proposes a chip packaging design optimization device, which includes: an acquisition module for acquiring circuit and material parameter information, packaging parameter information and chip thermal management parameter information; a design module for performing thermal simulation and stress simulation based on the circuit and material parameter information, the packaging parameter information, the chip thermal management parameter information and the functional yield of the chip, so as to determine the circuit wiring design and pin position and the target stacking or arrangement position of the chip according to the simulation results of the thermal simulation and stress simulation.

[0022] According to the chip packaging design optimization device of the embodiment of the present application, the acquisition module is used to acquire circuit and material parameter information, packaging parameter information and chip thermal management parameter information, and the design module is used to perform thermal simulation and stress simulation based on the circuit and material parameter information, the packaging parameter information, the chip thermal management parameter information and the functional yield of the chip, so as to determine the circuit wiring design and the pin position and the target stacking or arrangement position of the chip according to the simulation results of the thermal simulation and stress simulation. Thus, the device can improve the reliability and quality of chip packaging.

[0023] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A flowchart of a chip package design optimization method according to an embodiment of the present application;

[0025] Figure 2 A flowchart of a chip package design optimization method according to a specific example of the present application;

[0026] Figure 3 is a block diagram of an electronic device according to an embodiment of the present application;

[0027] Figure 4 A block diagram of an optimization device for chip packaging design according to an embodiment of the present application. DETAILED DESCRIPTION

[0028] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0029] The following describes a chip package design optimization method, a computer-readable storage medium, an electronic device, and a chip package design optimization device proposed in an embodiment of the present application with reference to the accompanying drawings.

[0030] Figure 1 The present invention is a flowchart of a chip package design optimization method according to an embodiment of the present application.

[0031] like Figure 1 As shown, the chip package design optimization method of the embodiment of the present application may include the following steps:

[0032] S1, obtaining circuit and material parameter information, packaging parameter information and chip thermal management parameter information;

[0033] S2, performing thermal simulation and stress simulation based on circuit and material parameter information, packaging parameter information, chip thermal management parameter information and the actual functional yield of the chip, so as to determine the circuit wiring design and pin position and the target stacking or arrangement position of the chip according to the simulation results of the thermal simulation and stress simulation.

[0034] Specifically, first obtain circuit and material parameter information, packaging parameter information and chip thermal management parameter information. Among them, the circuit and material parameter information may include circuit parameters, such as collecting the electrical parameters of the circuit, including resistance, capacitance, inductance, voltage and current levels, and also include material properties, such as obtaining the physical properties of the material (such as conductivity, thermal conductivity), chemical stability, thermal properties (such as thermal conductivity, thermal expansion coefficient) and mechanical strength. The packaging parameter information may include the packaging structure, such as the geometric structure of the package, including size, shape and internal layout, and packaging material information, such as the thermal and mechanical properties of plastics, ceramics or metals. The chip thermal management parameter information may include heat dissipation structures and thermal interface materials, such as the materials and dimensions of heat sinks, heat pipes or heat spreaders, and the thermal conductivity of thermal interface materials.

[0035] After obtaining the circuit and material parameter information, packaging parameter information and chip thermal management parameter information, thermal simulation and stress simulation can be performed based on the circuit and material parameter information, packaging parameter information, chip thermal management parameter information and the actual functional yield of the chip. Among them, during thermal simulation, a detailed thermal simulation model of the chip and package can be constructed based on the collected parameter information, and the boundary conditions of the simulation can be set, including ambient temperature, heat source distribution, and heat dissipation conditions. Then, the thermal simulation is run to analyze the temperature distribution and heat flow path of the chip under different working conditions, and to evaluate the thermal stress caused by the mismatch between temperature gradient and thermal expansion coefficient. Stress simulation may include constructing a mechanical simulation model of the chip and package, considering different mechanical loads and support conditions, inputting mechanical properties such as elastic modulus, Poisson's ratio, yield strength, etc. of the material, running stress simulation, and analyzing the stress distribution and deformation of the chip and package under different mechanical conditions.

[0036] Therefore, by performing pseudo-thermal simulation and stress simulation, the heat distribution generated by the chip during operation is predicted through simulation technology, and the mechanical stress that the chip may encounter during manufacturing and use is simulated, such as thermal expansion or contraction caused by temperature changes. Therefore, the circuit wiring design and pin position as well as the target stacking or arrangement position of the chip can be determined based on the simulation results of thermal simulation and stress simulation. For example, the circuit wiring design can be optimized to reduce thermal resistance and electrical loss, improve signal integrity, determine the best pin position to reduce thermal stress and electrical interference, and determine the optimal stacking or arrangement position of the chip in the package based on the thermal and stress simulation results to achieve the best thermal management and mechanical stability.

[0037] This enables optimal thermal management and mechanical performance, improves chip performance and reliability, and helps reduce production costs and shorten product time to market.

[0038] Further, according to an embodiment of the present application, obtaining circuit and material parameter information includes: obtaining protective layer circuit and material information, chip back side process circuit and material information, circuit bump circuit and material information, and carrier circuit and material information.

[0039] Specifically, circuit and material parameter information is a key step in the design and manufacturing process of semiconductor packaging, and this information is essential to ensure the reliability, performance and life of the package. When obtaining circuit and material parameter information, the protective layer circuit and material information, the chip back process circuit and material information, the circuit bump circuit and material information, and the carrier circuit and material information can be obtained. Among them, the protective layer circuit information may include the layout of the protective layer circuit, the routing design, the electrical parameters of the circuit (such as resistance, capacitance, inductance), etc., and the protective layer material information may include material types, such as polymers, ceramics, glass, etc. The chip back process circuit and material information includes silicon, metal (aluminum, copper), etc. The circuit bump circuit information may include bump design, such as bump shape, size, layout, etc., and electrical connection, such as the connection method between the bump and the chip and the packaging substrate, and may also include electrical parameters, such as resistance and inductance of the bump. Circuit bump material information includes material types, such as copper, tin, gold, etc. The bearing circuit information may include the layout and routing design of the bearing layer circuit, and the bearing material information may include, for example, glass fiber reinforced epoxy resin substrate, BT (Bismaleimide-Triazine) resin, ceramics, etc.

[0040] For example, you can obtain relevant information by obtaining the technical specifications of the materials from the material supplier, or you can use simulation software to simulate the performance of the circuit and materials to predict their performance under actual working conditions. By combining this information, you can optimize the package design, ensure the match between the circuit and the material, and improve the overall performance and reliability of the package.

[0041] Further, according to an embodiment of the present application, obtaining packaging parameter information includes: obtaining packaging material information and wafer stacking packaging information and bottom filling material information.

[0042] Specifically, in the field of semiconductor packaging, obtaining packaging parameter information is a key step to ensure packaging reliability and performance. When obtaining packaging parameter information, packaging material information, wafer stacking packaging information and bottom filling material information can be obtained. Among them, packaging material information may include substrate material information, such as glass fiber reinforced epoxy resin substrate, BT resin, and packaging shell materials, such as plastic, ceramic, and may also include welding materials, conductive materials, etc. Wafer stacking packaging information includes wafer material, wafer size and layout (such as size including length, width and thickness, layout single layer, double layer or multi-layer stacking.) Wafer protective layer, such as silicon nitride, photoresist, etc. Bottom filling material information may include material type, such as epoxy resin, acrylic resin, etc., as well as thermal properties, electrical properties (such as dielectric constant, loss factor), chemical properties (such as moisture resistance, chemical corrosion resistance), etc.

[0043] For example, relevant information can be obtained by obtaining the technical specifications of the materials from the material supplier, or simulation software can be used to simulate the performance of circuits and materials to predict their performance under actual working conditions. By combining this information, the package design can be optimized to ensure the reliability and performance of the package, while reducing production costs and improving production efficiency.

[0044] Further, according to an embodiment of the present application, obtaining chip thermal management parameter information includes: obtaining heat dissipation structure and packaging information.

[0045] Specifically, in the process of semiconductor chip design and packaging, thermal management is a crucial link because it directly affects the performance, reliability and life of the chip. When obtaining chip thermal management parameter information, the heat dissipation structure and packaging information can be obtained. The heat dissipation structure design includes the shape, size, material and layout of the heat sink, as well as the contact method between the heat sink and the chip. The heat dissipation structure material may include the thermal conductivity of the material (the thermal conductivity of the material determines the efficiency of heat conduction), the thermal expansion coefficient (to ensure that the expansion of the heat dissipation structure matches that of the chip when the temperature changes) and the mechanical strength (to ensure the stability of the heat dissipation structure under mechanical pressure). The packaging information includes the packaging shell material, such as plastic, ceramic or metal. The packaging structure includes the connection between the chip and the package, the internal layout of the package, and the thermal characteristics of the package, such as thermal diffusivity (the thermal diffusivity of the packaging material affects the speed of heat propagation inside the package), heat capacity (the thermal capacity of the packaging material affects the response speed of the package to temperature changes) and thermal expansion coefficient (the thermal expansion coefficient of the packaging material affects the stability of the package when the temperature changes).

[0046] For example, relevant information can be obtained by obtaining the technical specifications of the materials from the material supplier, or simulation software can be used to simulate the performance of circuits and materials to predict their performance under actual working conditions. By combining this information, the heat dissipation design of the chip can be optimized to ensure that the chip can maintain good thermal management under various working conditions, thereby improving the performance and reliability of the chip.

[0047] According to one embodiment of the present application, thermal simulation and stress action simulation are performed based on circuit and material parameter information, packaging parameter information, chip thermal management parameter information and the actual functional yield of the chip to determine the circuit wiring design and pin position and the target stacking or arrangement position of the chip according to the simulation results of the thermal simulation and stress simulation, and also includes: based on the comparison result of the chip functional yield obtained after simulation and the actual functional yield, the circuit wiring design and pin position and the target stacking or arrangement position of the chip are optimized.

[0048] Specifically, after thermal simulation and stress simulation are performed based on circuit and material parameter information, packaging parameter information, chip thermal management parameter information, and the actual functional yield of the chip, the functional yield of the chip, including potential failure modes and failure rates, can be predicted based on the simulation results. The functional yield predicted by the simulation is compared with the actual functional yield to identify differences and deviations. Based on the comparison results, the circuit wiring design, pin position, and chip stacking or arrangement position are iteratively optimized. Design parameters such as wiring length, width, material selection, pin layout, and chip position are adjusted to improve the consistency between simulation and actual functional yield.

[0049] For example, when iteratively optimizing the circuit wiring design, if the simulation shows that there are hot spots in certain areas, re-route the wiring to disperse the heat, such as increasing the width of the trace or changing the trace path. For signal integrity issues such as crosstalk or reflection, adjust the routing to reduce these effects, which may include adding shielding, adjusting the trace spacing, or using different insulation materials. Optimize the layout of power and ground lines to provide stable power distribution and good signal grounding, and reduce noise and interference. When iteratively optimizing the pin position, based on the simulation results, adjust the pin position to optimize electrical performance, such as reducing impedance mismatch and signal delay. If certain pin areas are overheated, re-layout the pins to improve thermal distribution, which may involve changing the size of the pins or relocating them to move away from hot spots. Consider the impact of pin position on mechanical stress and ensure that the pin layout does not cause excessive bending or stress concentration. For iterative optimization of chip stacking or arrangement position, based on the comparison results, adjust the chip stacking or arrangement position to optimize the thermal distribution of the overall package to ensure that the heat is evenly distributed and effectively conducted to the heat dissipation structure. Consider the impact of chip stacking or arrangement position on the mechanical stability of the package to ensure stability under temperature changes and mechanical shocks, and optimize chip position to reduce signal transmission delays and improve signal integrity, especially in high-speed or high-frequency applications.

[0050] Therefore, through this iterative optimization process, the performance of circuit wiring design, pin position and chip stacking or arrangement position can be gradually improved, ultimately achieving the goal of improving chip functional yield and overall packaging performance.

[0051] According to one embodiment of the present application, the chip packaging design optimization method also includes: obtaining the test probe chip probe point coordinates and test information; performing thermal simulation and stress action simulation based on the test probe chip probe point coordinates and test information, circuit and material parameter information, packaging parameter information, chip thermal management parameter information and the actual functional yield of the chip, so as to determine the circuit wiring design and pin position and the target stacking or arrangement position of the chip according to the simulation results of the thermal simulation and stress simulation.

[0052] Specifically, the coordinates of the test probe chip probe points and test information are obtained, wherein precision measuring equipment, such as a confocal microscope or a laser scanning microscope, can be used to obtain the precise coordinates of the chip probe points, and record the X, Y and Z coordinates of each probe point. Test information collection includes electrical testing, which is performed to collect parameters such as resistance, capacitance, and inductance of the probe points. Functional testing, which performs functional tests to verify the electrical functions and performance of each probe point. It also includes fault analysis, which records the failure mode and failure rate of the probe point, especially the test conditions when the failure occurs. Thus, the probe point coordinates and test information can be integrated with circuit, material, packaging and thermal management parameter information to build a comprehensive simulation model, including circuit wiring, packaging structure and thermal management components.

[0053] According to the thermal characteristics and packaging parameters of the chip, the boundary conditions and heat sources of the thermal simulation model are set, and the thermal simulation is run to analyze the temperature distribution and hot spots of the chip under different working conditions, and to evaluate the thermal stress caused by the mismatch of temperature gradient and thermal expansion coefficient. According to the material properties of the package and chip, the boundary conditions and loads of the mechanical simulation model are set, and the stress simulation is run to analyze the stress distribution and deformation of the chip and package under different mechanical conditions, and to predict the fatigue life and potential fracture risk caused by cyclic stress. Therefore, according to the thermal simulation results, the circuit wiring can be adjusted to reduce hot spots and thermal resistance, optimize the signal transmission path, optimize the wiring to reduce crosstalk, reflection and signal delay, and improve signal integrity.

[0054] When optimizing the pin position, the pin position can be adjusted based on the electrical test results to optimize the electrical performance, reduce impedance mismatch and signal delay, and consider the impact of the pin position on heat distribution, optimize the layout to improve thermal management. When optimizing the chip stacking or arrangement position, adjust the chip stacking or arrangement position to optimize the overall package heat distribution, and consider the impact of the chip position on the mechanical stability of the package to ensure stability under temperature changes and mechanical shocks.

[0055] Therefore, the chip packaging design is optimized based on the test probe chip probe point coordinates and test information to ensure that the design meets the performance requirements and improve the functional yield of the chip. This not only improves the performance and reliability of the chip, but also helps to reduce production costs and shorten product time to market, providing solid technical support for patent claims.

[0056] According to one embodiment of the present application, the chip packaging design optimization method also includes: optimizing the passivation layer, the redistribution layer, the type and material of the bump, the packaging type and material, the position of the stacked integrated circuits, the material of the carrier or the intermediate layer, and the heat dissipation device based on the simulation results.

[0057] Specifically, the passivation layer protects the chip surface from physical damage and chemical corrosion, provides insulation properties, and prevents electrical short circuits. According to the simulation results, the passivation material with the best dielectric properties, chemical stability, and thermal stability, such as silicon dioxide (SiO2), silicon nitride (Si3N4), etc., can be selected, the thickness of the passivation layer can be adjusted to optimize the electrical insulation performance and mechanical protection capabilities, and the layout and opening design of the passivation layer can be adjusted according to the simulation results to reduce parasitic capacitance and improve signal integrity.

[0058] The redistribution layer can redistribute the I / O endpoints on the chip to adapt to the layout requirements of the package substrate. The line layout of the RDL can be optimized according to the simulation results to reduce resistance and capacitance and increase signal transmission speed. For example, copper or other conductive materials with low resistivity and good adhesion can be selected. As the electrical and mechanical connection between the chip and the package substrate, the type selection can be optimized, such as selecting the most suitable bump type according to the simulation results, such as solder bumps, copper pillar bumps, etc., and the material can be optimized, selecting materials with good conductivity and heat resistance, such as SnAgCu solder, and the geometric design can also be optimized, such as adjusting the geometry and size of the bump to optimize the contact area and mechanical strength.

[0059] The package type and material protect the chip, provide physical support, and achieve electrical connection. The package material can be optimized, such as selecting a package material with good thermal conductivity, mechanical strength, and electrical insulation, such as BT resin. The package structure design can be optimized, such as optimizing the package structure to improve thermal management efficiency and mechanical stability. The position of the stacked integrated circuits can be optimized in a multi-chip package to improve performance. For example, the position of the stacked integrated circuit can be adjusted based on the simulation results to minimize signal delay and power supply noise, and the thermal distribution of the stacked integrated circuit can be considered to optimize the layout to improve heat dissipation efficiency.

[0060] The material of the carrier or interposer provides physical support and electrical connection between the chip and the package substrate. The material selection can be optimized to select materials with good thermal conductivity and mechanical strength, such as silicon interposers or glass carriers. Or the design can be optimized to optimize the thickness and layout of the interposer to improve electrical performance and thermal management efficiency. Heat sinks can extract heat from the surface of the chip to keep the chip at a safe operating temperature. The heat dissipation structure can be optimized, such as designing efficient heat dissipation structures such as heat pipes, heat spreaders, or heat sinks based on simulation results. The material selection can also be optimized, such as selecting materials with high thermal conductivity, such as copper or aluminum.

[0061] This ensures that the chip package design achieves the best balance between electrical performance, thermal management, mechanical stability and cost-effectiveness.

[0062] Combine the following Figure 2 To describe the optimization method of this application.

[0063] As a specific example, the chip package design optimization method of the present application may include the following steps:

[0064] S101, obtaining circuit and material parameter information, packaging parameter information, and chip thermal management parameter information.

[0065] S102, obtaining the probe point coordinates and test information of the test probe chip.

[0066] S103, performing thermal simulation and stress simulation based on the test probe chip probe point coordinates and test information, circuit and material parameter information, packaging parameter information, chip thermal management parameter information and the actual functional yield of the chip, so as to determine the circuit wiring design and pin position and the target stacking or arrangement position of the chip according to the simulation results of the thermal simulation and stress simulation.

[0067] S104, optimizing the passivation layer, the redistribution layer, the type and material of the bumps, the package type and material, the position of the stacked integrated circuits, the material of the carrier or the interposer, and the heat dissipation device based on the simulation results.

[0068] S105 , based on the comparison result between the chip functional yield obtained after simulation and the actual functional yield, optimizing the circuit wiring design and the pin position as well as the target stacking or arrangement position of the chip.

[0069] In summary, according to the chip packaging design optimization method of the embodiment of the present application, circuit and material parameter information, packaging parameter information and chip thermal management parameter information are obtained, and thermal simulation and stress action simulation are performed based on the circuit and material parameter information, packaging parameter information, chip thermal management parameter information and the actual functional yield of the chip, so as to determine the circuit wiring design and pin position and the target stacking or arrangement position of the chip according to the simulation results of the thermal simulation and stress simulation. Therefore, the method can improve the reliability and quality of chip packaging.

[0070] Corresponding to the above embodiments, the present application also proposes a computer-readable storage medium.

[0071] The computer-readable storage medium of the embodiment of the present application stores a program, which, when executed by a processor, implements the above-mentioned chip packaging design optimization method.

[0072] According to the computer-readable storage medium of the embodiment of the present application, by executing the above-mentioned chip package design optimization method, the reliability and quality of the chip package can be improved.

[0073] Corresponding to the above embodiment, the present application also proposes an electronic device.

[0074] like Figure 3 As shown, the electronic device 200 of the embodiment of the present application may include: a memory 210, a processor 220, and a program stored in the memory 210 and executable on the processor 220. When the processor 220 executes the program, the above-mentioned chip packaging design optimization method is implemented.

[0075] According to the electronic device of the embodiment of the present application, the reliability and quality of the chip packaging can be improved by executing the above-mentioned chip packaging design optimization method.

[0076] Corresponding to the above embodiments, the present application also proposes a device for optimizing chip packaging design.

[0077] like Figure 4 As shown, the chip package design optimization device 100 of the embodiment of the present application includes: an acquisition module 110 and a design module 120.

[0078] The acquisition module 110 is used to acquire circuit and material parameter information, packaging parameter information and chip thermal management parameter information. The design module 120 is used to perform thermal simulation and stress simulation based on the circuit and material parameter information, the packaging parameter information, the chip thermal management parameter information and the functional yield of the chip, so as to determine the circuit wiring design and the pin position and the target stacking or arrangement position of the chip according to the simulation results of the thermal simulation and stress simulation.

[0079] According to an embodiment of the present application, the acquisition module 110 acquires circuit and material parameter information, specifically for: acquiring protection layer circuit and material information, chip back side process circuit and material information, circuit bump circuit and material information, and carrier circuit and material information.

[0080] According to an embodiment of the present application, the acquisition module 110 acquires packaging parameter information, specifically for: acquiring packaging material information, wafer stacking packaging information, and bottom filling material information.

[0081] According to an embodiment of the present application, the acquisition module 110 acquires chip thermal management parameter information, specifically for: acquiring heat dissipation structure and packaging information.

[0082] According to one embodiment of the present application, the design module 120 is also used to: perform thermal simulation and stress simulation based on circuit and material parameter information, packaging parameter information, chip thermal management parameter information and the actual functional yield of the chip, so as to determine the circuit wiring design and pin position and the target stacking or arrangement position of the chip according to the simulation results of the thermal simulation and stress simulation, and optimize the circuit wiring design and pin position and the target stacking or arrangement position of the chip based on the comparison result between the chip functional yield obtained after simulation and the actual functional yield.

[0083] According to one embodiment of the present application, the design module 120 is also used to: obtain the test probe chip probe point coordinates and test information; perform thermal simulation and stress action simulation based on the test probe chip probe point coordinates and test information, circuit and material parameter information, packaging parameter information, chip thermal management parameter information and the actual functional yield of the chip, so as to determine the circuit wiring design and pin position and the target stacking or arrangement position of the chip according to the simulation results of the thermal simulation and stress simulation.

[0084] According to one embodiment of the present application, the design module 120 is also used to: optimize the passivation layer, the redistribution layer, the type and material of the bumps, the packaging type and material, the position of the stacked integrated circuits, the material of the carrier or the interposer, and the heat dissipation device based on the simulation results.

[0085] It should be noted that for details not disclosed in the chip packaging design optimization device of the embodiment of the present application, please refer to the details disclosed in the chip packaging design optimization method of the embodiment of the present application, and the details will not be repeated here.

[0086] According to the chip packaging design optimization device of the embodiment of the present application, the acquisition module is used to acquire circuit and material parameter information, packaging parameter information and chip thermal management parameter information, and the design module is used to perform thermal simulation and stress simulation based on the circuit and material parameter information, the packaging parameter information, the chip thermal management parameter information and the functional yield of the chip, so as to determine the circuit wiring design and the pin position and the target stacking or arrangement position of the chip according to the simulation results of the thermal simulation and stress simulation. Thus, the device can improve the reliability and quality of chip packaging.

[0087] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0088] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0089] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0090] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0091] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0092] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A chip packaging design optimization method, characterized in that: The method comprises: Obtain circuit and material parameter information, packaging parameter information and chip thermal management parameter information; Thermal simulation and stress action simulation are performed based on the circuit and material parameter information, the packaging parameter information, the chip thermal management parameter information and the actual functional yield of the chip, so as to determine the circuit wiring design and pin position and the target stacking or arrangement position of the chip according to the simulation results of the thermal simulation and stress simulation.

2. The chip package design optimization method according to claim 1, characterized in that: The obtaining of circuit and material parameter information includes: Obtain protection layer circuit and material information, chip backside process circuit and material information, circuit bump circuit and material information, and carrier circuit and material information.

3. The chip package design optimization method according to claim 1, characterized in that: The obtaining of packaging parameter information includes: Get packaging material information, wafer stacking packaging information, and underfill material information.

4. The chip package design optimization method according to claim 1, characterized in that: The obtaining of chip thermal management parameter information includes: Get the heat dissipation structure and packaging information.

5. The chip package design optimization method according to claim 1, characterized in that: The thermal simulation and stress simulation are performed based on the circuit and material parameter information, the packaging parameter information, the chip thermal management parameter information and the actual functional yield of the chip, so as to determine the circuit wiring design and the pin position and the target stacking or arrangement position of the chip according to the simulation results of the thermal simulation and the stress simulation, and further includes: Based on the comparison result between the chip functional yield obtained after simulation and the actual functional yield, the circuit wiring design and the pin position as well as the target stacking or arrangement position of the chip are optimized.

6. The chip package design optimization method according to claim 1, characterized in that: The method further comprises: Get the test probe chip probe point coordinates and test information; Thermal simulation and stress action simulation are performed based on the test probe chip probe point coordinates and test information, circuit and material parameter information, the packaging parameter information, the chip thermal management parameter information and the actual functional yield of the chip to determine the circuit wiring design and pin position and the target stacking or arrangement position of the chip according to the simulation results of the thermal simulation and stress simulation.

7. The chip package design optimization method according to claim 1, characterized in that: The method further comprises: Based on the simulation results, the passivation layer, redistribution layer, type and material of bumps, package type and material, position of stacked integrated circuits, material of carrier or interposer, and heat dissipation device are optimized.

8. A computer-readable storage medium, characterized in that: A program is stored thereon, and when the program is executed by a processor, the method for optimizing chip packaging design according to any one of claims 1-7 is implemented.

9. An electronic device, characterized in that: include: A memory, a processor, and a program stored in the memory and executable on the processor, wherein when the processor executes the program, the method for optimizing chip packaging design according to any one of claims 1 to 7 is implemented.

10. A chip packaging design optimization device, characterized in that: The device comprises: An acquisition module is used to acquire circuit and material parameter information, packaging parameter information, and chip thermal management parameter information; The design module is used to perform thermal simulation and stress simulation based on the circuit and material parameter information, the packaging parameter information, the chip thermal management parameter information and the functional yield of the chip, so as to determine the circuit wiring design and pin position and the target stacking or arrangement position of the chip according to the simulation results of the thermal simulation and stress simulation.

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