Spread spectrum clock generating device

Abstract

The invention discloses a spread spectrum clock generation device which comprises a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, a frequency divider, a phase converter, a parameter generator, a DSM modulator, a first adder and a second adder. The input end of the phase converter is connected with the frequency divider, and the output end of the phase converter is connected with the phase frequency detector and the parameter generator. The output end of the parameter generator is connected with the DSM modulator, the first adder and the second adder, the output end of the first adder is connected with the phase converter, and the output end of the second adder is connected with the frequency divider. The spread spectrum clock generated by the invention is high in precision, low in jitter and good in phase noise performance, and is particularly suitable for a SerDes communication system.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit design, and in particular relates to a spread spectrum clock generating device. Background Art

[0002] In the embedded field, traditional parallel communication methods are no longer able to meet the communication requirements of large data volumes and multi-device networking. Serial-to-Deserial (SerDes) has become the mainstream method for high-speed data transmission, placing higher demands on clock frequency and performance. For single-frequency clocking, as communication rates increase, the clock center frequency also increases, generating stronger electromagnetic interference (EMI) in the circuit, affecting the operation of other devices and limiting the development and application of this technology. To address this issue, spread-spectrum clocking technology has been developed. This evenly distributes the power of a single-frequency clock within a limited bandwidth, thereby reducing the power of its electromagnetic radiation.

[0003] Whether using single-frequency or spread-spectrum clocking, a phase-locked loop (PLL) is required. A PLL is an electronic system used to generate a clock with a specific phase relationship to a reference clock. This system typically includes a phase frequency detector (PFD), a charge pump (CP), a loop filter (LF), a voltage-controlled oscillator (VCO), and a frequency divider (DIV). Feedback from the entire loop ultimately aligns the phase of the divided clock with the reference clock. The VCO output typically serves as the target clock, with its frequency determined by the control voltage of the LF output.

[0004] There are four existing methods for PLL to generate spread spectrum clocks: (1) Directly modulate the reference clock. Although this method has a simple structure, the digital modulation noise bandwidth is very wide and difficult to filter out through the loop. It will be directly reflected in the output clock, resulting in poor phase noise performance; (2) Modulate the VCO control voltage. This method requires extremely high accuracy of the VCO control voltage. Under different processes, the accuracy of spread spectrum modulation cannot be guaranteed; (3) Directly use phase interpolation to implement the divider of the feedback loop. Due to the nonlinearity of phase interpolation and the resolution problem of the interpolator itself, this method causes a large number of spurious signals to appear in the output clock, seriously deteriorating the phase noise performance; (4) Directly use DSM to modulate the divider of the feedback loop. This method is relatively simple to implement digitally, but the quantization noise will inevitably produce fractional spurs, causing the output clock to have varying degrees of jitter. Summary of the Invention

[0005] Purpose of the invention: In order to solve the problems of low precision and poor phase noise performance of the spread spectrum clock generated by the spread spectrum clock generator in the prior art, the present invention provides a spread spectrum clock generating device.

[0006] Technical solution: A spread spectrum clock generator, including a frequency and phase detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a frequency divider, and also includes:

[0007] A phase converter, wherein the input end is connected to the frequency divider, the clock output end is connected to the frequency and phase detector and the parameter generator, the overflow value output end is connected to the second adder, and the phase converter is used to synthesize the divided clock by combining the at least two clocks output by the frequency divider;

[0008] The parameter generator has an output end connected to the DSM modulator, the first adder, and the second adder, respectively, for providing the input parameter of the DSM modulator, the first phase parameter component, and the base value of the frequency divider;

[0009] A DSM modulator, an output end of which is connected to the first adder and is used to provide a second phase parameter component;

[0010] a first adder, an output end of which is connected to the phase converter, for adding the first phase parameter component and the second phase parameter component and providing the sum to the phase converter;

[0011] The second adder has an output end connected to the frequency divider and is used for adding the base value of the frequency divider and the overflow value of the phase converter and then providing the sum to the frequency divider.

[0012] Furthermore, the phase converter includes a phase accumulator, a phase encoder, a phase inverter and a phase interpolator. The phase accumulator is used to continuously accumulate the input phase parameters; the phase encoder is used to synchronously set the flag according to the overflow state of the phase accumulator and encode the phase interpolation parameters; the phase inverter is used to exchange the two clocks input to the phase converter according to the bit flag, and reverse the phase value; the phase interpolator is used to interpolate according to the encoding and the two clocks input to the phase converter, and output the divided clock.

[0013] Furthermore, the DSM modulator at least includes a first-stage accumulator, and a random scrambling code is added to the last bit of the first-stage accumulator in an initial state.

[0014] Furthermore, the DSM modulator is used to output a mean value of α / 2 N The discrete phase of , N is the bit width of the DSM modulator, and α is the input parameter of the DSM modulator;

[0015] Where N is determined by the following formula:

[0016]

[0017] N=MW

[0018] in, is the clock resolution, is the reference clock frequency, is the upper frequency limit of the target spread spectrum clock, M is the sum of the bit width of the phase interpolator and the bit width of the DSM modulator, and W is the bit width of the phase interpolator in the phase converter.

[0019] Furthermore, the parameter generator includes an internal accumulator, and the total bit width of the internal accumulator is M+1, which includes a sign bit for bidirectional parameter update.

[0020] Furthermore, let the accumulator update step be , the frequency of the spread spectrum clock and The following relationship exists:

[0021]

[0022]

[0023] in, To adjust the frequency in a single step, is the clock resolution, is the spread spectrum clock frequency, is the spread spectrum clock modulation amplitude, is the reference clock frequency.

[0024] Furthermore, the parameter generator outputs preset corresponding parameters according to the divided clock, including the input parameter α of the DSM modulator, the first phase parameter component PH1, and the base value DIV_N of the frequency divider.

[0025] Furthermore, let the phase parameter output by the first adder be PH, let the second phase parameter component output by the DSM modulator be DSM, and DSM has a mean value of α / 2 N The relationship between the discrete phase parameters includes:

[0026] ,

[0027] PH= PH1+ DSM

[0028] Among them, n = 0, 1, 2, 3..., represents the sequence number, Represents multiple phase parameters.

[0029] Compared with the prior art, the spread spectrum clock generating device provided by the present invention has the following beneficial effects:

[0030] (1) By using a frequency divider to realize integer frequency division and combining it with a phase interpolator and a DSM modulator to realize fractional frequency division, the resolution of phase interpolation can be improved to a certain index accuracy, so that the generated spread spectrum clock has high accuracy and low jitter, which is particularly suitable for application in SerDes systems, improving the applicability and reliability of the system;

[0031] (2) Using the modified DSM modulation technology to achieve phase interpolation randomization and effectively suppress spurious frequencies;

[0032] (3) The phase converter uses phase inversion technology to ensure the continuity of phase interpolation, so as to avoid large random phase jumps caused by large changes in phase parameters, and effectively suppress the nonlinearity of the phase interpolator;

[0033] (4) The parameter generator outputs the phase parameters required by the phase converter, the input parameters required by the DSM modulator, and the frequency division base value required by the frequency divider according to the frequency division clock, so that the phase converter, DSM modulator, and frequency divider work together to achieve a better frequency division effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a structural diagram of a spread spectrum clock generating device;

[0035] Figure 2 is a structural diagram of a phase converter;

[0036] Figure 3 It is a composite diagram of phase interpolation and inversion vector;

[0037] Figure 4 is the phase interpolation timing;

[0038] Figure 5 Schematic diagram of the structure of the DSM modulator;

[0039] Figure 6 Output noise spectrum diagram for a common DSM modulator;

[0040] Figure 7 Output noise spectrum of the improved DSM modulator;

[0041] Figure 8 It is a fractional resolution modulation waveform;

[0042] Figure 9 Output waveform of the phase inverter;

[0043] Figure 10 Output PRBS signal eye diagram for single frequency;

[0044] Figure 11 The frequency spectrum of the VCO output is shown in Figure 1 when the spread spectrum clock function is enabled and disabled. DETAILED DESCRIPTION

[0045] The present invention will be further explained below with reference to the accompanying drawings and specific embodiments.

[0046] A spread spectrum clock generating device, such as Figure 1As shown, it includes a frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator and a frequency divider, and also includes:

[0047] A phase converter, whose input end is connected to the frequency divider; a clock output end outputs a divided clock CLK_DIV, which is connected to the frequency detector and the parameter generator; an overflow value output end outputs Q, which is connected to the second adder; the phase converter is used to synthesize the divided clock CLK_DIV by combining at least two clocks P1 and P2 output by the frequency divider, thereby further realizing fractional frequency division based on the integer frequency division realized by the frequency divider;

[0048] The parameter generator has its output ends connected to the DSM modulator, the first adder, and the second adder, respectively, for providing the input parameter α of the DSM modulator, the first phase parameter component PH1, and the base value DIV_N of the frequency divider;

[0049] A DSM modulator, an output end of which is connected to the first adder and is used to provide a second phase parameter component DSM;

[0050] A first adder, an output end of which is connected to the phase converter, for adding the first phase parameter component PH1 and the second phase parameter component DSM and providing the summed values ​​to the phase converter, wherein the phase parameter after addition is recorded as PH;

[0051] The second adder has an output end connected to the frequency divider and is used for adding the base value DIV_N of the frequency divider and the overflow value Q of the phase converter and then providing the sum to the frequency divider.

[0052] The phase interpolator is used to interpolate based on the phase parameter PH and the two clocks P1 and P2 input to the phase converter, and output the divided clock CLK_DIV. Figure 2 As shown, the phase converter includes a phase accumulator, a phase encoder, a phase inverter and a phase interpolator. The phase accumulator is used to continuously accumulate the input phase parameter PH; the phase encoder determines whether the phase interpolation crosses the quadrant according to the overflow value Q of the phase accumulator, that is, whether clock switching is required, and synchronously sets the flag CKSWAP to encode the phase interpolation parameter; the phase inverter is used to exchange the two clocks P1 and P2 input to the phase converter according to the bit flag CKSWAP, and reverse the phase value ɸ (2 W -ɸ), if CKSWAP=0, it means that the phase interpolation does not cross the quadrant, P1 and P2 are not swapped, and the phase value is not reversed; if CKSWAP=1, it means that the phase interpolation crosses the quadrant, P1 and P2 are swapped, and the phase value is reversed (2 W -ɸ). Figure 3As shown, when the phase interpolation parameter increases or decreases in one direction, the phase interpolation clock always adjusts in one direction, P1->P2 or P2->P1. The phase interpolator performs phase interpolation based on the input phase parameter PH and the clocks P1 and P2, and outputs the target divided clock CLK_DIV, which always has a phase between P1 and P2.

[0053] In addition, the overflow value Q generated by the phase accumulator is input from the second adder, and after being added to the frequency division base value DIV_N output by the parameter generator, it is input to the frequency divider as the input parameter of the frequency divider. For example, when Q is 1, the input parameter of the frequency divider is DIV_N+1; when Q is 2, the input parameter of the frequency divider is DIV_N+2. Figure 4 As shown, this can be adjusted based on the actual spread spectrum amplitude; the larger the spread spectrum amplitude, the greater the Q. The phase converter is used to further divide the integer-divided clock by the divider to obtain a fractional-frequency clock, ultimately generating the high-resolution target fractional-frequency clock CLK_DIV. This divided clock is fed into the phase and frequency detector. After current-to-voltage conversion by the charge pump and filtering and shaping by the loop filter, it controls the voltage-controlled oscillator to output the target spread spectrum clock.

[0054] The DSM modulator at least includes a first-stage accumulator, and adds a random scrambling code to the last bit of the first-stage accumulator in the initial state, such as adding a 1-bit random scrambling code in this embodiment. Figure 5 The figure shows the implementation of a three-level DSM modulator. The specific DSM modulator structure can be implemented in more than one way. The DSM modulator is used to output the DSM value, which has an average value of α / 2. N The discrete phase of the DSM modulator, N is the bit width of the DSM modulator, and α is the input parameter of the DSM modulator. The DSM value is a random value of phase variation. The first adder then adds the DSM value to the first phase parameter component PH1 output by the parameter generator as the input parameter PH of the phase converter. The output noise spectrum of a common DSM modulator without random scrambling is as follows: Figure 6 As shown in , because its output sequence has a certain periodicity, the spurious signal shown in the spectrum appears. Figure 7 The DSM modulator with 1-bit random scrambling code breaks up the periodicity of the sequence and effectively suppresses spurious signals.

[0055] The bit width N of the DSM modulator is determined according to the clock resolution index to be designed, and specifically has the following relationship:

[0056] (1)

[0057] N=MW (2)

[0058] in, is the clock resolution, is the reference clock frequency, is the upper frequency limit of the target spread spectrum clock, M is the sum of the bit width of the phase interpolator and the bit width of the DSM modulator, and W is the bit width of the phase interpolator in the phase converter.

[0059] The parameter generator outputs preset corresponding parameters based on the divided clock, including the input parameter α of the DSM modulator, the first phase parameter component PH1, and the base value DIV_N of the divider. By changing these parameter values, the frequency division ratio can be changed in real time, thereby causing the VCO control voltage to change in real time, producing a spread spectrum effect on its output frequency.

[0060] The parameter generator includes an internal accumulator with a total bit width of M+1, including a sign bit for bidirectional parameter update. Determines the frequency of the spread spectrum clock, and the update step size refers to the number of bits required for a single step adjustment. Assume that the accumulator update step size is , the frequency of the spread spectrum clock and The following relationship exists:

[0061] (3)

[0062] (4)

[0063] in, To adjust the frequency in a single step, is the clock resolution, is the spread spectrum clock frequency, is the spread spectrum clock modulation amplitude, is the reference clock frequency.

[0064] The PH output extreme value is related to the selection of DIV_N. Let the first phase parameter component be PH1, the base value of the divider be DIV_N, the phase parameter output by the first adder be PH, the second phase parameter component output by the DSM modulator be DSM, and the mean value of DSM is α / 2 N The discrete phase of DIV_N should be selected to output the optimal value to the second adder. Under this optimal value, the pH value fluctuation is minimal and the phase interpolator is more stable. The following relationship exists between the various parameters:

[0065] (5)

[0066] PH = PH1 + DSM (6)

[0067] Among them, n = 0, 1, 2, 3..., represents the sequence number, Represents multiple phase parameters.

[0068] To verify the spread spectrum effect of this embodiment, the following experiments were conducted:

[0069] The external reference clock frequency is 24 MHz, requiring a 2.5 GHz upper cutoff frequency for the output spread-spectrum clock, a 33 kHz SSC modulation frequency, and an amplitude range of -4900 ppm to 0 ppm. The DSM modulator is designed with an 11-bit bit width, and the phase interpolator is designed with a 5-bit bit width. Because bidirectional adjustment is required, the parameter unit accumulator is designed as a signed number, resulting in a total parameter unit bit width of 17 bits, with an adjustable range of [-65536, 65535].

[0070] The clock resolution (frequency resolution) can be calculated by formula (1): =0.1465 ppm / lsb.

[0071] The frequency adjustment range is [-9601 ppm, 9600 ppm]. For 2.5 GHz, the upper deviation is 1600 ppm, while the lower deviation is -3400 ppm. The frequency division base value, or the division ratio DIV_N, is set to 104, and the parameter adjustment range is [-3400 ppm, 1600 ppm], corresponding to the 17-bit parameter adjustment range of [-23208 10922]. The step size, according to equation (3), yields a single-step adjustment frequency of 13.4750 ppm. Based on equation (3), the corresponding 17-bit parameter step size is set to approximately 92.

[0072] Its modulation waveform is as follows Figure 8 As shown in Figure 1, the parameter generator sends the lower 11 bits of the 17-bit accumulator as the α value to the DSM modulator to calculate the second phase parameter component, that is, the random DSM value. The upper 6 bits are used as the fractional parameter part of the phase interpolation implementation, and are combined with the DSM value as the input parameter PH of the phase converter. The simulation results are shown in Figure 1. Figure 8 As shown in the figure, as the parameter accumulator is continuously updated, PH1 and DSM are continuously updated and merged into the actual adjustment phase parameter PH, which is mixed with random jitter in the determined phase change. After mean filtering, the fractional phase adjustment obtained is shown as Mean in the figure, which represents that the divider has achieved the spread spectrum effect of fractional frequency division.

[0073] The input parameter PH of the phase converter is accumulated, encoded and switched by the phase converter. Figure 9As shown in the figure, SWAP is a flag bit. When the SWAP signal is 0, it indicates that the phase has not crossed quadrants (the phase difference between P1 and P2 represents one quadrant). P1 and P2 clocks do not need to be switched, with P1 leading P2 by one VCO output clock cycle. The PH value accumulates normally, indicating a phase shift from P1 to P2. When SWAP is 1, it indicates that the current interpolated phase has crossed quadrants. P1 and P2 are switched, with P1 lagging P2 by one VCO output clock cycle. Simultaneously, the PH value decreases in reverse order, indicating a phase shift from P2 to P1. Therefore, overall, the interpolated clock phase always shifts from the advanced clock to the delayed clock, and vice versa. Without a phase switching design, when the interpolated phase crosses quadrants, the division ratio increases by +1 or -1, and the PH value may jump directly from 32 to 0 or other smaller values, resulting in a large PH jump. Therefore, a phase converter with a phase switching structure can control the PH jump value within a narrow range.

[0074] Figure 10 When the spread spectrum function is not enabled, the VCO outputs a single-point frequency, and the eye diagram obtained by driving the PRBS signal with this clock shows that its PP jitter is 50ps. Figure 11 As shown in the figure, the dotted box represents the signal spectrum of the VCO output when the spread spectrum function is turned off, and the solid box represents the signal spectrum of the VCO output when the spread spectrum function is turned on. After the spread spectrum is formed, the peak power drops by 15.6dBm, and the energy of the main frequency is dispersed to -5000pp~0ppm, achieving a good spread spectrum effect.

Claims

1. A spread spectrum clock generating device, comprising a frequency detector, a charge pump, a loop filter, a voltage controlled oscillator and a frequency divider, characterized in that: Also includes: A phase converter, wherein the input end is connected to the frequency divider, the clock output end is connected to the frequency detector and the parameter generator, the overflow value output end is connected to the second adder, and the phase converter is used to synthesize the divided clock by combining at least two clocks output by the frequency divider; A parameter generator, the output end of which is respectively connected to the DSM modulator, the first adder, and the second adder, and is used to provide the input parameter of the DSM modulator, the first phase parameter component, and the base value of the frequency divider respectively; A DSM modulator, an output end of which is connected to a first adder for providing a second phase parameter component; A first adder, the output end of which is connected to the phase converter, and is used to add the first phase parameter component and the second phase parameter component and then provide the result to the phase converter; The second adder has an output end connected to the frequency divider and is used for adding the base value of the frequency divider and the overflow value of the phase converter and then providing the result to the frequency divider.

2. The spread spectrum clock generating device according to claim 1, characterized in that: The phase converter includes a phase accumulator, a phase encoder, a phase inverter and a phase interpolator. The phase accumulator is used to continuously accumulate input phase parameters; the phase encoder is used to synchronously set a flag according to an overflow state of the phase accumulator and encode the phase interpolation parameter; The phase inverter is used to exchange the two clocks of the input phase converter according to the bit mark and reverse the phase value; the phase interpolator is used to interpolate the two clocks of the encoding and input phase converter and output the divided clock.

3. The spread spectrum clock generating device according to claim 1 or 2, characterized in that: The DSM modulator at least comprises a first-stage accumulator, and a random scrambling code is added to the last bit of the first-stage accumulator in an initial state.

4. The spread spectrum clock generating device according to claim 3, characterized in that: The DSM modulator is used to output a mean value of α / 2 N The discrete phase of the DSM modulator, N is the bit width of the DSM modulator, and α is the input parameter of the DSM modulator; Where N is determined by the following formula: N=MW in, is the clock resolution, is the reference clock frequency, is the upper frequency limit of the target spread spectrum clock, M is the sum of the bit width of the phase interpolator and the bit width of the DSM modulator, and W is the bit width of the phase interpolator in the phase converter.

5. The spread spectrum clock generating device according to claim 1 or 2, characterized in that: The parameter generator includes an internal accumulator, and the total bit width of the internal accumulator is M+1, which includes a sign bit for bidirectional parameter update.

6. The spread spectrum clock generating device according to claim 5, characterized in that: Assume that the accumulator update step size is , the frequency of the spread spectrum clock and The following relationship exists: in, To adjust the frequency in a single step, is the clock resolution, is the spread spectrum clock frequency, is the spread spectrum clock modulation amplitude, is the reference clock frequency.

7. The spread spectrum clock generating device according to claim 1 or 2, characterized in that: The parameter generator outputs preset corresponding parameters according to the divided clock, including the input parameter α of the DSM modulator, the first phase parameter component PH1, and the base value DIV_N of the frequency divider.

8. The spread spectrum clock generating device according to claim 6, characterized in that: Assume that the phase parameter output by the first adder is PH, and the second phase parameter component output by the DSM modulator is DSM, where the mean value of DSM is α / 2. N The relationship between the discrete phases of the parameters includes: ， PH= PH1+ DSM Among them, n = 0, 1, 2, 3..., represents the sequence number, Represents multiple phase parameters.

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