Noise shaping circuit and analog-to-digital converter

Abstract

The embodiment of the invention provides a noise shaping circuit and an analog-to-digital converter, which can be applied to the technical field of integrated circuits. The noise shaping circuit comprises a plurality of switches, a first capacitor, a second capacitor and a buffer connected between the first capacitor and the second capacitor, the plurality of switches are configured to respond to a switch control signal and alternatively enable one of the first capacitor and the second capacitor to serve as an integrating capacitor to be connected to the analog signal input end, so that the integrating capacitor provides an integrating voltage for the buffer based on a margin voltage provided by the analog signal input end and a capacitor voltage stored in the integrating capacitor; the other one of the first capacitor and the second capacitor is used as a storage capacitor, and the integral voltage flowing through the buffer is received and stored; the integrating capacitor is configured to output an integrating voltage to the output end of the noise shaping circuit, so that the digital logic circuit performs analog-to-digital conversion on the integrating voltage to obtain a margin voltage and provide the margin voltage to the analog signal input end.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and more specifically, to a noise shaping circuit and an analog-to-digital converter. Background Art

[0002] With the rapid advancement of cutting-edge technologies such as deep space exploration and quantum computing, more stringent requirements are placed on the performance of ADCs, that is, they must maintain high speed and high precision in extremely low temperature environments. Among them, the use of noise shaping technology can be used to improve the accuracy of ADCs.

[0003] However, the traditional successive approximation noise shaping circuit uses an operational amplifier as an integrator, which has problems such as increased power consumption, pole problems introduced by gain error, and significant effects of voltage, temperature and other changes on gain fluctuations in extremely low temperature environments. In addition, the traditional noise shaping circuit also combines passive switched capacitor filtering and dynamic amplifiers to optimize the noise transfer function at low frequencies, but PVT has a greater impact on its gain fluctuations and poor stability in extremely low temperature environments. Summary of the invention

[0004] In view of this, the present disclosure provides a noise shaping circuit and an analog-to-digital converter.

[0005] One aspect of the present disclosure provides a noise shaping circuit, comprising: a plurality of switches, a first capacitor, a second capacitor, and a buffer connected between the first capacitor and the second capacitor; the plurality of switches are configured to respond to a switch control signal, alternately connect one of the first capacitor and the second capacitor as an integral capacitor to an analog signal input terminal, so that the integral capacitor provides an integral voltage to the buffer based on a residual voltage provided by the analog signal input terminal and a capacitor voltage stored in the integral capacitor, and the other of the first capacitor and the second capacitor is used as a storage capacitor to receive and store the integral voltage flowing through the buffer; the integral capacitor is configured to output the integral voltage to an output terminal of the noise shaping circuit, so that a digital logic circuit performs analog-to-digital conversion on the integral voltage, obtains the residual voltage, and provides it to the analog signal input terminal.

[0006] According to an embodiment of the present disclosure, the multiple switches include a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a ninth switch, a tenth switch, an eleventh switch, a twelfth switch, a thirteenth switch, and a fourteenth switch; the first capacitor includes a first sub-capacitor and a second sub-capacitor, the second capacitor includes a third sub-capacitor and a fourth sub-capacitor, and the buffer includes a first buffer and a second buffer.

[0007] According to an embodiment of the present disclosure, the noise shaping unit is configured as follows: a first end of the first switch is connected to the analog signal input end, a second end of the first switch is connected to the first end of the first sub-capacitor, a second end of the first sub-capacitor is connected to the first end of the third switch and the second end of the fourth switch via the thirteenth switch, a second end of the third switch is connected to the first end of the first buffer and the first end of the output end of the noise shaping circuit, a second end of the first buffer is connected to the first end of the fifth switch and the first end of the fourth switch, a second end of the fifth switch is connected to the second end of the third sub-capacitor via the eleventh switch; a first end of the second switch is connected to the analog signal input end, a second end of the second switch is connected to the first end of the third sub-capacitor, a first end of the sixth switch is connected to the second end of the third sub-capacitor, and a second end of the sixth switch is connected to the first end of the first buffer.

[0008] According to an embodiment of the present disclosure, the noise shaping unit is further configured such that the first end of the second sub-capacitor is connected to the second end of the first sub-capacitor via the thirteenth switch and the fourteenth switch, respectively, the second end of the second sub-capacitor is connected to the first end of the seventh switch and the second end of the eighth switch, the second end of the seventh switch is connected to the first end of the second buffer and the first end of the comparator, the second end of the second buffer is connected to the first end of the ninth switch and the first end of the eighth switch, respectively, the second end of the ninth switch is connected to the second end of the fourth sub-capacitor; the first end of the fourth sub-capacitor is connected to the second end of the third sub-capacitor via the eleventh switch and the twelfth switch, respectively, the first end of the tenth switch is connected to the second end of the fourth sub-capacitor, and the second end of the tenth switch is connected to the first end of the second buffer.

[0009] According to an embodiment of the present disclosure, the switch control signal is a periodic signal, and the switch control signal includes a first sub-signal and a second sub-signal; the first sub-signal and the second sub-signal are alternately configured to be high level based on a time period.

[0010] According to an embodiment of the present disclosure, the above-mentioned multiple switches are configured to respond to the above-mentioned first sub-signal, control the above-mentioned first switch, the above-mentioned third switch, the above-mentioned fifth switch, the above-mentioned eleventh switch, and the above-mentioned thirteenth switch to be closed, and the above-mentioned second switch, the above-mentioned fourth switch, and the above-mentioned sixth switch to be opened, so that the above-mentioned first sub-capacitor is connected to the above-mentioned analog signal input terminal as the above-mentioned integral capacitor, so that the above-mentioned first sub-capacitor superimposes the above-mentioned capacitor voltage stored in itself with the above-mentioned residual voltage provided by the above-mentioned analog signal input terminal to obtain a first integral voltage, and provides the above-mentioned first integral voltage to the above-mentioned first buffer, and makes the above-mentioned third sub-capacitor serve as the above-mentioned storage capacitor to receive the first integral voltage flowing through the above-mentioned first buffer and perform row storage; the multiple switches are also configured to control the seventh switch, the ninth switch, and the fourteenth switch to be closed, and control the eighth switch, the tenth switch, and the twelfth switch to be opened in response to the first sub-signal, so that the second sub-capacitor is connected to the first sub-capacitor as the integration capacitor, so that the second sub-capacitor superimposes the capacitor voltage stored in itself, the capacitor voltage stored in itself by the first sub-capacitor, and the residual voltage provided by the analog signal input terminal to obtain a second integration voltage, and provides the second integration voltage to the second buffer, and makes the fourth sub-capacitor serve as the storage capacitor to receive and store the second integration voltage flowing through the second buffer.

[0011] According to an embodiment of the present disclosure, the above-mentioned multiple switches are configured to respond to the above-mentioned second sub-signal, control the above-mentioned second switch, the above-mentioned fourth switch, the above-mentioned sixth switch, the above-mentioned eleventh switch, and the above-mentioned thirteenth switch to be closed, and control the above-mentioned first switch, the above-mentioned third switch, and the above-mentioned fifth switch to be opened, so that the above-mentioned third sub-capacitor is connected to the above-mentioned analog signal input terminal as the above-mentioned integral capacitor, so that the above-mentioned third sub-capacitor superimposes the above-mentioned capacitor voltage stored in itself with the above-mentioned residual voltage provided by the above-mentioned analog signal input terminal to obtain a third integral voltage, and provides the above-mentioned third integral voltage to the above-mentioned first buffer, and makes the above-mentioned first sub-capacitor serve as the above-mentioned storage capacitor to receive the third integral voltage flowing through the above-mentioned first buffer. and store; the multiple switches are also configured to respond to the second sub-signal, control the eighth switch, the tenth switch, and the twelfth switch to close, and control the seventh switch, the ninth switch, and the fourteenth switch to open, so that the fourth sub-capacitor is connected to the third sub-capacitor as the integration capacitor, so that the fourth sub-capacitor superimposes the capacitor voltage stored in itself, the capacitor voltage stored in itself by the third sub-capacitor, and the residual voltage provided by the analog signal input terminal to obtain a fourth integral voltage, and provides the fourth integral voltage to the second buffer, and makes the second sub-capacitor serve as the storage capacitor to receive and store the fourth integral voltage flowing through the second buffer.

[0012] According to an embodiment of the present disclosure, the buffer includes a differential buffer, and the noise shaping circuit is further configured to connect the first capacitor or the second capacitor between multiple output terminals of the differential buffer to process the differential voltage output by the differential buffer.

[0013] According to an embodiment of the present disclosure, the above-mentioned multiple switches are configured as a charge pump switch structure, and the above-mentioned charge pump switch structure is configured to control the conduction and shutdown of multiple switch tubes in response to a two-phase non-overlapping clock signal to achieve an increase in the over-drive voltage of each of the above-mentioned multiple switches.

[0014] Another aspect of the present disclosure provides an analog-to-digital converter, comprising: the above-mentioned noise shaping circuit, a capacitor array, an amplifier and a digital logic circuit; wherein the above-mentioned noise shaping circuit outputs an integrated voltage to the above-mentioned amplifier based on the residual voltage provided by the above-mentioned capacitor array; the above-mentioned amplifier and the above-mentioned digital logic circuit perform analog-to-digital conversion on the above-mentioned integrated voltage to obtain a conversion result, wherein the above-mentioned conversion result includes the above-mentioned residual voltage; and the above-mentioned digital logic circuit provides the above-mentioned residual voltage to the above-mentioned capacitor array.

[0015] According to the noise shaping circuit provided by the embodiment of the present disclosure, by alternately using multiple integration capacitors and multiple storage capacitors, combined with the switching of multiple switches, the continuity of the integration process is ensured, which not only avoids the interference that may be caused by directly reading the integration result during the integration process, but also expands the higher-order structure, thereby quantizing the noise more finely to improve the signal-to-noise ratio of the analog-to-digital converter. In addition, by introducing a buffer and a storage capacitor to store the integration result, the circuit can achieve ideal integration without using an amplifier for subsequent analog-to-digital conversion. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0017] Figure 1 The circuit structure diagram of the noise shaping circuit according to the embodiment of the present disclosure is schematically shown.

[0018] Figure 2 The circuit structure diagram of the noise shaping circuit according to a specific embodiment of the present disclosure is schematically shown.

[0019] Figure 3 A circuit structure diagram of a noise shaping circuit according to another specific embodiment of the present disclosure is schematically shown.

[0020] Figure 4 The figure schematically shows a noise shaping circuit using differential integration according to a specific embodiment of the present disclosure.

[0021] Figure 5 A schematic diagram of a charge pump switch structure according to a specific embodiment of the present disclosure is shown schematically.

[0022] Figure 6 The schematic diagram shows a circuit structure of an analog-to-digital converter according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0024] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0025] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0026] When using expressions such as "at least one of A, B, and C, etc.", they should generally be interpreted according to the meaning of the expression commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0027] The core function of an analog-to-digital converter (ADC) is to accurately convert a continuous analog signal into a discrete digital signal. With the rapid advancement of cutting-edge technologies such as deep space exploration and quantum computing, more stringent requirements are placed on the performance of ADCs, namely, maintaining high speed and high precision in extremely low temperature environments.

[0028] Under extremely low temperature conditions, the threshold voltage of the MOS tube becomes higher, the carrier activity slows down or even freezes, and the mismatch between devices of the same area is aggravated. These problems make it difficult for the low-temperature ADC to achieve the same performance as the normal temperature ADC.

[0029] Noise shaping technology can be used to improve the accuracy of ADC. Among them, the traditional successive approximation analog-to-digital converter (SARADC) performs a binary search on the input signal in the comparator quantization stage, and the voltage on the capacitor DAC successively approximates the input analog signal value. Since the SAR structure no longer switches it after the least significant bit (LSB) judgment is completed, the voltage remaining on the upper plate of the capacitor is the N-1-bit residual value. By extracting and processing these residuals, effective shaping of quantization noise and comparator noise can be achieved. At the same time, combined with oversampling technology, the KT / C noise introduced by the in-band sampling switch can be further suppressed, thereby improving the signal-to-noise ratio.

[0030] However, the traditional successive approximation analog-to-digital converter uses an operational amplifier as an integrator, which has problems such as increased power consumption, pole problems introduced by gain error, and significant effects of PVT (process, voltage, temperature) changes on gain fluctuations in extremely low temperature environments. In order to meet the power consumption and process scaling characteristics of the SAR structure, another method of noise shaping is the fully passive NS-SAR structure, but this structure can only achieve lossy shaping, and the noise transfer function (NTF) at low frequencies is shallow at low frequencies. In addition, the noise transfer function at low frequencies is optimized by combining passive switched capacitor filtering and dynamic amplifiers, but PVT has a greater impact on its gain fluctuations and poor stability in extremely low temperature environments.

[0031] Based on the above problems, the embodiments of the present disclosure provide a noise shaping circuit and an analog-to-digital converter. By alternately using multiple integration capacitors and multiple storage capacitors in the noise shaping circuit, the continuity of the integration process is ensured by combining the switching of multiple switches, which not only avoids the interference that may be caused by directly reading the integration result during the integration process, but also expands the higher-order structure to quantize the noise more finely to improve the signal-to-noise ratio of the analog-to-digital converter. In addition, by introducing a buffer and a storage capacitor to store the integration result, the circuit can achieve ideal integration without using an amplifier for subsequent analog-to-digital conversion.

[0032] Specifically, an embodiment of the present disclosure provides a noise shaping circuit, wherein the noise shaping circuit includes: a plurality of switches, a first capacitor, a second capacitor, and a buffer connected between the first capacitor and the second capacitor; the plurality of switches are configured to respond to a switch control signal, alternately connecting one of the first capacitor and the second capacitor as an integral capacitor to an analog signal input terminal, so that the integral capacitor provides an integral voltage to the buffer based on a residual voltage provided by the analog signal input terminal and a capacitor voltage stored in the integral capacitor, and enables the other of the first capacitor and the second capacitor to serve as a storage capacitor to receive and store the integral voltage flowing through the buffer; the integral capacitor is configured to output the integral voltage to the output terminal of the noise shaping circuit, so that the digital logic circuit performs analog-to-digital conversion on the integral voltage, obtains the residual voltage, and provides it to the analog signal input terminal.

[0033] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0034] According to an embodiment of the present disclosure, the noise shaping circuit proposed in the present disclosure includes a plurality of switches, a first capacitor, a second capacitor, and a buffer connected between the first capacitor and the second capacitor. Wherein, under the control of the switch control signal, the plurality of switches respectively conduct different paths, and alternately make one of the first capacitor and the second capacitor connected to the analog signal input terminal as an integral capacitor to superimpose the residual voltage that has not been quantized in the previous operation cycle of the ADC with the capacitor voltage stored in the integral capacitor itself, and the other capacitor is used as a storage capacitor to store the integration result through the buffer, and the buffer can be used to isolate the integral capacitor and the storage capacitor to reduce the mutual influence between the capacitors and provide a stable input for subsequent ADC conversion.

[0035] Figure 1 The circuit structure diagram of the noise shaping circuit according to the embodiment of the present disclosure is schematically shown.

[0036] like Figure 1 As shown, the multiple switches include, for example, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a seventh switch S7, an eighth switch S8, a ninth switch S9, and a tenth switch S10, wherein the multiple switches also include, for example, an eleventh switch S11, a twelfth switch S12, a thirteenth switch S13, and a fourteenth switch S14; the first capacitor includes, for example, a first sub-capacitor Co1 and a second sub-capacitor Co2, the second capacitor includes, for example, a third sub-capacitor Ce1 and a fourth sub-capacitor Ce2, and the buffer includes, for example, a first buffer BUFF1 and a second buffer BUFF2, so as to form a second-order noise shaping circuit.

[0037] Specifically, the first end of the first switch S1 is respectively connected to the analog signal input end and the output end of the noise shaping circuit, the second end of the first switch S1 is connected to the first end of the first sub-capacitor Co1, the second end of the first sub-capacitor Co1 is respectively connected to the first end of the third switch S3 and the second end of the fourth switch S4 via the thirteenth switch S13, the second end of the third switch S3 is respectively connected to the first end of the first buffer BUFF1 and the output end of the noise shaping circuit, the second end of the first buffer BUFF1 is respectively connected to the first end of the fifth switch S5 and the first end of the fourth switch S4, and the second end of the fifth switch S5 is connected to the second end of the third sub-capacitor Ce1 via the eleventh switch S11.

[0038] Among them, the first end of the second switch S2 is connected to the analog signal input end and the output end of the noise shaping circuit respectively, the second end of the second switch S2 is connected to the first end of the third sub-capacitor Ce1, the first end of the sixth switch S6 is connected to the second end of the third sub-capacitor Ce1, and the second end of the sixth switch S6 is connected to the first end of the first buffer BUFF1.

[0039] Among them, the first end of the second sub-capacitor Co2 is connected to the second end of the first sub-capacitor Co1 via the thirteenth switch S13 and the fourteenth switch S14 respectively, the second end of the second sub-capacitor Co2 is connected to the first end of the seventh switch S7 and the second end of the eighth switch S8, the second end of the seventh switch S7 is connected to the first end of the second buffer BUFF2 and the output end of the noise shaping circuit respectively, the second end of the second buffer BUFF2 is connected to the first end of the ninth switch S9 and the first end of the eighth switch S8 respectively, and the second end of the ninth switch S9 is connected to the second end of the fourth sub-capacitor Ce2.

[0040] The first end of the fourth sub-capacitor Ce2 is connected to the second end of the third sub-capacitor Ce1 via the eleventh switch S11 and the twelfth switch S12 respectively, the first end of the tenth switch S10 is connected to the second end of the fourth sub-capacitor Ce2, and the second end of the tenth switch S10 is connected to the first end of the second buffer BUFF2.

[0041] like Figure 1As shown, the plurality of switches further include, for example, a first grounding switch QE1, a second grounding switch QE2, a third grounding switch QE3, and a fourth grounding switch QE4, wherein a first end of the first grounding switch QE1 is connected to a first end of the third sub-capacitor Ce1, and a second end of the first grounding switch QE1 is grounded. A first end of the second grounding switch QE2 is connected to a fourth sub-capacitor Ce2, and a second end of the second grounding switch QE2 is grounded. A first end of the third grounding switch QE3 is connected to a first end of the first sub-capacitor Co1, and a second end of the first third grounding switch QE4 is grounded. A first end of the fourth grounding switch QE4 is connected to a second sub-capacitor Co2, and a second end of the fourth grounding switch QE4 is grounded.

[0042] According to an embodiment of the present disclosure, a switch control signal can be used to characterize an operation cycle of an analog-to-digital converter (ADC), for example, including a sampling cycle or a conversion cycle of the ADC. The switch control signal includes a first sub-signal and a second sub-signal, and the first sub-signal and the second sub-signal are alternately configured to different levels in a time period. For example, when the first sub-signal is at a high level, the second sub-signal is at a low level.

[0043] According to an embodiment of the present disclosure, multiple switches perform ping-pong operations on the first capacitor and the second capacitor based on the control of the first sub-signal and the second sub-signal, so that the first capacitor and the second capacitor alternately serve as an integration capacitor or a storage capacitor, thereby realizing a continuous integration process without using a closed-loop amplifier in the noise shaping circuit.

[0044] For example, when the first sub-signal is at a high level in the 2k-1th cycle, the first capacitor is used as an integration capacitor and the second capacitor is used as a storage capacitor. The first capacitor integrates the unquantized residual voltage in the 2k-2th cycle and the integrated voltage stored in the 2k-2th cycle, and outputs the integrated voltage in the 2k-1th cycle for quantization, and the integrated voltage is also stored in the second capacitor through the buffer.

[0045] For example, when the second sub-signal is at a high level in the 2kth cycle, the second capacitor is used as an integration capacitor and the first capacitor is used as a storage capacitor. The second capacitor integrates the unquantized residual voltage in the 2k-1th cycle and the integrated voltage stored in its own 2k-1th cycle, and outputs the integrated voltage in the 2kth cycle for quantization, and the integrated voltage is also stored in the first capacitor through the buffer.

[0046] Figure 2 The circuit structure diagram of the noise shaping circuit according to a specific embodiment of the present disclosure is schematically shown.

[0047] like Figure 2As shown, in the operation cycle when the first sub-signal CLKS1 is at a high level, the first switch S1, the third switch S3, the fifth switch S5, the first grounding switch QE1, the second grounding switch QE2, the eleventh switch S11, and the thirteenth switch S13 are closed, and the second switch S2, the fourth switch S4, the sixth switch S6, the third grounding switch QE3, and the fourth grounding switch QE4 are opened, so that the first sub-capacitor Co1 is connected to the analog signal input terminal as an integrating capacitor, so that the first sub-capacitor Co1 can store the capacitor voltage V Co1 The analog signal input terminal provides a margin voltage V res The first integrated voltage is obtained by superposition and is used as the output voltage V out2 Output from the output terminal; at the same time, the first sub-capacitor Co1 provides the first integrated voltage to the first buffer BUFF1. The third sub-capacitor Ce1 serves as a storage capacitor, receiving the first integrated voltage flowing through the first buffer BUFF1 as the voltage V stored in the third sub-capacitor Ce1 itself. Ce1 At this time, the voltage V stored in the third sub-capacitor Ce1 itself Ce1 =V Co1 +V res .

[0048] In addition, during the operation cycle when the first sub-signal CLKS1 is at a high level, the seventh switch S7, the ninth switch S9, and the fourteenth switch S14 are closed, and the eighth switch S8, the tenth switch S10, and the twelfth switch S12 are opened, so that the second sub-capacitor Co2 is connected to the first sub-capacitor Co1 as an integrating capacitor, so that the second sub-capacitor Co2 can store the capacitor voltage V Co2 , the capacitor voltage V stored in the first sub-capacitor itself Co1 The analog signal input terminal provides a margin voltage V res The second integrated voltage is obtained by superposition and is used as the output voltage V out3 The fourth sub-capacitor Ce2 is used as a storage capacitor to receive the second integrated voltage flowing through the second buffer BUFF2 as the voltage V stored in the fourth sub-capacitor Ce2 itself. Ce2 At this time, the voltage V stored in the fourth sub-capacitor Ce2 itself Ce2 =V Co1 +V Co2+ V res .

[0049] Figure 3 A circuit structure diagram of a noise shaping circuit according to another specific embodiment of the present disclosure is schematically shown.

[0050] like Figure 3As shown, in the operation cycle when the second sub-signal CLKS2 is at a high level, the second switch S2, the fourth switch S4, the sixth switch S6, the third ground switch QE3, the fourth ground switch QE4, the eleventh switch S11, and the thirteenth switch S13 are closed, and the first switch S1, the third switch S3, the fifth switch S5, the first ground switch QE1, and the second ground switch QE2 are opened, so that the third sub-capacitor Ce1 is connected to the analog signal input terminal as an integrating capacitor, so that the third sub-capacitor Ce1 can store the capacitor voltage V Ce1 The analog signal input terminal provides a margin voltage V res The third integrated voltage is obtained by superposition and is used as the output voltage V out2 Output from the output terminal; at the same time, provide the third integrated voltage to the first buffer BUFF1. The first sub-capacitor Co1 serves as a storage capacitor, receiving the third integrated voltage flowing through the first buffer BUFF1 as the voltage V stored in the first sub-capacitor Co1 itself. Co1 At this time, the voltage V stored in the first sub-capacitor Co1 itself Co1 =V Ce1 +V res .

[0051] In addition, during the operation cycle when the second sub-signal CLKS2 is at a high level, the eighth switch S8, the tenth switch S10, and the twelfth switch S12 are closed, and the seventh switch S7, the ninth switch S9, and the fourteenth switch S14 are opened, so that the fourth sub-capacitor Ce2 is connected to the third sub-capacitor Ce1 as an integrating capacitor, so that the fourth sub-capacitor Ce2 can store the capacitor voltage V Ce2 , the capacitor voltage V stored in the third sub-capacitor Ce1 itself Ce1 The analog signal input terminal provides a margin voltage V res The fourth integrated voltage is obtained by superposition and is used as the output voltage V out3 Output from the output terminal; at the same time, provide the fourth integrated voltage to the second buffer BUFF2. The second sub-capacitor Co2 serves as a storage capacitor, receiving the fourth integrated voltage flowing through the second buffer BUFF2 as the voltage V stored in the second sub-capacitor Co2 itself. Co2 At this time, the voltage V stored in the second sub-capacitor Co2 itself Co2 =V Ce1 + V Ce2+ V res .

[0052] Based on this, the embodiment of the present disclosure alternately uses multiple integration capacitors and multiple storage capacitors in the noise shaping circuit, and combines the switching of multiple switches to ensure the continuity of the integration process, which not only avoids the interference that may be caused by directly reading the integration result during the integration process, but also expands the higher-order structure to quantize the noise more finely to improve the signal-to-noise ratio of the analog-to-digital converter. In addition, by introducing a buffer and a storage capacitor to store the integration result, the circuit can achieve ideal integration without using an amplifier for subsequent analog-to-digital conversion.

[0053] According to an embodiment of the present disclosure, the noise shaping unit is further configured to connect the first capacitor or the second capacitor between the multiple output terminals of the buffer to process the differential voltage output by the buffer.

[0054] According to the embodiments of the present disclosure, since single-ended integration has problems such as easy saturation of the DC element of the integrating capacitor, buffer offset and common-mode voltage mismatch, a differential buffer can be used, and the integrating capacitor is set between multiple output terminals of the differential buffer. The differential buffer and the integrating capacitor are used to perform differential integration, so as to use the differential signal to offset part of the DC offset, so as to avoid saturation of the integrating capacitor and buffer offset.

[0055] According to the embodiments of the present disclosure, the buffer and storage capacitor can also be chopped to achieve differential integration. Under the same kT / C noise, the use of differential integration can reduce the total storage capacitor size in the differential ADC by 4 times compared with single-ended integration, thereby reducing the complexity and cost of the circuit. In addition, the use of chopping technology to periodically flip the noise shaping circuit can reduce the flicker noise of the buffer, thereby reducing its impact on the integration result.

[0056] Figure 4 The figure schematically shows a noise shaping circuit using differential integration according to a specific embodiment of the present disclosure.

[0057] like Figure 4 As shown in FIG. 1 , in a second-order noise shaping circuit using differential integration, the first sub-capacitor Co1 is stacked on the upper plate of the capacitor of the digital-to-analog conversion circuit. At the same time, the second sub-capacitor Co2 is stacked on the lower plate of the capacitor of the digital-to-analog conversion circuit. According to the charge conservation principle of the capacitor, when a new signal voltage is added to the capacitor, it will be added to the original voltage on the capacitor. Therefore, this stacking operation realizes the integration result of the current input signal and the previous operation cycle, that is, the capacitor voltage V stored in the first sub-capacitor Co1 itself. Co1 and the capacitor voltage V stored in the second sub-capacitor Co2 itself Co2 Specifically, the digital-to-analog conversion circuit (DAC) generates an unquantized residual voltage V according to the input digital code. res The noise shaping circuit obtains the residual voltage V from the DAC plateres , the margin voltage V res Based on the superposition of the integral capacitor and the voltage stored on the integral capacitor, the integral result is obtained, that is, V Ce2 =V Co1 + V Co2+ V res After the integration is completed, the integration result can be compared by starting the comparator to determine whether the integration result has reached the conversion threshold and trigger the sampling or conversion process of the ADC. In the next operation cycle, the noise shaping circuit is flipped to perform the chopping operation, and the third sub-capacitor Ce1 is stacked on the capacitor p-plate of the digital-to-analog conversion circuit. At the same time, the fourth sub-capacitor Ce2 is stacked on the capacitor n-plate of the digital-to-analog conversion circuit to achieve the capacitor voltage V stored in the third sub-capacitor Ce1 itself. Ce1 and the capacitor voltage V stored in the fourth sub-capacitor Ce2 itself Ce2 The noise shaping circuit obtains the remaining voltage V from the DAC plate. res , the margin voltage V res Based on the superposition of the integral capacitor and the voltage stored on the integral capacitor, the integral result is obtained, that is, V Co2 =V Ce1 + V Ce2+ V res .

[0058] According to an embodiment of the present disclosure, multiple switches are configured as a charge pump switch structure, and the charge pump switch structure is configured to control the conduction and shutdown of multiple switch tubes in response to a two-phase non-overlapping clock signal to achieve an increase in the overdrive voltage of each of the multiple switches.

[0059] According to an embodiment of the present disclosure, due to the increase in threshold voltage at low temperatures, traditional switches have a slow turn-on speed and a large on-resistance. Therefore, multiple switches in the present disclosure all adopt a charge pump switch structure, which includes multiple switch tubes. The multiple switch tubes realize charge transfer and voltage increase under the control of two-phase non-overlapping clock signals.

[0060] Figure 5 The schematic diagram of the charge pump switch structure according to a specific embodiment of the present disclosure is shown schematically.

[0061] like Figure 5 As shown, the charge pump switch structure includes a first switch tube M1, a second switch tube M2, a third switch tube M3, a fourth switch tube M4 and a fifth switch tube M5, and also includes a first switch capacitor C1 and a second switch capacitor C2. The two-phase non-overlapping clock signal controlling the charge pump switch structure includes a first clock signal CLKS and a second clock signal CLKSB.

[0062] Among them, the source of the first switch tube M1 is connected to the power supply VDD, the drain of the first switch tube M1 is connected to the upper plate of the first switch capacitor C1, and the gate of the first switch tube M1 is connected to the upper plate of the second switch capacitor C2. The source of the second switch tube M2 is connected to the power supply VDD, the drain of the second switch tube M2 is connected to the upper plate of the second switch capacitor C2, and the gate of the second switch tube M2 is connected to the upper plate of the first switch capacitor C1. The source of the third switch tube M3 is connected to the CLKSBOOST signal line, the drain of the third switch tube M3 is connected to the upper plate of the first switch capacitor C1, and the gate of the third switch tube M3 is connected to the power supply VDD to ensure that it is turned on in the boost stage. The source of the fourth switch tube M4 is connected to the first clock signal CLKS, the drain of the fourth switch tube M4 is connected to the CLKSBOOST signal line, and the gate of the fourth switch tube M4 is connected to the power supply VDD to ensure that it is turned on in the reset phase and turned off in the boost phase; the gate of the fifth switch tube M5 is connected to the CLKSBOOST signal line, the source of the fifth switch tube M5 is connected to the input voltage VIN, and the drain of the fifth switch tube M5 is connected to the output voltage VOUT.

[0063] According to an embodiment of the present disclosure, the charge pump switch structure includes a reset stage and a boost stage.

[0064] Specifically, in the reset phase, when the first clock signal CLKS is at a low level, the second clock signal CLKSB is at a high level, and the fourth switch tube M4 is turned on, pulling the CLKSBOOST signal line down to a low level. At the same time, the lower plates of the first switch capacitor C1 and the second switch capacitor C2 are connected to the low level VSS and the high level VDD, respectively, to prepare for the subsequent boost phase. In this phase, the first switch tube M1 is turned on and charges the upper plate of the first switch capacitor C1, while the second switch tube M2 and the third switch tube M3 are in the off state.

[0065] In the boost phase, when the first clock signal CLKS is at a high level (VDD), the second clock signal CLKSB is at a low level, and the fourth switch tube M4 is turned off. The connection state of the lower plates of the first switch capacitor C1 and the second switch capacitor C2 is reversed, the lower plate of the first switch capacitor C1 becomes a high level VDD, and the lower plate of the second switch capacitor C2 becomes a low level VSS. Since the first switch capacitor C1 has been charged to VDD in the reset phase, the upper plate voltage of the first switch capacitor C1 will be raised to 2VDD in the boost phase. At this time, the third switch tube M3 is turned on, and the voltage of the upper plate of the first switch capacitor C1 is transmitted to the CLKSBOOST signal line to achieve boost output, thereby driving the fifth switch tube M5 to turn on.

[0066] Based on this, the embodiments of the present disclosure precisely control the two-phase non-overlapping clock signals to ensure that the charge pump switch structure smoothly transitions between the reset and boost stages, thereby outputting a stable boost voltage, significantly improving the overdrive voltage of multiple switches while reducing resistance to maintain good linearity, thereby avoiding nonlinear errors that may occur in integration.

[0067] Figure 6 The schematic diagram shows a circuit structure of an analog-to-digital converter according to an embodiment of the present disclosure.

[0068] like Figure 6 As shown, the analog-to-digital converter includes a capacitor array 1, a noise shaping circuit 2, an amplifier 3 and a digital logic circuit 4.

[0069] According to an embodiment of the present disclosure, the noise shaping circuit 2 can output an integrated voltage to the amplifier 3 based on the residual voltage provided by the capacitor array 1, and realize integration by capacitor stacking. In addition, since the buffer is simple and has little influence on PVT alignment, and a differential buffer is used as a buffer, and the storage capacitor is integrated and the integration result is stored, so that the integration and storage operations are alternately performed between multiple capacitors to achieve a continuous integration process without using a closed-loop amplifier, and a sharp NTF with zero close to the unit circle is realized. At the same time, the quantization noise or other types of noise are pushed to a higher frequency range, and a lower noise level and higher resolution are achieved within the target bandwidth.

[0070] According to an embodiment of the present disclosure, the capacitor array 1 can be used to sample and hold the charge of the input signal. In the sampling phase, the capacitor array 1 captures the charge of the input signal; in the holding phase, the capacitor array 1 holds the captured charge for subsequent circuit processing. The capacitor array 1 also participates in providing a residual voltage Vres to the noise shaping circuit 2, and receives the residual voltage Vres fed back by the digital logic circuit 4 for the next round of sampling and holding.

[0071] According to an embodiment of the present disclosure, the amplifier 3 may be used to enhance the amplitude of the integrated voltage so that the subsequent digital logic circuit 4 can accurately identify and convert it.

[0072] According to an embodiment of the present disclosure, the digital logic circuit 4 can be used to perform analog-to-digital conversion on the amplified integrated voltage to obtain a conversion result, wherein the conversion result includes the residual voltage Vres. The digital logic circuit 4 feeds back the residual voltage Vres to the capacitor array so that the capacitor array performs the next round of sampling, holding and integration process based on the fed-back residual voltage. Through multiple iterations, the analog-to-digital converter gradually approaches the true value of the input signal and outputs a high-precision digital signal.

[0073] In one embodiment of the present disclosure, the method can achieve 93.3 dB SNDR at a bandwidth of 250 kHz with an oversampling rate (OSR) of 10. Since the analog-to-digital conversion circuit can achieve an SNDR of more than 90 dB with a bandwidth greater than 100 kHz, it indicates that the integrity of the signal can be well maintained during the conversion process while suppressing noise and distortion. At the same time, it consumes 340 μW of power, indicating that the analog-to-digital conversion circuit maintains low energy consumption while providing high performance.

[0074] Based on this, the embodiments of the present disclosure use a noise shaping circuit and multiple iterations to enable the proposed analog-to-digital converter to approximate the true value of the input signal, thereby achieving high-precision, low-noise, and low-power analog-to-digital conversion functions. In addition, the noise shaping circuit proposed in the present disclosure can push quantization noise or other types of noise to a higher frequency range, thereby achieving a lower noise level within the target bandwidth.

[0075] So far, the embodiments of the present disclosure have been described in detail in conjunction with the accompanying drawings. It should be noted that the implementation methods not shown or described in the drawings or the body of the specification are all forms known to ordinary technicians in the relevant technical field and are not described in detail. In addition, the above definitions of each element and method are not limited to the various specific structures, shapes or methods mentioned in the embodiments, and ordinary technicians in the field can simply change or replace them.

[0076] Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or constructions will be omitted when they may cause confusion in the understanding of the present disclosure.

[0077] Moreover, the shapes and sizes of the components in the figures do not reflect the real size and proportion, but only illustrate the contents of the embodiments of the present disclosure. In addition, in the claims, any reference symbols between brackets shall not be constructed as limiting the claims.

[0078] Unless otherwise indicated, the numerical parameters in this specification and the appended claims are approximate values ​​and can vary according to the desired properties obtained through the content of the present disclosure. In particular, all numbers used in the specification and claims to express the content of the composition, reaction conditions, etc., should be understood to be modified by the term "about" in all cases. Furthermore, the word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

[0079] The ordinal numbers used in the specification and claims, such as "first", "second", "third", etc., to modify the corresponding elements, do not themselves mean that the elements have any ordinal numbers, nor do they represent the order of one element and another element, or the order in the manufacturing method. The use of these ordinal numbers is only used to clearly distinguish a component with a certain name from another component with the same name.

[0080] It will be appreciated by those skilled in the art that the features described in the various embodiments of the present disclosure may be combined and / or combined in a variety of ways, even if such combinations or combinations are not explicitly described in the present disclosure. In particular, without departing from the spirit and teachings of the present disclosure, the features described in the various embodiments of the present disclosure may be combined and / or combined in a variety of ways. All of these combinations and / or combinations fall within the scope of the present disclosure.

[0081] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present disclosure. Although the embodiments are described above, this does not mean that the measures in the various embodiments cannot be used in combination to advantage. Without departing from the scope of the present disclosure, those skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A noise shaping circuit, wherein: The noise shaping circuit includes: a plurality of switches, a first capacitor, a second capacitor, and a buffer connected between the first capacitor and the second capacitor; The plurality of switches are configured to, in response to a switch control signal, alternately connect one of the first capacitor and the second capacitor as an integral capacitor to the analog signal input terminal, so that the integral capacitor provides an integral voltage to the buffer based on the residual voltage provided by the analog signal input terminal and the capacitor voltage stored therein, and to connect the other of the first capacitor and the second capacitor as a storage capacitor to receive and store the integral voltage flowing through the buffer; The integration capacitor is configured to output the integration voltage to the output terminal of the noise shaping circuit, so that the digital logic circuit performs analog-to-digital conversion on the integration voltage to obtain the residual voltage and provide it to the analog signal input terminal.

2. The circuit according to claim 1, wherein The multiple switches include a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a ninth switch, a tenth switch, an eleventh switch, a twelfth switch, a thirteenth switch, and a fourteenth switch; the first capacitor includes a first sub-capacitor and a second sub-capacitor, the second capacitor includes a third sub-capacitor and a fourth sub-capacitor, and the buffer includes a first buffer and a second buffer.

3. The circuit according to claim 2, wherein: The noise shaping unit is configured such that a first end of the first switch is connected to the analog signal input end, a second end of the first switch is connected to a first end of the first sub-capacitor, a second end of the first sub-capacitor is connected to a first end of the third switch and a second end of the fourth switch via the thirteenth switch, a second end of the third switch is connected to a first end of the first buffer and a first end of the output end of the noise shaping circuit, a second end of the first buffer is connected to a first end of the fifth switch and a first end of the fourth switch, and a second end of the fifth switch is connected to a second end of the third sub-capacitor via the eleventh switch; A first end of the second switch is connected to the analog signal input end, a second end of the second switch is connected to a first end of the third sub-capacitor, a first end of the sixth switch is connected to a second end of the third sub-capacitor, and a second end of the sixth switch is connected to a first end of the first buffer.

4. The circuit according to claim 3, wherein: The noise shaping unit is further configured such that the first end of the second sub-capacitor is connected to the second end of the first sub-capacitor via the thirteenth switch and the fourteenth switch, the second end of the second sub-capacitor is connected to the first end of the seventh switch and the second end of the eighth switch, the second end of the seventh switch is connected to the first end of the second buffer and the first end of the comparator, the second end of the second buffer is connected to the first end of the ninth switch and the first end of the eighth switch, and the second end of the ninth switch is connected to the second end of the fourth sub-capacitor; The first end of the fourth sub-capacitor is connected to the second end of the third sub-capacitor via the eleventh switch and the twelfth switch respectively, the first end of the tenth switch is connected to the second end of the fourth sub-capacitor, and the second end of the tenth switch is connected to the first end of the second buffer.

5. The circuit according to claim 4, wherein: The switch control signal is a periodic signal, and the switch control signal includes a first sub-signal and a second sub-signal; the first sub-signal and the second sub-signal are alternately configured to be a high level based on a time period.

6. The circuit according to claim 5, wherein: The plurality of switches are configured to, in response to the first sub-signal, control the first switch, the third switch, the fifth switch, the eleventh switch, and the thirteenth switch to be closed, and the second switch, the fourth switch, and the sixth switch to be opened, so that the first sub-capacitor is connected to the analog signal input terminal as the integral capacitor, so that the first sub-capacitor superimposes the capacitor voltage stored in itself with the residual voltage provided by the analog signal input terminal to obtain a first integral voltage, and provides the first integral voltage to the first buffer, and enables the third sub-capacitor to serve as the storage capacitor to receive and store the first integral voltage flowing through the first buffer; The multiple switches are also configured to control the seventh switch, the ninth switch, and the fourteenth switch to be closed, and control the eighth switch, the tenth switch, and the twelfth switch to be opened in response to the first sub-signal, so that the second sub-capacitor is connected to the first sub-capacitor as the integral capacitor, so that the second sub-capacitor superimposes the capacitor voltage stored in itself, the capacitor voltage stored in itself by the first sub-capacitor, and the residual voltage provided by the analog signal input terminal to obtain a second integral voltage, and provides the second integral voltage to the second buffer, and enables the fourth sub-capacitor to serve as the storage capacitor to receive and store the second integral voltage flowing through the second buffer.

7. The circuit according to claim 5, wherein: The plurality of switches are configured to, in response to the second sub-signal, control the second switch, the fourth switch, the sixth switch, the eleventh switch, and the thirteenth switch to be closed, and control the first switch, the third switch, and the fifth switch to be opened, so that the third sub-capacitor is connected to the analog signal input terminal as the integral capacitor, so that the third sub-capacitor superimposes the capacitor voltage stored in itself with the residual voltage provided by the analog signal input terminal to obtain a third integral voltage, and provides the third integral voltage to the first buffer, and enables the first sub-capacitor to serve as the storage capacitor to receive and store the third integral voltage flowing through the first buffer; The multiple switches are also configured to control the eighth switch, the tenth switch, and the twelfth switch to be closed, and control the seventh switch, the ninth switch, and the fourteenth switch to be opened in response to the second sub-signal, so that the fourth sub-capacitor is connected to the third sub-capacitor as the integrating capacitor, so that the fourth sub-capacitor superimposes the capacitor voltage stored in itself, the capacitor voltage stored in itself by the third sub-capacitor, and the residual voltage provided by the analog signal input terminal to obtain a fourth integrated voltage, and provides the fourth integrated voltage to the second buffer, and enables the second sub-capacitor to serve as the storage capacitor to receive and store the fourth integrated voltage flowing through the second buffer.

8. The circuit according to any one of claims 1 to 7, wherein: The buffer includes a differential buffer, and the noise shaping circuit is further configured to connect the first capacitor or the second capacitor between multiple output terminals of the differential buffer to process a differential voltage output by the differential buffer.

9. The circuit according to any one of claims 1 to 8, wherein: The multiple switches are configured as a charge pump switch structure, and the charge pump switch structure is configured to control the on and off of the multiple switch tubes in response to a two-phase non-overlapping clock signal to achieve the increase of the overdrive voltage of each of the multiple switches.

10. An analog-to-digital converter, comprising: The noise shaping circuit, capacitor array, amplifier and digital logic circuit according to any one of claims 1 to 9; Wherein, the noise shaping circuit outputs an integrated voltage to the amplifier based on the residual voltage provided by the capacitor array; The amplifier and the digital logic circuit perform analog-to-digital conversion on the integrated voltage to obtain a conversion result, wherein the conversion result includes the residual voltage; The digital logic circuit provides the margin voltage to the capacitor array.

Images