Semiconductor device and method for manufacturing semiconductor device

Abstract

The present disclosure provides a semiconductor device capable of reducing gate leakage and a method of manufacturing the semiconductor device. The semiconductor device includes: a nitride semiconductor layer; a dielectric nitrogen oxide film provided on the nitride semiconductor layer and having a first surface facing the nitride semiconductor layer; and a gate electrode provided on the dielectric nitrogen oxide film, the surface of the nitride semiconductor layer facing the dielectric nitrogen oxide film having nitrogen polarity.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] Conventionally, a high electron mobility transistor (HEMT) in which a channel layer is formed on a barrier layer has been proposed. Also, hafnium silicate having a high relative dielectric constant is known as a material for a gate insulating film.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application No. 2009-506537

[0006] Patent Document 2: Japanese Patent Application Laid-Open No. 5-223855

[0007] Patent Document 3: International Publication No. 2005 / 119787

[0008] In recent years, the demand for reduction of gate leakage has been increasing. Summary of the invention

[0009] An object of the present disclosure is to provide a semiconductor device and a method for manufacturing the semiconductor device that can reduce gate leakage.

[0010] The semiconductor device disclosed in the present invention comprises: a nitride semiconductor layer; a dielectric nitride oxide film, which is arranged on the nitride semiconductor layer and has a first surface opposite to the nitride semiconductor layer; and a gate electrode, which is arranged on the dielectric nitride oxide film, and the surface of the nitride semiconductor layer opposite to the dielectric nitride oxide film has nitrogen polarity.

[0011] Effects of the Invention

[0012] According to the present disclosure, gate leakage can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a cross-sectional view showing a semiconductor device according to an embodiment.

[0014] Figure 2 It is a cross-sectional view showing the structure of a dielectric oxynitride film.

[0015] Figure 3 This is a graph showing the trend of bonding strength measured by X-ray photoelectron spectroscopy.

[0016] Figure 4 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment (Part 1).

[0017] Figure 5 This is a cross-sectional view showing the method for manufacturing a semiconductor device according to the embodiment (part 2).

[0018] Figure 6 It is a cross-sectional view showing the method for manufacturing a semiconductor device according to the embodiment (part 3).

[0019] Figure 7 It is a cross-sectional view showing the method for manufacturing a semiconductor device according to an embodiment (Part 4).

[0020] Figure 8 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment (Part 5).

[0021] Fig. 9 It is a cross-sectional view showing the method for manufacturing a semiconductor device according to an embodiment (the sixth).

[0022] Fig.10 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment (part seven).

[0023] Description of Reference Numerals

[0024] 1: Semiconductor devices;

[0025] 10: Growth substrate;

[0026] 20: nitride semiconductor layer;

[0027] 21: buffer layer;

[0028] 22: barrier layer;

[0029] 23: spacer layer;

[0030] 24: channel layer;

[0031] 24A: upper surface;

[0032] 25: cap layer;

[0033] 26: channel area;

[0034] 31: Dielectric nitride oxide film;

[0035] 31A: first side;

[0036] 31B: Second side;

[0037] 31D, 31S, 50D, 50G, 50S: open;

[0038] 39: Dielectric oxide film;

[0039] 40D, 40S: concave part;

[0040] 41D, 41S: regrowth layer;

[0041] 42D: drain electrode;

[0042] 42S: source electrode;

[0043] 43: gate electrode;

[0044] 50: passivation film;

[0045] 61: First point;

[0046] 62: Second point;

[0047] 71: X-ray;

[0048] 72: Optoelectronics. DETAILED DESCRIPTION

[0049] [Description of Embodiments of the Present Disclosure]

[0050] First, embodiments of the present disclosure will be described by way of examples.

[0051] [1] A semiconductor device according to one embodiment of the present disclosure comprises: a nitride semiconductor layer; a dielectric nitride oxide film, which is disposed on the nitride semiconductor layer and has a first surface opposite to the nitride semiconductor layer; and a gate electrode, which is disposed on the dielectric nitride oxide film, and the surface of the nitride semiconductor layer opposite to the dielectric nitride oxide film has nitrogen polarity.

[0052] The surface of the nitride semiconductor layer facing the dielectric nitride oxide film has nitrogen polarity, thereby making it easy to achieve low resistance. In addition, the dielectric nitride oxide film functions as a gate insulating film. The dielectric nitride oxide film has higher insulation and withstand voltage than the dielectric oxide film, and can reduce gate leakage.

[0053] [2] In [1], a first concentration of nitrogen atoms at a first point in the dielectric nitride oxide film at a first distance from the first surface may be higher than a second concentration of nitrogen atoms at a second point in the dielectric nitride oxide film at a second distance from the first surface, wherein the second distance is longer than the first distance. In this case, the dielectric nitride oxide film has a high affinity with the nitride semiconductor layer, and an interface state formed at an interface between the dielectric nitride oxide film and the nitride semiconductor layer is easily reduced, thereby suppressing current collapse.

[0054] [3] In [2], the concentration of nitrogen atoms in the dielectric oxynitride film may change continuously with respect to the distance from the first surface. In this case, it is easy to increase the withstand voltage of the dielectric oxynitride film.

[0055] [4] In any one of [1] to [3], the dielectric oxynitride film may include at least one selected from the group consisting of hafnium, lanthanum, and zirconium. In this case, a high relative dielectric constant can be easily obtained in the dielectric oxynitride film.

[0056] [5] In [4], the dielectric oxynitride film may include at least one selected from the group consisting of silicon and aluminum. In this case, a high relative dielectric constant can be easily obtained in the dielectric oxynitride film.

[0057] [6] Another embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising the following steps: forming a dielectric oxide film having a relative dielectric constant higher than that of silicon dioxide on a nitride semiconductor layer; nitriding the dielectric oxide film to form a dielectric nitride oxide film; and forming a gate electrode on the dielectric nitride oxide film, wherein the surface of the nitride semiconductor layer opposite to the dielectric oxide film has nitrogen polarity.

[0058] The surface of the nitride semiconductor layer facing the dielectric oxide film has nitrogen polarity, thereby making it easy to achieve low resistance of the semiconductor device and reduce gate leakage.

[0059] [Details of the embodiments of the present disclosure]

[0060] The following describes the embodiments of the present disclosure in detail, but the present disclosure is not limited to these contents. It should be noted that in this specification and the drawings, for components having substantially the same functional configuration, repeated descriptions are sometimes omitted by marking the same figure numbers. In the present disclosure, "looking down" refers to observing an object from above.

[0061] The embodiment relates to a semiconductor device including a GaN-based high electron mobility transistor (HEMT). Figure 1 is a cross-sectional view showing a semiconductor device according to an embodiment.

[0062] like Figure 1 As shown, the semiconductor device 1 of the embodiment mainly includes a growth substrate 10, a nitride semiconductor layer 20, a dielectric oxynitride film 31, a passivation film 50, a regrown layer 41S, a regrown layer 41D, a gate electrode 43, a source electrode 42S, and a drain electrode 42D.

[0063] The growth substrate 10 is, for example, a semi-insulating silicon carbide (SiC) substrate. When the growth substrate 10 is a SiC substrate, the upper surface of the growth substrate 10 is a carbon (C) polar surface. When the surface of the growth substrate 10 is a C polar surface, the nitride semiconductor layer 20 can grow crystals with the nitrogen (N) polar surface as the growth surface.

[0064] The nitride semiconductor layer 20 includes a buffer layer 21 , a barrier layer 22 , a spacer layer 23 , a channel layer 24 , and a cap layer 25 .

[0065] The buffer layer 21 is located on the growth substrate 10. The buffer layer 21 is, for example, an aluminum nitride (AlN) layer. The thickness of the AlN layer is, for example, not less than 1 nm and not more than 2000 nm. The buffer layer 21 may also include an AlN layer and a GaN layer or an aluminum gallium nitride (AlGaN) layer on the AlN layer.

[0066] The barrier layer 22 is located on the buffer layer 21. The barrier layer 22 is, for example, an AlGaN layer. The band gap of the barrier layer 22 is greater than the band gap of the channel layer 24. The thickness of the barrier layer 22 is, for example, greater than 1 nm and less than 50 nm. The composition of the barrier layer 22 is, for example, Al Y Ga 1－Y N (0.15≤Y≤0.55). The conductivity type of the barrier layer 22 is, for example, n-type or non-doped (i-type). A scandium aluminum nitride (ScAlN) layer, an indium aluminum nitride (InAlN) layer, or an indium aluminum gallium nitride (InAlGaN) layer may be used instead of the AlGaN layer.

[0067] The spacer layer 23 is located on the barrier layer 22. The spacer layer 23 is, for example, an AlN layer. The thickness of the spacer layer 23 is, for example, in the range of 0.2 nm to 5 nm.

[0068] The channel layer 24 is located on the spacer layer 23. The channel layer 24 is, for example, a GaN layer. The band gap of the channel layer 24 is smaller than the band gap of the barrier layer 22. The thickness of the channel layer 24 is, for example, greater than 1 nm and less than 50 nm. Between the channel layer 24 and the barrier layer 22 and the spacer layer 23, strain is generated due to the difference in their lattice constants, and the strain causes piezoelectric charge at the interface between the two. As a result, a two-dimensional electron gas (two dimensional electron gas: 2DEG) is generated near the surface of the channel layer 24 that is opposite to the barrier layer 22, and a channel region 26 is formed. The conductivity type of the channel layer 24 is, for example, n-type or non-doped (i-type).

[0069] The cap layer 25 is located on the channel layer 24. The cap layer 25 is, for example, an AlGaN layer. The thickness of the cap layer 25 is, for example, not less than 0.1 nm and not more than 10 nm.

[0070] On the C-polarity surface of the SiC substrate, the buffer layer 21, the barrier layer 22, the spacer layer 23, the channel layer 24, and the cap layer 25 grow crystals with the N-polarity surface as the growth surface. Therefore, the upper surfaces of the buffer layer 21, the barrier layer 22, the spacer layer 23, the channel layer 24, and the cap layer 25 have N-polarity, and the lower surfaces have gallium (Ga) polarity.

[0071] A recess 40S for the source and a recess 40D for the drain are formed in the nitride semiconductor layer 20. The bottom of the recess 40S and the bottom of the recess 40D are closer to the lower surface of the nitride semiconductor layer 20 than the upper surface 24A of the channel layer 24. That is, the recess 40S and the recess 40D are formed deeper than the upper surface 24A of the channel layer 24. The bottom of the recess 40S and the bottom of the recess 40D may be located in the channel layer 24, in the spacer layer 23, or in the barrier layer 22.

[0072] The dielectric nitride oxide film 31 is located on the nitride semiconductor layer 20. The dielectric nitride oxide film 31 is in contact with the upper surface of the nitride semiconductor layer 20. The relative dielectric constant of the dielectric nitride oxide film 31 is higher than the relative dielectric constant of silicon dioxide (SiO2). The dielectric nitride oxide film 31 is a high dielectric constant film. The dielectric nitride oxide film 31 may also include at least one selected from the group consisting of hafnium (Hf), lanthanum (La) and zirconium (Zr). In addition, the dielectric nitride oxide film 31 may also include at least one selected from the group consisting of silicon (Si) and aluminum (Al). For example, the dielectric nitride oxide film 31 is a hafnium silicon oxynitride (HfSiON) film or a hafnium aluminum oxynitride (HfAlON) film. The thickness of the dielectric nitride oxide film 31 is, for example, greater than 1 nm and less than 30 nm. An opening 31S for a source and an opening 31D for a drain are formed in the dielectric nitride oxide film 31. The opening 31S is connected to the recessed portion 40S, and the opening 31D is connected to the recessed portion 40D.

[0073] The regrown layer 41S is located on the channel layer 24, the spacer layer 23 or the barrier layer 22 in the recess 40S. The regrown layer 41D is located on the channel layer 24, the spacer layer 23 or the barrier layer 22 in the recess 40D. The regrown layer 41S and the regrown layer 41D are, for example, n-type GaN layers. The regrown layer 41S and the regrown layer 41D contain germanium (Ge) or Si as n-type impurities. The resistance of the regrown layer 41S and the regrown layer 41D is lower than the resistance of the channel layer 24. For example, the regrown layer 41S and the regrown layer 41D are formed by regrowing the n-type GaN layer after the recess 40S and the recess 40D are formed in the nitride semiconductor layer 20.

[0074] The source electrode 42S is located on the regrown layer 41S, and the drain electrode 42D is located on the regrown layer 41D. The source electrode 42S is in contact with the regrown layer 41S, and the drain electrode 42D is in contact with the regrown layer 41D. The source electrode 42S is in ohmic contact with the regrown layer 41S, and the drain electrode 42D is in ohmic contact with the regrown layer 41D.

[0075] The passivation film 50 covers the dielectric oxynitride film 31, the regrown layer 41S, the regrown layer 41D, the source electrode 42S, and the drain electrode 42D. The passivation film 50 is, for example, a silicon nitride (SiN) film. The thickness of the passivation film 50 is, for example, 5 nm or more and 100 nm or less in the portion where the thickness is uniform on the dielectric oxynitride film 31. An opening 50S for the source, an opening 50D for the drain, and an opening 50G for the gate are formed in the passivation film 50. A portion of the source electrode 42S is exposed from the opening 50S, and a portion of the drain electrode 42D is exposed from the opening 50D. When viewed from above, the opening 50G is located between the opening 50S and the opening 50D. A portion of the dielectric oxynitride film 31 is exposed from the opening 50G.

[0076] The gate electrode 43 is located between the source electrode 42S and the drain electrode 42D in a plan view. The gate electrode 43 is located on the passivation film 50 and the dielectric oxynitride film 31 and is in contact with the dielectric oxynitride film 31 via the opening 50G.

[0077] Here, the dielectric oxynitride film 31 will be further described. Figure 2 It is a cross-sectional view showing the structure of the dielectric oxynitride film 31 . Figure 3 This is a graph showing the trend of bonding strength measured by X-ray photoelectron spectroscopy (XPS).

[0078] In the present embodiment, the dielectric oxynitride film 31 has a first surface 31A facing the nitride semiconductor layer 20. The first concentration of N atoms at a first point 61 in the dielectric oxynitride film 31 at a first distance L1 from the first surface 31A is higher than the second concentration of N atoms at a second point 62 in the dielectric oxynitride film 31 at a second distance L2 from the first surface 31A. The second distance L2 is longer than the first distance L1. In the case where the dielectric oxynitride film 31 is an HfSiON film containing Hf as a transition metal element, the concentration of N atoms in the dielectric oxynitride film 31 can be determined based on the strength of the bond between Hf atoms and N atoms measured by XPS. That is, the higher the bond strength between Hf atoms and N atoms measured by XPS, the higher the concentration of N atoms in the dielectric oxynitride film 31.

[0079] In the determination of bond strength by XPS, Figure 2As shown, X-rays 71 are irradiated to the second surface 31B of the dielectric oxynitride film 31 opposite to the first surface 31A. In this case, the larger the angle (angle θ) formed by the second surface 31B and the irradiation direction of the X-rays 71, the deeper the X-rays 71 reach the dielectric oxynitride film 31. Then, the photoelectrons 72 released at the point reached by the X-rays 71 are detected outside the dielectric oxynitride film 31. Therefore, the bonding strength at points with different distances from the first surface 31A can be measured by changing the angle θ. In the present embodiment, when the bonding strength between Hf atoms and N atoms is measured for the dielectric oxynitride film 31, the bonding strength at the first point 61 is higher than the bonding strength at the second point 62.

[0080] For example, when the thickness of the dielectric oxynitride film 31 is 10 nm, if the angle θ is set to 85°, the bonding strength at a point where the distance from the first surface 31A is in the range of about 2 nm to about 3 nm can be obtained. If the angle θ is set to 45°, the bonding strength at a point where the distance from the first surface 31A is in the range of about 5 nm to about 6 nm can be obtained. If the angle θ is set to 30°, the bonding strength at a point where the distance from the first surface 31A is in the range of about 8 nm to about 9 nm can be obtained. Then, as Figure 3 As shown, the following result can be obtained: when the angle θ is larger, the bonding strength between the Hf atom and the N atom is higher.

[0081] Next, a method for manufacturing the semiconductor device 1 according to the embodiment will be described. Figures 4 to 10 It is a cross-sectional view showing a method for manufacturing the semiconductor device 1 according to the embodiment.

[0082] First, if Figure 4 As shown, a nitride semiconductor layer 20 is formed on a growth substrate 10 by metal organic chemical vapor deposition (MOCVD) method, for example. In the formation of the nitride semiconductor layer 20, a buffer layer 21, a barrier layer 22, a spacer layer 23, a channel layer 24 and a cap layer 25 are sequentially formed.

[0083] Then, if Figure 5As shown, a dielectric oxide film 39 is formed on the nitride semiconductor layer 20. The dielectric oxide film 39 can be formed, for example, by an atomic layer deposition (ALD) method. The dielectric oxide film 39 is in contact with the upper surface of the nitride semiconductor layer 20. The relative dielectric constant of the dielectric oxide film 39 is higher than the relative dielectric constant of silicon dioxide (SiO2). The dielectric oxide film 39 is a high dielectric constant film. The dielectric oxide film 39 may also include at least one selected from the group consisting of Hf, La, and Zr. In addition, the dielectric oxide film 39 may also include at least one selected from the group consisting of Si and Al. For example, the dielectric oxide film 39 is hafnium silicate (HfSiO X ) film or hafnium aluminate (HfAlO X The thickness of the dielectric oxide film 39 is, for example, not less than 1 nm and not more than 30 nm.

[0084] Then, if Figure 6 As shown, the dielectric oxide film 39 is nitrided to form the dielectric nitride oxide film 31. The nitridation of the dielectric oxide film 39 is performed in a chamber of a film forming device such as a CVD (Chemical Vapor Deposition) device. As an N source in the nitridation of the dielectric oxide film 39, for example, N atoms generated by thermally decomposing ammonia (NH3) are used. During the nitridation of the dielectric oxide film 39, the reduction of the dielectric oxide film 39 also occurs.

[0085] Then, if Figure 7 As shown, an opening 31S for the source and an opening 31D for the drain are formed in the dielectric nitride oxide film 31, and a recess 40S for the source and a recess 40D for the drain are formed in the nitride semiconductor layer 20. The bottom of the recess 40S and the bottom of the recess 40D may be closer to the lower surface of the nitride semiconductor layer 20 than the upper surface 24A of the channel layer 24. That is, the recess 40S and the bottom of the recess 40D may be formed deeper than the upper surface 24A of the channel layer 24. The bottom of the recess 40S and the bottom of the recess 40D may be located in the channel layer 24, in the spacer layer 23, or in the barrier layer 22.

[0086] The opening 31S, the opening 31D, the recess 40S, and the recess 40D can be formed by, for example, reactive ion etching (RIE) using a mask (not shown). For example, chlorine (Cl)-based gas is used as reactive gas in forming the opening 31S, the opening 31D, the recess 40S, and the recess 40D.

[0087] Then, if Figure 8As shown, a regrown layer 41S is formed in the recess 40S and on the channel layer 24, the spacer layer 23 or the barrier layer 22, and a regrown layer 41D is formed in the recess 40D and on the channel layer 24, the spacer layer 23 or the barrier layer 22. The regrown layer 41S and the regrown layer 41D can be formed by a physical vapor deposition (PVD) method such as evaporation, sputtering, or molecular beam epitaxy (MBE).

[0088] Then, if Fig. 9 As shown, a source electrode 42S is formed on the regrown layer 41S, and a drain electrode 42D is formed on the regrown layer 41D. In forming the source electrode 42S and the drain electrode 42D, first, a metal layer (not shown) constituting the source electrode 42S and the drain electrode 42D is formed. When forming the metal layer, for example, a growth mask (not shown) having an opening formed in a region where the metal layer is to be formed is used to form a film, and then the growth mask is removed together with the metal layer (not shown) formed thereon. That is, lift-off is performed.

[0089] Then, if Fig.10 As shown, a passivation film 50 is formed on the dielectric oxynitride film 31, the regrown layer 41S, the regrown layer 41D, the source electrode 42S, and the drain electrode 42D. The passivation film 50 covers the dielectric oxynitride film 31, the regrown layer 41S, the regrown layer 41D, the source electrode 42S, and the drain electrode 42D.

[0090] Next, an opening 50G for a gate is formed in the passivation film 50 (see Figure 1 The opening 50G can be formed, for example, by RIE using a mask (not shown). For example, in the formation of the opening 50G, a F (fluorine)-based gas is used as a reactive gas.

[0091] Next, a gate electrode 43 is formed on the passivation film 50 and the dielectric nitride oxide film 31 so as to be in contact with the dielectric nitride oxide film 31 via the opening 50G (see Figure 1 ). When forming the gate electrode 43, for example, a metal layer is formed using a growth mask (not shown) having an opening in a region where the gate electrode 43 is to be formed, and then the growth mask is removed together with the metal layer (not shown) formed thereon. That is, lift-off is performed.

[0092] Next, an opening 50S for the source and an opening 50D for the drain are formed in the passivation film 50 (see Figure 1 The opening 50S and the opening 50D can be formed, for example, by RIE using a mask (not shown). For example, in forming the opening 50S and the opening 50D, an F-based gas is used as a reactive gas.

[0093] In this way, the semiconductor device 1 can be manufactured.

[0094] It should be noted that the film forming device used for nitriding the dielectric oxide film 39 may be a low pressure chemical vapor deposition (LPCVD) device or a rapid thermal annealing (RTA) device. In addition, the N source in the nitriding of the dielectric oxide film 39 may be ammonia (NH3), nitrous oxide (N2O) or nitric oxide (NO) gas.

[0095] In the semiconductor device 1 of the embodiment, the surface of the nitride semiconductor layer 20 facing the dielectric oxide film 39 and the surface facing the dielectric nitride oxide film 31 after nitridation have N polarity, thereby easily shortening the distance between the channel region 26 and the source electrode 42S and the drain electrode 42D, and easily achieving low resistance.

[0096] The dielectric oxynitride film 31 functions as a gate insulating film. The dielectric oxynitride film 31 has higher insulation and withstand voltage than the dielectric oxide film 39, and according to this embodiment, gate leakage can be reduced.

[0097] In addition, the first concentration of N atoms at the first point 61 in the dielectric oxynitride film 31 is higher than the second concentration of N atoms at the second point 62 in the dielectric oxynitride film 31. That is, the concentration of N atoms is higher at a point closer to the first surface 31A. Therefore, the affinity between the dielectric oxynitride film 31 and the nitride semiconductor layer 20 is high, and the interface state formed at the interface between the dielectric oxynitride film 31 and the nitride semiconductor layer 20 can be reduced, thereby suppressing current collapse.

[0098] Furthermore, when the concentration of N atoms in the dielectric oxynitride film 31 changes continuously with respect to the distance from the first surface 31A, the electric field applied to the dielectric oxynitride film 31 is gradually relaxed, and the withstand voltage of the dielectric oxynitride film 31 can be improved.

[0099] The dielectric oxide film 39 includes at least one selected from the group consisting of hafnium, lanthanum, and zirconium, thereby making it easy to obtain a high relative dielectric constant in the dielectric oxynitride film 31. Furthermore, the dielectric oxide film 39 includes at least one selected from the group consisting of silicon and aluminum, thereby making it easy to obtain a high relative dielectric constant in the dielectric oxynitride film 31.

[0100] As mentioned above, although embodiment is described in detail, this disclosure is not limited to a specific embodiment, Various deformation|transformation and change are possible within the range described in a claim.

Claims

1. A semiconductor device comprising: a nitride semiconductor layer; a dielectric oxynitride film, provided on the nitride semiconductor layer, and having a first surface facing the nitride semiconductor layer; and A gate electrode is provided on the dielectric oxynitride film, A surface of the nitride semiconductor layer facing the dielectric oxynitride film has nitrogen polarity.

2. The semiconductor device according to claim 1, wherein A first concentration of nitrogen atoms at a first point in the dielectric oxynitride film at a first distance from the first surface is higher than a second concentration of nitrogen atoms at a second point in the dielectric oxynitride film at a second distance from the first surface, wherein the second distance is longer than the first distance.

3. The semiconductor device according to claim 2, wherein: The concentration of nitrogen atoms in the dielectric oxynitride film changes continuously with respect to the distance from the first surface.

4. The semiconductor device according to any one of claims 1 to 3, wherein: The dielectric oxynitride film includes at least one selected from the group consisting of hafnium, lanthanum, and zirconium.

5. The semiconductor device according to claim 4, wherein: The dielectric oxynitride film includes at least one selected from the group consisting of silicon and aluminum.

6. A method for manufacturing a semiconductor device, comprising the following steps: forming a dielectric oxide film having a relative dielectric constant higher than that of silicon dioxide on the nitride semiconductor layer; nitriding the dielectric oxide film to form a dielectric oxynitride film; and forming a gate electrode on the dielectric oxynitride film, A surface of the nitride semiconductor layer facing the dielectric oxide film has nitrogen polarity.

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