MOSFET cellular structure and manufacturing method thereof

Abstract

The invention provides an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) cellular structure and a manufacturing method thereof, and relates to the technical field of semiconductors. Comprising an N-type substrate; the N-type epitaxial layer is positioned on the surface of the substrate; the first JFET region, the second JFET region and the P-type shielding layer are located on the surface of the epitaxial layer, and the interface between the P-type shielding layer and the first JFET region and the interface between the P-type shielding layer and the second JFET region are arranged to be of an inclined structure; the first gate oxide layer and the first gate polycrystalline silicon layer are located at the top of the first JFET region, and the second gate oxide layer and the second gate polycrystalline silicon layer are located at the top of the second JFET region; the current channel expansion layer is located at the bottom corner of the first gate oxide layer and the second gate oxide layer; the first doped region, the second doped region, the third doped region and the fourth doped region are located on the side edges of the first gate oxide layer and the second gate oxide layer. The method has the advantages that the electric stress borne by the oxide layer at the corner position of the trench gate is reduced, the gate oxide failure probability is reduced, and the reliability and robustness of the device are greatly improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a MOSFET cell structure and a method for manufacturing the same. Background Art

[0002] The trench gate structure of SiC MOSFET has two major advantages. On the one hand, its longitudinal sidewalls The interface trap density in the crystal direction is low, which will effectively reduce the channel Coulomb scattering, making the channel carrier mobility u ch On the other hand, compared with planar gate, trench gate can significantly reduce chip size, thereby achieving lower parasitic capacitance and specific on-resistance R on,sp , while also reducing chip costs.

[0003] However, the gate oxide reliability problem of trench gate MOSFET is more serious than that of planar gate MOSFET. This is because when the device is in a high blocking voltage state, the electric field at the bottom corner of the trench gate is more concentrated, which can easily exceed the maximum critical electric field strength, thus causing the gate oxide layer to be broken down, affecting the reliability of the device.

[0004] In summary, in the prior art, there are problems that the corners of the trench gate MOSFET are easily broken down, and the reliability and robustness of the device are poor. Summary of the invention

[0005] The purpose of the present application is to provide a MOSFET cell structure and a method for manufacturing the same, so as to solve the problems in the prior art that the corners of the trench gate MOSFET are easily broken down and the device reliability and robustness are poor.

[0006] In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows: On the one hand, an embodiment of the present application provides a MOSFET cell structure, wherein the MOSFET cell structure includes: N-type substrate; An N-type epitaxial layer located on the surface of the substrate; A first JFET region and a second JFET region and a P-type shielding layer are located on the surface of the epitaxial layer, the first JFET region and the second JFET region are arranged at intervals, and the first JFET region and the second JFET region are both N-type; the interface between the P-type shielding layer and the first JFET region and the second JFET region is set to an inclined structure; A first gate oxide layer and a first gate polysilicon layer are located at the top of the first JFET region, wherein the first gate oxide layer wraps the first gate polysilicon layer; a second gate oxide layer and a second gate polysilicon layer are located at the top of the second JFET region, wherein the second gate oxide layer wraps the second gate polysilicon layer; A current channel expansion layer located at the bottom corner of the first gate oxide layer and the second gate oxide layer, wherein part of the current channel expansion layer is located on the surface of the first JFET region and the second JFET region, and another part of the current channel expansion layer is located on the side wall of the first gate oxide layer, and the current channel expansion layer is N-type doped; a first doping region, a second doping region, a third doping region and a fourth doping region located at the sides of the first gate oxide layer and the second gate oxide layer, the first doping region, the second doping region and the third doping region being arranged layer by layer in a direction away from the substrate and forming an integral body, one side of the integral body being in contact with the first gate oxide layer or the second gate oxide layer, and the other side of the integral body being in contact with the fourth doping region, the thickness of the fourth doping region being greater than or equal to the sum of the thicknesses of the first doping region, the second doping region and the third doping region, the first doping region and the third doping region being N-type, and the second doping region and the fourth doping region being P-type; a first dielectric layer located on the surface of the first gate polysilicon layer, the first gate oxide layer and a portion of the third doped region, and a second dielectric layer located on the surface of the second gate polysilicon layer, the second gate oxide layer and a portion of the third doped region; A first metal layer is located on the surface and a second metal layer is located on the back side of the substrate.

[0007] Optionally, the P-type shielding layer includes a first shielding layer, a second shielding layer and a third shielding layer, the first shielding layer, the second shielding layer and the third shielding layer are arranged at intervals, and a first trapezoidal region is formed between the first shielding layer and the second shielding layer, a second trapezoidal region is formed between the second shielding layer and the third shielding layer, the first JFET region and the corresponding current channel expansion layer are located in the first trapezoidal region, and the second JFET region and the corresponding current channel expansion layer are located in the second trapezoidal region; Optionally, one of them is a regular trapezoidal structure with a bottom width greater than a top width, and the other is an inverted trapezoidal structure with a bottom width less than a top width.

[0008] Optionally, the included angle of the top of the inverted trapezoidal structure is [60°, 90°); the included angle of the top of the regular trapezoidal structure is (90°, 120].

[0009] Optionally, the current channel extension layer located on the surface of the first JFET region and on the sidewall of the first gate oxide layer together constitute a first inclined extension layer and a second inclined extension layer, the first inclined extension layer and the second inclined extension layer are symmetrically arranged, and the first inclined extension layer and the second inclined extension layer are respectively located on both sides of the first JFET region, and the first inclined extension layer, the middle area of ​​the first JFET region and the second inclined extension layer are all in contact with the first gate oxide layer; The current channel expansion layer located on the surface of the second JFET region and on the side wall of the second gate oxide layer together constitute a third inclined expansion layer and a fourth inclined expansion layer, the third inclined expansion layer and the fourth inclined expansion layer are symmetrically arranged, and the third inclined expansion layer and the fourth inclined expansion layer are respectively located on both sides of the second JFET region, and the third inclined expansion layer, the middle area of ​​the second JFET region and the fourth inclined expansion layer are all in contact with the second gate oxide layer.

[0010] Optionally, the current channel expansion layer located on the surface of the first JFET region and on the sidewall of the first gate oxide layer together constitute a first annular expansion layer, and the bottom of the first annular expansion layer contacts the first JFET region; The current channel expansion layer located on the surface of the second JFET region and on the sidewall of the second gate oxide layer together constitute a second annular expansion layer, and the bottom of the second annular expansion layer contacts the second JFET region.

[0011] Optionally, the current channel expansion layer located on the surface of the first JFET region and on the sidewall of the first gate oxide layer together constitute a first annular expansion layer, and the bottom of the first annular expansion layer contacts the first JFET region; wherein the first JFET region is located in the inverted trapezoidal structure region; The current channel expansion layer located on the surface of the second JFET region and on the side wall of the second gate oxide layer together constitute a first inclined expansion layer and a second inclined expansion layer, the first inclined expansion layer and the second inclined expansion layer are symmetrically arranged, and the first inclined expansion layer and the second inclined expansion layer are respectively located on both sides of the second JFET region, the first inclined expansion layer, the middle area of ​​the second JFET region and the second inclined expansion layer are all in contact with the second gate oxide layer; wherein, the second JFET region is located in the positive trapezoidal structure area.

[0012] Optionally, the ion concentration of the first JFET region is greater than the ion concentration of the current channel extension layer; and the ion concentration of the second JFET region is less than the ion concentration of the current channel extension layer.

[0013] Optionally, the N-type epitaxial layer includes an epitaxial sublayer and a current spreading layer, and the substrate, the epitaxial sublayer and the current spreading layer are connected layer by layer.

[0014] On the other hand, an embodiment of the present application further provides a method for manufacturing a MOSFET cell structure, which is used for the above cell structure, and the method includes: Providing an N-type substrate; Fabricating a first epitaxial layer based on the surface of the substrate; Fabricating a second epitaxial layer based on the surface of the first epitaxial layer; A first JFET region, a second JFET region and a P-type shielding layer are manufactured based on the second epitaxial layer, the first JFET region and the second JFET region are spaced apart, and the first JFET region and the second JFET region are both N-type; the interface between the P-type shielding layer and the first JFET region and the second JFET region is set to an inclined structure; Fabricating a third epitaxial layer based on the surface of the second epitaxial layer, and fabricating a first doped layer based on the third epitaxial layer; A fourth epitaxial layer is fabricated based on the surface of the third epitaxial layer, and a second doped layer and a third doped layer are fabricated based on the fourth epitaxial layer; wherein the first epitaxial layer, the second epitaxial layer, the third epitaxial layer and the fourth epitaxial layer are all N-type doped; Fabricating a fourth doping region, and forming a first doping region, a second doping region, and a third doping region; performing terminal ion implantation; Etching the third epitaxial layer and the fourth epitaxial layer to form a first gate trench and a second gate trench, and performing ion implantation at the bottom of the first gate trench and the second gate trench to form a current channel expansion layer; High temperature furnace tube annealing; A first gate oxide layer and a first gate polysilicon layer are sequentially manufactured based on the first gate trench, and a second gate oxide layer and a second gate polysilicon layer are sequentially manufactured based on the second gate trench; wherein the first gate oxide layer wraps the first gate polysilicon layer, and the second gate oxide layer wraps the second gate polysilicon layer; a current channel expansion layer is located at the bottom corner of the first gate oxide layer and the second gate oxide layer, and part of the current channel expansion layer is located on the surface of the first JFET region and the second JFET region, and another part of the current channel expansion layer is located on the side wall of the first gate oxide layer, and the current channel expansion layer is N-type doped; The first doping region, the second doping region and the third doping region are arranged layer by layer in a direction away from the substrate to form an integral body, one side of the integral body is in contact with the first gate oxide layer or the second gate oxide layer, and the other side of the integral body is in contact with the fourth doping region, the thickness of the fourth doping region is greater than or equal to the sum of the thicknesses of the first doping region, the second doping region and the third doping region, the first doping region and the third doping region are N-type, and the second doping region and the fourth doping region are P-type; Manufacturing a first dielectric layer located on the surface of the first gate polysilicon layer, the first gate oxide layer, and a portion of the third doped region, and manufacturing a second dielectric layer located on the surface of the second gate polysilicon layer, the second gate oxide layer, and a portion of the third doped region; A first metal layer located on the surface and a second metal layer located on the back side of the substrate are manufactured.

[0015] Compared with the prior art, this application has the following beneficial effects: The present application provides a MOSFET cell structure and a manufacturing method thereof, comprising an N-type substrate; an N-type epitaxial layer located on the surface of the current extension layer substrate; a first JFET region and a second JFET region and a P-type shielding layer located on the surface of the current extension layer epitaxial layer, the first JFET region of the current extension layer and the second JFET region of the current extension layer are arranged at intervals, and the first JFET region of the current extension layer and the second JFET region of the current extension layer are both N-type; an interface between the P-type shielding layer of the current extension layer and the first JFET region of the current extension layer and the second JFET region of the current extension layer is arranged as an inclined structure; a first JFET region located on the top of the first JFET region of the current extension layer The first gate oxide layer and the first gate polysilicon layer of the current expansion layer are arranged at the top of the second JFET region of the current expansion layer, and the first gate oxide layer of the current expansion layer wraps the first gate polysilicon layer of the current expansion layer; the second gate oxide layer and the second gate polysilicon layer are arranged at the top of the second JFET region of the current expansion layer, and the second gate oxide layer of the current expansion layer wraps the second gate polysilicon layer of the current expansion layer; the current channel expansion layer is located at the bottom corner of the first gate oxide layer of the current expansion layer and the second gate oxide layer of the current expansion layer, wherein part of the current expansion layer current channel expansion layer is located on the surface of the first JFET region and the second JFET region of the current expansion layer, and another part of the current expansion layer current channel expansion layer is located at the current expansion layer The first gate oxide layer of the current expansion layer is a side wall of the first gate oxide layer, and the current channel expansion layer is N-type doped; the first doped region, the second doped region, the third doped region and the fourth doped region are located on the sides of the first gate oxide layer of the current expansion layer and the second gate oxide layer of the current expansion layer, the first doped region of the current expansion layer, the second doped region of the current expansion layer and the third doped region of the current expansion layer are arranged layer by layer in a direction away from the substrate and form a whole, one side of the current expansion layer as a whole is in contact with the first gate oxide layer or the second gate oxide layer of the current expansion layer, and the other side of the current expansion layer as a whole is in contact with the fourth doped region of the current expansion layer, and the thickness of the fourth doped region of the current expansion layer is greater than or equal to the first doped region of the current expansion layer The sum of the thicknesses of the doped region, the second doped region of the current spreading layer and the third doped region of the current spreading layer, the first doped region of the current spreading layer and the third doped region of the current spreading layer are N-type, and the second doped region of the current spreading layer and the fourth doped region of the current spreading layer are P-type; a first dielectric layer located on the surface of the first gate polysilicon layer of the current spreading layer, the first gate oxide layer of the current spreading layer and part of the third doped region of the current spreading layer, a second dielectric layer located on the surface of the second gate polysilicon layer of the current spreading layer, the second gate oxide layer of the current spreading layer and part of the third doped region of the current spreading layer; a first metal layer located on the surface and a second metal layer located on the back of the current spreading layer substrate.

[0016] Since the MOSFET cell structure provided in the present application is provided with a current channel expansion layer and a P-type shielding layer, and the interface between the P-type shielding layer and the first JFET region and the second JFET region is set to an inclined structure. On the one hand, the P-type shielding layer and the surrounding N-type region can be made to form a "pinch-off" of the depletion region to shield and protect the middle gate oxide layer, reduce the electrical stress on the oxide layer at the corner of the trench gate, reduce the probability of gate oxide failure, and greatly improve the reliability of the gate oxide. On the other hand, by setting the interface to an inclined structure, an inclined PN structure can be formed, so that when the device is reverse blocked, its electric field distribution can be equivalent to a vertical structure superimposed on a linear gradient PN junction, thereby playing a flexible buffering role for the electric field at the corner of the gate oxide, further improving the flexibility of the gate oxide protection shielding and a more flexible balanced specific on-resistance R on,sp and short-circuit withstand capability SCWT, thereby improving device reliability and robustness.

[0017] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 A schematic diagram of the first structure of the MOSFET cell structure provided in an embodiment of the present application.

[0020] Figure 2 A second structural schematic diagram of the MOSFET cell structure provided in an embodiment of the present application.

[0021] Figure 3 A third structural schematic diagram of the MOSFET cell structure provided in an embodiment of the present application.

[0022] Figure 4 A fourth structural schematic diagram of the MOSFET cell structure provided in an embodiment of the present application.

[0023] Figure 5 This is a cross-sectional schematic diagram corresponding to S102 provided in an embodiment of the present application.

[0024] Figure 6 This is a cross-sectional schematic diagram corresponding to S103 provided in an embodiment of the present application.

[0025] Figure 7A cross-sectional schematic diagram corresponding to ion implantation of the first JFET region and the second JFET region provided in an embodiment of the present application.

[0026] Figure 8 A cross-sectional schematic diagram corresponding to P+ ion implantation provided in an embodiment of the present application.

[0027] Fig. 9 This is a cross-sectional schematic diagram corresponding to S105 provided in an embodiment of the present application.

[0028] Fig.10 This is a cross-sectional schematic diagram corresponding to S106 provided in an embodiment of the present application.

[0029] Fig.11 This is a cross-sectional schematic diagram corresponding to S107 provided in an embodiment of the present application.

[0030] Fig.12 This is a cross-sectional schematic diagram corresponding to S109 provided in an embodiment of the present application.

[0031] Fig.13 A cross-sectional schematic diagram corresponding to the formation of a current channel expansion layer by tilted ion implantation provided in an embodiment of the present application.

[0032] icon: 110-substrate; 121-epitaxial sublayer; 122-current spreading layer; 131-first shielding layer; 132-second shielding layer; 133-third shielding layer; 141-first JFET region; 142-second JFET region; 151-first inclined spreading layer; 152-second inclined spreading layer; 153-third inclined spreading layer; 154-fourth inclined spreading layer; 161-first doped region; 162-second doped region; 163-third doped region; 164-fourth doped region; 171-first gate oxide layer; 172-first gate polysilicon layer; 173-second gate oxide layer; 174-second gate polysilicon layer; 181-first dielectric layer; 182-second dielectric layer; 191-first metal layer; 192-second metal layer. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0034] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0035] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0036] It should be noted that, in this document, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0037] In the description of the present application, it should be noted that the terms "upper", "lower", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the product of the application is usually placed when in use. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0038] The trench gate structure of SiC MOSFET is currently widely used and has obvious advantages. However, as described in the background technology, when the device is in a high blocking voltage state, the electric field at the bottom corner of the trench gate is more concentrated, which is very easy to exceed the maximum critical electric field strength, thereby causing the gate oxide layer to be broken down, affecting the reliability of the device. Therefore, the use of an optimized internal structure to reduce the working electric field strength of the oxide layer at the bottom of the trench is the first problem that all current trench gate MOSFET structure designs need to solve.

[0039] However, gate oxide breakdown is usually related to the on-resistance R ds,on There is a trade-off relationship. According to the existing technical route in the industry, in the device structure design, when reducing the electrical stress on the oxide layer at the corner of the trench gate, it is easy to introduce additional JFET resistance, such as making the current path from the drain to the vertical channel more complicated, or sacrificing the number of current channels, which will lead to an increase in the on-resistance R ds,on Therefore, the gate oxide is designed to have higher reliability and on-resistance R ds,on Lower trench MOSFETs will have greater industrial value.

[0040] In view of this, in order to solve the above problems, an embodiment of the present application provides a MOSFET cell structure, which optimizes the structure of the gate oxide layer corners so that the gate oxide layer corners are not easily broken down, thereby improving the reliability and robustness of the device.

[0041] The following is an exemplary description of the MOSFET cell structure provided in this application: As an alternative implementation, see Figure 1 , the MOSFET cell structure includes: N-type substrate 110; N-type epitaxial layer located on the surface of substrate 110; first JFET region 141 and second JFET region 142 and P-type shielding layer located on the surface of epitaxial layer, first JFET region 141 and second JFET region 142 are arranged at intervals, and both first JFET region 141 and second JFET region 142 are N-type; the interface between P-type shielding layer and first JFET region 141 and second JFET region 142 is arranged as an inclined structure; first gate oxide layer 171 and first gate polysilicon layer 172 located on the top of first JFET region 141, The first gate oxide layer 171 wraps the first gate polysilicon layer 172; the second gate oxide layer 173 and the second gate polysilicon layer 174 are located at the top of the second JFET region 142, and the second gate oxide layer 173 wraps the second gate polysilicon layer 174; the current channel expansion layer is located at the bottom corner of the first gate oxide layer 171 and the second gate oxide layer 173, wherein part of the current channel expansion layer is located on the surface of the first JFET region 141 and the second JFET region 142, and another part of the current channel expansion layer is located on the side wall of the first gate oxide layer 171, and the current channel expansion layer The first doping region 161, the second doping region 162, the third doping region 163 and the fourth doping region 164 are located on the sides of the first gate oxide layer 171 and the second gate oxide layer 173. The first doping region 161, the second doping region 162 and the third doping region 163 are arranged layer by layer in a direction away from the substrate 110 to form a whole. One side of the whole is in contact with the first gate oxide layer 171 or the second gate oxide layer 173, and the other side of the whole is in contact with the fourth doping region 164. The thickness of the fourth doping region 164 is greater than or equal to the thickness of the first doping region 161 and the second doping region 1 62 and the third doping region 163, the first doping region 161 and the third doping region 163 are N-type, and the second doping region 162 and the fourth doping region 164 are P-type; a first dielectric layer 181 located on the surface of the first gate polysilicon layer 172, the first gate oxide layer 171 and a portion of the third doping region 163, a second dielectric layer 182 located on the surface of the second gate polysilicon layer 174, the second gate oxide layer 173 and a portion of the third doping region 163; a first metal layer 191 located on the surface of the device and a second metal layer 192 located on the back side of the substrate 110.

[0042] Since the MOSFET cell structure provided in the present application is provided with a current channel expansion layer and a P-type shielding layer, and the interface between the P-type shielding layer and the first JFET region 141 and the second JFET region 142 is set to an inclined structure. On the one hand, the P-type shielding layer and the surrounding N-type region can be "pinched off" to form a depletion region to shield and protect the middle gate oxide layer, reduce the electrical stress on the oxide layer at the corner of the trench gate, reduce the probability of gate oxide failure, and greatly improve the gate oxide reliability. On the other hand, by setting the interface to an inclined structure, an inclined PN structure can be formed, so that when the device is reverse blocked, its electric field distribution can be equivalent to a vertical structure superimposed on a linear gradient PN junction, thereby playing a flexible buffering role for the electric field at the corner of the gate oxide, further improving the flexibility of the gate oxide protection shielding and a more flexible balanced specific on-resistance R on,sp and short-circuit withstand capability SCWT, and improve device reliability and robustness.

[0043] In one implementation, the N-type epitaxial layer includes an epitaxial sublayer 121 and a current spreading layer 122, and the substrate 110, the epitaxial sublayer 121 and the current spreading layer 122 are connected layer by layer. In addition, the epitaxial sublayer 121 is N-doped, and the current spreading layer 122 is N+ doped.

[0044] It should be noted that in the present application, the MOSFET cell structure includes two gate structures. Therefore, in order to improve the two gate structures from being easily broken down at the corners, a first JFET region 141, a second JFET region 142 and a P-type shielding layer need to be made on the epitaxial layer. Optionally, the top width of the first JFET region 141 is equal to the width of the first gate oxide layer 171; the top width of the second JFET region 142 is equal to the width of the second gate oxide layer 173. That is, a first gate oxide layer 171 and a first gate polysilicon layer 172 are arranged on the top of the first JFET region 141, and the first gate oxide layer 171 wraps the first gate polysilicon layer 172; a second gate oxide layer 173 and a second gate polysilicon layer 174 are arranged on the top of the second JFET region 142, and the second gate oxide layer 173 wraps the second gate polysilicon layer 174.

[0045] At the same time, when making the P-type shielding layer, it is formed by inclined ion implantation. That is, the inclined ion implantation can be performed first to the left, and then to the right; or the inclined ion implantation can be performed first to the right, and then to the left; and thus the following can be formed: Figure 1The first shielding layer 131, the second shielding layer 132 and the third shielding layer 133 are shown, and the first shielding layer 131, the second shielding layer 132 and the third shielding layer 133 are arranged at intervals. Among them, the second shielding layer 132 is formed by ion implantation tilted to the left, and the first shielding layer 131 and the third shielding layer 133 are formed by ion implantation tilted to the right, so that a first trapezoidal region can be formed between the first shielding layer 131 and the second shielding layer 132, and a second trapezoidal region can be formed between the second shielding layer 132 and the third shielding layer 133. Moreover, one of the first trapezoidal region and the second trapezoidal region is a regular trapezoidal structure with a bottom width greater than a top width, and the other is an inverted trapezoidal structure with a bottom width less than a top width. As shown in FIG. Figure 1 In the figure, the first trapezoidal area on the left is an inverted trapezoidal structure, and the second trapezoidal area on the right is a regular trapezoidal structure.

[0046] Of course, in another implementation, the P-type shielding layer can also be formed by only one ion implantation. For example, when only P+ ion implantation is performed to the left, only a P+ shielding layer is formed on the epitaxial layer. Figure 1 The second shielding layer 132 in the middle is formed in the epitaxial layer; when only P+ ion implantation is performed to the right, only Figure 1 The first shielding layer 131 and the third shielding layer 133 are located on both sides.

[0047] In order to expand the current channel and flexibly modulate the current path, reduce the on-resistance, increase the switching speed and reduce the switching loss, the MOSFET cell structure also includes a current channel expansion layer located at the bottom corner of the first gate oxide layer 171 and the second gate oxide layer 173, wherein part of the current channel expansion layer is located on the surface of the first JFET region 141 and the second JFET region 142, and another part of the current channel expansion layer is located on the side wall of the first gate oxide layer 171, and the current channel expansion layer is N+ type doped.

[0048] It should be noted that, when making the P-type shielding layer, it is necessary to first make a layer of N-epitaxial, and then form the first JFET region 141 and the second JFET region 142 and the P-type shielding layer by ion implantation. Therefore, in the positive trapezoidal structure, a part of the N-region will be retained below the current channel expansion layer.

[0049] In one implementation, the current channel expansion layer may include two inclined expansion layers. In practical applications, this may be implemented in the form of inclined ion implantation. That is, during the first ion implantation, the implantation direction may be to the left, forming one of the inclined expansion layers. During the second ion implantation, the implantation direction may be to the right, forming another inclined expansion layer. Both inclined expansion layers need to be able to provide an N-type current channel, otherwise the implantation is invalid.

[0050] In another embodiment, the current channel expansion layer can be set as a ring-shaped expansion layer, and when performing ion implantation, the implantation area width needs to be greater than the gate trench width. At the same time, both need to be able to provide an N-type current channel, otherwise the implantation is invalid.

[0051] On this basis, the first current extension layer in the MOSFET cell structure provided by the present application can be set in the following ways: The first one, such as Figure 1 As shown, the two trapezoidal regions are both provided with inclined extension layers, so that the current channel extension layers located on the surface of the first JFET region 141 and on the sidewalls of the first gate oxide layer 171 together constitute the first inclined extension layer 151 and the second inclined extension layer 152, the first inclined extension layer 151 and the second inclined extension layer 152 are symmetrically arranged, and the first inclined extension layer 151 and the second inclined extension layer 152 are respectively located on both sides of the first JFET region 141, and the first inclined extension layer 151, the middle region of the first JFET region 141 and the second inclined extension layer 152 are all The third inclined expansion layer 153 and the fourth inclined expansion layer 154 are symmetrically arranged, and the third inclined expansion layer 153 and the fourth inclined expansion layer 154 are respectively located on both sides of the second JFET region 142, and the third inclined expansion layer 153, the middle area of ​​the second JFET region 142 and the fourth inclined expansion layer 154 are all in contact with the second gate oxide layer 173.

[0052] The second type, such as Figure 2 As shown, annular expansion layers are used in both trapezoidal regions, so that the current channel expansion layer located on the surface of the first JFET region 141 and the side wall of the first gate oxide layer 171 together constitute a first annular expansion layer, and the bottom of the first annular expansion layer is in contact with the first JFET region 141; the current channel expansion layer located on the surface of the second JFET region 142 and the side wall of the second gate oxide layer 173 together constitute a second annular expansion layer, and the bottom of the second annular expansion layer is in contact with the second JFET region 142.

[0053] The third type, such as Figure 3As shown, one of the two trapezoidal regions adopts an inclined expansion layer and the other adopts an annular expansion layer. The current channel expansion layer located on the surface of the first JFET region 141 and the side wall of the first gate oxide layer 171 together form a first annular expansion layer, and the bottom of the first annular expansion layer contacts the first JFET region 141; wherein the first JFET region 141 is located in the inverted trapezoidal structure region; the current channel expansion layer located on the surface of the second JFET region 142 and the side wall of the second gate oxide layer 173 together form a first inclined expansion layer 151 and a second inclined expansion layer 152, the first inclined expansion layer 151 and the second inclined expansion layer 152 are symmetrically arranged, and the first inclined expansion layer 151 and the second inclined expansion layer 152 are respectively located on both sides of the second JFET region 142, and the first inclined expansion layer 151, the middle region of the second JFET region 142 and the second inclined expansion layer 152 are all in contact with the second gate oxide layer 173; wherein the second JFET region 142 is located in the positive trapezoidal structure region.

[0054] Figure 3 In the embodiment, an annular expansion layer is provided in the inverted trapezoidal structure, and an inclined expansion layer is provided in the regular trapezoidal structure; of course, in another implementation, an inclined expansion layer may be provided in the inverted trapezoidal structure, and an annular expansion layer may be provided in the regular trapezoidal structure, which is not limited here.

[0055] Please continue reading Figure 1-Figure 3 , the side of the gate oxide layer also includes a first doping region 161, a second doping region 162, a third doping region 163 and a fourth doping region 164, the first doping region 161, the second doping region 162 and the third doping region 163 are arranged layer by layer in a direction away from the substrate 110 and form a whole, one side of the whole is in contact with the first gate oxide layer 171 or the second gate oxide layer 173, and the other side of the whole is in contact with the fourth doping region 164, the thickness of the fourth doping region 164 is greater than or equal to the sum of the thicknesses of the first doping region 161, the second doping region 162 and the third doping region 163, the first doping region 161 and the third doping region 163 are N-type, and the second doping region 162 and the fourth doping region 164 are P-type.

[0056] The first doping region 161 may adopt a conventional epitaxial layer concentration, i.e., N-doping. Alternatively, the first doping region 161 may also be used as the current spreading layer 122, i.e., N+ doping, which is not limited here. Furthermore, the second doping region 162 is used as a P-type well region, the third doping region 163 is used as an NP layer, and the fourth doping region 164 is used as a PP layer.

[0057] Of course, the MOSFET cell structure also includes a first dielectric layer 181 on the surface of the first gate polysilicon layer 172, the first gate oxide layer 171 and part of the third doped region 163, and a second dielectric layer 182 on the surface of the second gate polysilicon layer 174, the second gate oxide layer 173 and part of the third doped region 163. Both the first dielectric layer 181 and the second dielectric layer 182 can be ILD layers.

[0058] A first metal layer 191 is disposed on the surface of the MOSFET cell structure, and a second metal layer 192 is disposed on the back of the substrate 110. By way of example, the first metal layer 191 may be made of metal aluminum.

[0059] Combine the following Figure 1-Figure 4 , explain its related parameters: Please combine Figure 1 and Figure 4 When the current channel expansion layer is an inclined expansion layer, it is necessary to satisfy W1>W2, W1=W2+W5+W6, where W1 represents the total width of the groove and the second doping regions 162 on the left and right sides, W2 represents the groove width, W5 represents the width of the second doping region 162 on the left side of the groove, and W6 represents the width of the second doping region 162 on the right side of the groove. And W5 and W6 can be unequal, at this time, the device on-resistance Ron and short-circuit withstand capability SCWT can be flexibly adjusted, and the device performance, reliability and robustness can be flexibly controlled.

[0060] Moreover, in the inverted trapezoidal structure, each structure is symmetrically arranged, and in the normal trapezoidal structure, each structure is also symmetrically arranged. W31, W32 and W4 cannot be 0, and both W31 and W32 are greater than W4. In one implementation, W32 can be tilted to be greater than W1. When W4 is not 0, the ion concentration of the second JFET region 142 and the second JFET region 142 is less than the ion concentration of the current channel expansion layer, which is beneficial to improve the gate oxide breakdown reliability of the device of this structure.

[0061] In addition, to obtain a better gate oxide shielding effect, W71 and W72 must be less than or equal to W2. The smaller W71 and W72 are, the better the gate oxide electric field shielding effect is, and the better the modulation output characteristics are, but the larger the on-resistance is. Therefore, the size of W71 and W72 can be flexibly adjusted, and the gate oxide breakdown characteristics and the size of the on-resistance can be flexibly adjusted. Therefore, if Figure 4 , the angle a1 of the top of the inverted trapezoidal structure is [60°, 90°); the angle a2 of the top of the normal trapezoidal structure is (90°, 120]. Wherein, W4 represents the width of the first JFET region 141 or the second JFET region 142 in contact with the gate oxide layer, W31 represents the bottom width of the inverted trapezoidal structure, W71 represents the top width of the inverted trapezoidal structure, W32 represents the bottom width of the normal trapezoidal structure, and W72 represents the top width of the normal trapezoidal structure.

[0062] Among them, in the inverted trapezoidal structure, the larger W31 is (by adjusting the injection angle and injection depth of the P-type shielding layer, so that the angle a1 is a relatively large acute angle), and in the positive trapezoidal structure, the smaller W32 is (by adjusting the injection angle and injection depth of the P-type shielding layer, so that the angle a2 is a relatively small obtuse angle), the better the gate oxide shielding effect is, and the better the device modulation output characteristics are. Therefore, the size of W31, W71, W32, W72 and the angle can be flexibly adjusted, the device's anti-electromagnetic interference, oscillation, surge, overshoot ability can be flexibly adjusted, the device's effect of suppressing self-opening and false opening can be flexibly adjusted, and the on-resistance R can be flexibly balanced. onsp The contradiction between the short-circuit withstand capability SCWT is resolved, the gate oxide breakdown characteristics and the avalanche characteristics of the device are flexibly optimized, and the reliability and robustness of the device are flexibly improved.

[0063] Furthermore, if the device simultaneously introduces a P-type shielding layer, a first JFET region 141 and a second JFET region 142, a current channel expansion layer, a current expansion layer 122 and a first doping region 161, on the one hand, the current flow path can be flexibly and effectively modulated, the on-resistance can be reduced, the switching speed can be increased, and the switching loss can be reduced. On the other hand, by introducing a PN junction depletion region equivalent resistor and capacitor with automatic buffering suppression function into the current path, when an abnormal working condition occurs, the device can automatically and flexibly expand the PN depletion region at different positions, and then automatically generate depletion layer equivalent resistors and capacitors of different sizes, automatically suppressing EMI electromagnetic interference, oscillation, surge and other problems, and finally making the device more resistant to electromagnetic interference, oscillation, surge, voltage and current overshoot, better suppressing self-opening and false opening, stronger suppressing short circuit tolerance SCWT, better device avalanche characteristics, and better device reliability and robustness.

[0064] Similarly, in Figure 2 In the structure shown, the parameters can achieve the same effect. It should be noted that Figure 2 In the structure, the ion concentration of the first JFET region 141 and the second JFET region 142 needs to be greater than the ion concentration of the current channel extension layer to improve the gate oxide breakdown reliability of the device of this structure.

[0065] And in Figure 3 In the structure shown, the ion concentration of the first JFET region 141 is set to be greater than the ion concentration of the current channel expansion layer; and the ion concentration of the second JFET region 142 is less than the ion concentration of the current channel expansion layer, which is beneficial to improving the gate oxide breakdown reliability of this structural device.

[0066] Furthermore, the applicant has found that in an inverted trapezoidal structure, the annular expansion layer has a better buffering effect; while in a regular trapezoidal structure, the inclined expansion layer has a better buffering effect. Figure 3As shown, in the inverted trapezoidal structure of the present application, the current channel expansion layer adopts a ring expansion layer, and the ion concentration of the first JFET region 141 is greater than the ion concentration of the current channel expansion layer; while in the positive trapezoidal structure, the current channel expansion layer adopts an inclined expansion layer, and the ion concentration of the second JFET region 142 is less than the ion concentration of the current channel expansion layer. The use of this optimal combination scheme can achieve the best buffering effect of the high voltage and strong electric field at the gate oxide position, effectively reduce the peak electric field reaching the gate oxide, improve the gate oxide reliability, and solve the problems of long-term electrical stress damage, and finally achieve high stability of device performance and excellent reliability and robustness of the device.

[0067] Based on the above implementation, the embodiment of the present application further provides a method for manufacturing a MOSFET cell structure, which is used to manufacture the above MOSFET cell structure. The method includes: S101, providing an N-type substrate 110; S102, forming a first epitaxial layer based on the surface of the substrate 110; S103, forming a second epitaxial layer based on the surface of the first epitaxial layer; S104, manufacturing a first JFET region 141, a second JFET region 142 and a P-type shielding layer based on the second epitaxial layer, wherein the first JFET region 141 and the second JFET region 142 are spaced apart, and both the first JFET region 141 and the second JFET region 142 are N-type; the P-type shielding layer is adjacent to the first JFET region 141 and the second JFET region 142, and the interface between the P-type shielding layer and the first JFET region 141 and the second JFET region 142 is set to an inclined structure; S105, forming a third epitaxial layer based on the surface of the second epitaxial layer, and forming a first doped layer based on the third epitaxial layer; S106, forming a fourth epitaxial layer based on the surface of the third epitaxial layer, and forming a second doped layer and a third doped layer based on the fourth epitaxial layer; wherein the first epitaxial layer, the second epitaxial layer, the third epitaxial layer and the fourth epitaxial layer are all N-type doped; S107, manufacturing the fourth doping region 164, and forming the first doping region 161, the second doping region 162 and the third doping region 163; S108, performing terminal ion implantation; S109, etching the third epitaxial layer and the fourth epitaxial layer to form a first gate trench and a second gate trench, and performing ion implantation at the bottom of the first gate trench and the second gate trench to form a current channel expansion layer; S110, high temperature furnace tube annealing; S111, based on the first gate trench, a first gate oxide layer 171 and a first gate polysilicon layer 172 are sequentially manufactured, and based on the second gate trench, a second gate oxide layer 173 and a second gate polysilicon layer 174 are sequentially manufactured; wherein, the first gate oxide layer 171 is arranged to wrap the first gate polysilicon layer 172, and the second gate oxide layer 173 is arranged to wrap the second gate polysilicon layer 174; the current channel expansion layer is located at the bottom corner of the first gate oxide layer 171 and the second gate oxide layer 173, and part of the current channel expansion layer is located on the surface of the first JFET region 141 and the second JFET region 142, and another part of the current channel expansion layer is located on the side wall of the first gate oxide layer 171, and the current channel expansion layer is N-type doped; The first doping region 161, the second doping region 162 and the third doping region 163 are arranged layer by layer in a direction away from the substrate 110 to form an integral body, one side of the integral body is in contact with the first gate oxide layer 171 or the second gate oxide layer 173, and the other side of the integral body is in contact with the fourth doping region 164, the thickness of the fourth doping region 164 is greater than or equal to the sum of the thicknesses of the first doping region 161, the second doping region 162 and the third doping region 163, the first doping region 161 and the third doping region 163 are N-type, and the second doping region 162 and the fourth doping region 164 are P-type; S112, forming a first dielectric layer 181 on the surface of the first gate polysilicon layer 172, the first gate oxide layer 171 and a portion of the third doping region 163, and forming a second dielectric layer 182 on the surface of the second gate polysilicon layer 174, the second gate oxide layer 173 and a portion of the third doping region 163; S113 , manufacturing a first metal layer 191 on the surface and a second metal layer 192 on the back side of the substrate 110 .

[0068] Below Figure 1 Taking the structure shown in the figure as an example, the method for manufacturing the MOSFET cell structure provided by the present application is exemplarily described in combination with the accompanying drawings: See also Figure 5 First, a first epitaxial layer is formed on the surface of the substrate 110, wherein the first epitaxial layer may include an epitaxial sublayer 121 and a current spreading layer 122. Next, refer to Figure 6 A second epitaxial layer is formed on the surface of the first epitaxial layer, wherein the ion concentration of the second epitaxial layer is the same as that of the epitaxial sublayer 121 .

[0069] See also Figure 7 , ion implantation is performed into the first JFET region 141 and the second JFET region 142. Figure 8 , and then P+ ion implantation is performed, and a P-type shielding layer is formed by two tilted implantations.

[0070] Afterwards, see Fig. 9, forming a third epitaxial layer based on the surface of the second epitaxial layer, and forming a first doped layer based on the third epitaxial layer. Fig.10 , continue to fabricate a fourth epitaxial layer based on the surface of the third epitaxial layer, and a second doped layer and a third doped layer based on the fourth epitaxial layer.

[0071] See also Fig.11 , and make the fourth doping layer. Then, terminal ion implantation is performed.

[0072] See also Fig.12 , etching the gate trench.

[0073] See also Fig.13 , a current channel expansion layer is formed by using inclined ion implantation.

[0074] Afterwards, a first gate oxide layer 171 , a second gate oxide layer 173 , a first gate polysilicon layer 172 , a second gate polysilicon layer 174 , a first dielectric layer 181 , a second dielectric layer 182 , a first metal layer 191 , and a second metal layer 192 are fabricated, which will not be described in detail herein.

[0075] Of course, when it is necessary to manufacture MOSFET cell structures of other structures, it is only necessary to adjust the corresponding processes. Figure 2 When the MOSFET cell structure is shown, the rest of the process remains unchanged, and only the following adjustments need to be made: Fig.13 The corresponding ion implantation process is sufficient. That is, the ion implantation in the annular area is directly performed, and the width of the implantation area needs to be greater than the width of the groove. It is also required to provide an N-type current channel, otherwise the implantation is invalid.

[0076] When you need to make Figure 3 When the MOSFET cell structure shown in the figure is used, the other processes remain unchanged and only the following adjustments need to be made: Fig.13 The corresponding ion implantation process is sufficient. That is, in the inverted trapezoidal structure, the ion implantation in the annular area is directly performed, and the width of the implantation area needs to be greater than the width of the groove. It is also required to provide an N-type current channel, otherwise the implantation is invalid. Then, in the positive trapezoidal structure, the ion implantation with the tilted direction to the left is first used, and then the ion implantation with the tilted direction to the right is used, and it is required to provide an N-type current channel, otherwise the implantation is invalid.

[0077] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0078] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, and that the present application can be implemented in other specific forms without departing from the spirit or essential features of the present application. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present application. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A MOSFET cell structure, characterized in that: The MOSFET cell structure comprises: N-type substrate; An N-type epitaxial layer located on the surface of the substrate; A first JFET region and a second JFET region and a P-type shielding layer are located on the surface of the epitaxial layer, the first JFET region and the second JFET region are arranged at intervals, and the first JFET region and the second JFET region are both N-type; the interface between the P-type shielding layer and the first JFET region and the second JFET region is set to an inclined structure; A first gate oxide layer and a first gate polysilicon layer are located at the top of the first JFET region, wherein the first gate oxide layer wraps the first gate polysilicon layer; a second gate oxide layer and a second gate polysilicon layer are located at the top of the second JFET region, wherein the second gate oxide layer wraps the second gate polysilicon layer; A current channel expansion layer located at the bottom corner of the first gate oxide layer and the second gate oxide layer, wherein part of the current channel expansion layer is located on the surface of the first JFET region and the second JFET region, and another part of the current channel expansion layer is located on the side wall of the first gate oxide layer, and the current channel expansion layer is N-type doped; a first doping region, a second doping region, a third doping region and a fourth doping region located at the sides of the first gate oxide layer and the second gate oxide layer, the first doping region, the second doping region and the third doping region being arranged layer by layer in a direction away from the substrate and forming an integral body, one side of the integral body being in contact with the first gate oxide layer or the second gate oxide layer, and the other side of the integral body being in contact with the fourth doping region, the thickness of the fourth doping region being greater than or equal to the sum of the thicknesses of the first doping region, the second doping region and the third doping region, the first doping region and the third doping region being N-type, and the second doping region and the fourth doping region being P-type; a first dielectric layer located on the surface of the first gate polysilicon layer, the first gate oxide layer and a portion of the third doped region, and a second dielectric layer located on the surface of the second gate polysilicon layer, the second gate oxide layer and a portion of the third doped region; A first metal layer is located on the surface and a second metal layer is located on the back side of the substrate.

2. The MOSFET cell structure according to claim 1, wherein: The P-type shielding layer includes a first shielding layer, a second shielding layer and a third shielding layer, the first shielding layer, the second shielding layer and the third shielding layer are arranged at intervals, and a first trapezoidal region is formed between the first shielding layer and the second shielding layer, a second trapezoidal region is formed between the second shielding layer and the third shielding layer, the first JFET region and the corresponding current channel expansion layer are located in the first trapezoidal region, and the second JFET region and the corresponding current channel expansion layer are located in the second trapezoidal region; Among the first trapezoidal area and the second trapezoidal area, one is a regular trapezoidal structure with a bottom width greater than a top width, and the other is an inverted trapezoidal structure with a bottom width less than a top width.

3. The MOSFET cell structure according to claim 2, characterized in that: The included angle of the top of the inverted trapezoidal structure is [60°, 90°); the included angle of the top of the regular trapezoidal structure is (90°, 120].

4. The MOSFET cell structure according to claim 2, characterized in that: The current channel extension layer located on the surface of the first JFET region and on the sidewall of the first gate oxide layer together constitute a first inclined extension layer and a second inclined extension layer, the first inclined extension layer and the second inclined extension layer are symmetrically arranged, and the first inclined extension layer and the second inclined extension layer are respectively located on both sides of the first JFET region, and the first inclined extension layer, the middle area of ​​the first JFET region and the second inclined extension layer are all in contact with the first gate oxide layer; The current channel expansion layer located on the surface of the second JFET region and on the side wall of the second gate oxide layer together constitute a third inclined expansion layer and a fourth inclined expansion layer, the third inclined expansion layer and the fourth inclined expansion layer are symmetrically arranged, and the third inclined expansion layer and the fourth inclined expansion layer are respectively located on both sides of the second JFET region, and the third inclined expansion layer, the middle area of ​​the second JFET region and the fourth inclined expansion layer are all in contact with the second gate oxide layer.

5. The MOSFET cell structure according to claim 2, characterized in that: The current channel expansion layer located on the surface of the first JFET region and on the sidewall of the first gate oxide layer together constitute a first annular expansion layer, and the bottom of the first annular expansion layer contacts the first JFET region; The current channel expansion layer located on the surface of the second JFET region and on the sidewall of the second gate oxide layer together constitute a second annular expansion layer, and the bottom of the second annular expansion layer contacts the second JFET region.

6. The MOSFET cell structure according to claim 2, characterized in that: The current channel expansion layer located on the surface of the first JFET region and on the sidewall of the first gate oxide layer together constitute a first annular expansion layer, and the bottom of the first annular expansion layer contacts the first JFET region; wherein the first JFET region is located in the inverted trapezoidal structure region; The current channel expansion layer located on the surface of the second JFET region and on the side wall of the second gate oxide layer together constitute a first inclined expansion layer and a second inclined expansion layer, the first inclined expansion layer and the second inclined expansion layer are symmetrically arranged, and the first inclined expansion layer and the second inclined expansion layer are respectively located on both sides of the second JFET region, the first inclined expansion layer, the middle area of ​​the second JFET region and the second inclined expansion layer are all in contact with the second gate oxide layer; wherein, the second JFET region is located in the positive trapezoidal structure area.

7. The MOSFET cell structure according to claim 6, characterized in that: The ion concentration of the first JFET region is greater than the ion concentration of the current channel extension layer; and the ion concentration of the second JFET region is less than the ion concentration of the current channel extension layer.

8. The MOSFET cell structure according to claim 1, wherein: The N-type epitaxial layer includes an epitaxial sublayer and a current spreading layer, and the substrate, the epitaxial sublayer and the current spreading layer are connected layer by layer.

9. A method for manufacturing a MOSFET cell structure, characterized in that: For manufacturing the MOSFET cell structure according to any one of claims 1 to 8, the method comprises: Providing an N-type substrate; Fabricating a first epitaxial layer based on the surface of the substrate; Fabricating a second epitaxial layer based on the surface of the first epitaxial layer; A first JFET region, a second JFET region and a P-type shielding layer are manufactured based on the second epitaxial layer, the first JFET region and the second JFET region are spaced apart, and the first JFET region and the second JFET region are both N-type; the interface between the P-type shielding layer and the first JFET region and the second JFET region is set to an inclined structure; Fabricating a third epitaxial layer based on the surface of the second epitaxial layer, and fabricating a first doped layer based on the third epitaxial layer; A fourth epitaxial layer is fabricated based on the surface of the third epitaxial layer, and a second doped layer and a third doped layer are fabricated based on the fourth epitaxial layer; wherein the first epitaxial layer, the second epitaxial layer, the third epitaxial layer and the fourth epitaxial layer are all N-type doped; Fabricating a fourth doping region, and forming a first doping region, a second doping region, and a third doping region; performing terminal ion implantation; Etching the third epitaxial layer and the fourth epitaxial layer to form a first gate trench and a second gate trench, and performing ion implantation at the bottom of the first gate trench and the second gate trench to form a current channel expansion layer; High temperature furnace tube annealing; A first gate oxide layer and a first gate polysilicon layer are sequentially manufactured based on the first gate trench, and a second gate oxide layer and a second gate polysilicon layer are sequentially manufactured based on the second gate trench; wherein the first gate oxide layer wraps the first gate polysilicon layer, and the second gate oxide layer wraps the second gate polysilicon layer; a current channel expansion layer is located at the bottom corner of the first gate oxide layer and the second gate oxide layer, and part of the current channel expansion layer is located on the surface of the first JFET region and the second JFET region, and another part of the current channel expansion layer is located on the side wall of the first gate oxide layer, and the current channel expansion layer is N-type doped; The first doping region, the second doping region and the third doping region are arranged layer by layer in a direction away from the substrate to form an integral body, one side of the integral body is in contact with the first gate oxide layer or the second gate oxide layer, and the other side of the integral body is in contact with the fourth doping region, the thickness of the fourth doping region is greater than or equal to the sum of the thicknesses of the first doping region, the second doping region and the third doping region, the first doping region and the third doping region are N-type, and the second doping region and the fourth doping region are P-type; Manufacturing a first dielectric layer located on the surface of the first gate polysilicon layer, the first gate oxide layer, and a portion of the third doped region, and manufacturing a second dielectric layer located on the surface of the second gate polysilicon layer, the second gate oxide layer, and a portion of the third doped region; A first metal layer located on the surface and a second metal layer located on the back side of the substrate are manufactured.

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