Split-level unit and preparation method thereof

Abstract

The invention provides a staggered layer unit and a preparation method thereof, which can be applied to the technical field of semiconductors. The staggered layer unit comprises a first group of field effect transistors and a second group of field effect transistors which are respectively arranged on the upper surface of a substrate along a first horizontal direction; an intermediate dielectric layer surrounding the substrate, the first set of field effect transistors, and the second set of field effect transistors; the first staggered layer contact hole is connected with a gate stack of the power-on transistor in the first group of field effect transistors, extends to the lower surface of the substrate in the intermediate dielectric layer, penetrates through the substrate and is connected with a common layer of the second group of field effect transistors; the second staggered-layer contact hole is used for connecting the gate stack of the power-on transistor in the second group of field effect transistors and the common layer of the first group of field effect transistors, so that the first group of field effect transistors and the second group of field effect transistors are cross-coupled with each other.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a staggered unit and a manufacturing method thereof. Background Art

[0002] With the continuous development of integrated circuit manufacturing process nodes and key technologies, NS-GAA FET (Nano-SheetGate-All-Around Field-Effect Transistor) will replace the existing Fin FET (Fin Field-Effect Transistor) technology at 3nm and below nodes. Furthermore, three-dimensional stacked transistors will become the main technical route after the 1nm node. Among them, three-dimensional stacked transistors include three-dimensional stacked integrated transistors and VFET (Vertical Field-Effect Transistor, vertical channel field effect transistor). Among them, the three-dimensional stacked integrated transistor is 3DS FET, or CFET (Complementary FieldEffect Transistor, complementary field effect transistor).

[0003] The main process methods for realizing 3DS FET include two categories: one is sequential integration, and the other is self-aligned same-time (or single-time) integration. The former process method is simple, but it is limited by performance and resources; the latter process method has high integration and superior performance, but this method is complex and has many process technology challenges. Summary of the invention

[0004] In view of this, the present disclosure provides a staggered-layer unit and a method for preparing the same.

[0005] One aspect of the present disclosure provides a staggered unit, comprising: a first group of field effect transistors and a second group of field effect transistors respectively arranged along a first horizontal direction on an upper surface of a substrate; and an intermediate dielectric layer surrounding the substrate, the first group of field effect transistors and the second group of field effect transistors; wherein the first group of field effect transistors and the second group of field effect transistors respectively include a transmission transistor and a stacked pull-up transistor, and the stacked pull-up transistors include a pull-down transistor and a pull-up transistor stacked along a vertical direction; the transmission transistor, the pull-down transistor and the pull-up transistor respectively include: a channel layer; a source / drain layer connected to the channel layer on both sides of the channel layer in the first horizontal direction; A gate stack extending in a second horizontal direction intersecting the first horizontal direction and surrounding the channel layer; pull-down transistors, pull-up transistors and transfer transistors belonging to the same group are coupled via a common layer; a first staggered contact hole connected to the gate stack of the pull-up transistor in the first group of field effect transistors extends in the intermediate dielectric layer to the lower surface of the substrate and passes through the substrate to connect with the common layer of the second group of field effect transistors, thereby forming a staggered structure with the second staggered contact hole used to connect the gate stack of the pull-up transistor in the second group of field effect transistors and the common layer of the first group of field effect transistors, so that the first group of field effect transistors and the second group of field effect transistors are cross-coupled with each other.

[0006] According to an embodiment of the present disclosure, a first group of field effect transistors and a second group of field effect transistors are arranged along a second horizontal direction with a spacing space between them; a first staggered contact hole extends from a gate stack of a pull-up transistor in the first group of field effect transistors toward the spacing space to the lower surface of the substrate, and passes through the interior of the substrate to connect with a common layer in the second group of field effect transistors; and a second staggered contact hole extends from a gate stack of a pull-up transistor in the second group of field effect transistors toward the spacing space to connect with the common layer in the first group of field effect transistors above the substrate.

[0007] According to an embodiment of the present disclosure, the source layer contact hole connected to the upper surface of the source layer of the transfer transistor in the first group of field effect transistors extends downward in the spacing space to the surface of the intermediate dielectric layer to facilitate electrical connection between the transfer transistor in the first group of field effect transistors and the bit line terminal.

[0008] According to an embodiment of the present disclosure, a source layer contact hole connected to the lower surface of the source layer of the pull-up transistor in the second group of field effect transistors extends downward from the upper surface of the substrate through the substrate to the surface of the intermediate dielectric layer, thereby electrically connecting the pull-up transistor in the second group of field effect transistors to the power supply terminal; a source layer contact hole connected to the upper surface of the source layer of the pull-down transistor in the second group of field effect transistors extends downward within the spacing space to the surface of the intermediate dielectric layer, thereby electrically connecting the pull-down transistor in the second group of field effect transistors to the ground terminal.

[0009] Another aspect of the present disclosure provides a method for preparing a staggered unit, comprising: forming a first group of field effect transistors and a second group of field effect transistors spaced from each other and arranged in a first horizontal direction on an upper surface of a substrate; wherein the first group of field effect transistors and the second group of field effect transistors each include a transmission transistor and a stacked pull-up transistor, and the stacked pull-up transistor includes a pull-down transistor and a pull-up transistor stacked in a vertical direction; the transmission transistor, the pull-down transistor, and the pull-up transistor each include: a channel layer, a source / drain layer connected to the channel layer on both sides of the channel layer in the first horizontal direction, and a gate stack extending in a second horizontal direction intersecting the first horizontal direction and surrounding the channel layer; the pull-down transistor, the pull-up transistor, and the transmission transistor belonging to the same group The body transistors are coupled via a common layer; an intermediate dielectric layer is formed surrounding the first group of field effect transistors, the second group of field effect transistors and the substrate; a first staggered-layer contact hole and a second staggered-layer contact hole are formed in the intermediate dielectric layer to obtain a staggered-layer unit; wherein the second staggered-layer contact hole is connected to the gate stack of the pull-up transistor in the second group of field effect transistors, and is simultaneously connected to the common layer of the first group of field effect transistors; the first staggered-layer contact hole is connected to the gate stack of the pull-up transistor in the first group of field effect transistors, and simultaneously extends in the intermediate dielectric layer to the lower surface of the substrate and passes through the substrate to connect to the common layer of the second group of field effect transistors, thereby forming a staggered-layer structure with the second staggered-layer contact hole, so that the first group of field effect transistors and the second group of field effect transistors are cross-coupled with each other.

[0010] According to an embodiment of the present disclosure, an intermediate dielectric layer wraps around a first group of field effect transistors and a second group of field effect transistors; the above-mentioned preparation method also includes: etching the intermediate dielectric layer from above to form a first opening exposing a source layer of a pull-down transistor in the second group of field effect transistors and a second opening exposing a source layer of a transfer transistor in the first group of field effect transistors, wherein the spacing space between the first group of field effect transistors and the second group of field effect transistors partially overlaps with a projection surface of the first opening in a vertical direction, and the spacing space partially overlaps with a projection surface of the second opening in a vertical direction; filling the first opening and the second opening with a conductive material, and sealing the first opening and the second opening; etching from below The intermediate dielectric layer located in the spacing area between the first group of field effect transistors and the second group of field effect transistors is etched to form a third opening exposing the conductive material in the first opening and a fourth opening exposing the conductive material in the second opening; the conductive material is filled in the third opening and the fourth opening, thereby forming a source layer contact hole connected to the source layer of the pull-down transistor in the second group of field effect transistors in the intermediate dielectric layer, so that the pull-down transistor in the second group of field effect transistors is electrically connected to the ground terminal, and forming a source layer contact hole connected to the source layer of the transmission transistor in the first group of field effect transistors in the intermediate dielectric layer, so that the transmission transistor in the first group of field effect transistors is electrically connected to the bit line terminal.

[0011] According to an embodiment of the present disclosure, the pull-up transistor and the transfer transistor in the second group of field effect transistors are electrically connected through the first common layer, and the pull-down transistor and the transfer transistor in the second group of field effect transistors are electrically connected through the first common layer and the second common layer; a first staggered-layer contact hole and a second staggered-layer contact hole are formed in the intermediate dielectric layer to obtain a staggered-layer unit, including: etching the intermediate dielectric layer from above to form a fifth opening that simultaneously exposes the first common layer, the second common layer, and the gate stack of the pull-up transistor in the second group of field effect transistors; filling the fifth opening with a conductive material that contacts the first common layer, the second common layer, and the gate stack of the pull-up transistor in the second group of field effect transistors, and closing the fifth opening to form a second staggered-layer contact hole.

[0012] According to an embodiment of the present disclosure, the pull-up transistor and the transfer transistor in the first group of field effect transistors are electrically connected through the third common layer, and the pull-down transistor and the transfer transistor in the first group of field effect transistors are electrically connected through the third common layer and the fourth common layer; the above-mentioned preparation method also includes: etching the intermediate dielectric layer from above along the surface of the intermediate dielectric layer to form a sixth opening exposing the third common layer and the fourth common layer, wherein the spacing space between the first group of field effect transistors and the second group of field effect transistors partially overlaps with the projection surface of the sixth opening in the vertical direction; filling the sixth opening with conductive material and closing the sixth opening; forming a first staggered-layer contact hole and a second staggered-layer contact hole in the intermediate dielectric layer to obtain a staggered-layer unit, and also includes: etching the intermediate dielectric layer from below along the surface of the intermediate dielectric layer to form a seventh opening that simultaneously exposes at least one of the third common layer and the fourth common layer and the gate stack of the pull-up transistor in the second group of field effect transistors; filling the seventh opening with conductive material and closing the seventh opening to form a first staggered-layer contact hole.

[0013] According to an embodiment of the present disclosure, the above-mentioned preparation method also includes: etching the substrate and the intermediate dielectric layer from below according to the source layer position of the pull-up transistor in the second group of field effect transistors, forming a source layer contact hole that passes through the substrate and the intermediate dielectric layer and connects to the lower surface of the source layer of the pull-up transistor in the second group of field effect transistors, so as to facilitate the electrical connection of the pull-up transistor in the second group of field effect transistors with the power supply terminal.

[0014] According to an embodiment of the present disclosure, the first group of field effect transistors and the second group of field effect transistors each include a lower fin formed by etching a substrate; a portion of the substrate remaining after etching is connected between the lower fins of the first group of field effect transistors and the second group of field effect transistors; an intermediate dielectric layer surrounding the first group of field effect transistors, the second group of field effect transistors and the substrate is formed, including: etching a portion of the substrate from below until the lower surface of the lower fin of the first group of field effect transistors and the second group of field effect transistors is exposed; depositing a dielectric material on the lower surface of the lower fin of the first group of field effect transistors and the second group of field effect transistors to obtain an intermediate dielectric layer.

[0015] According to the embodiments of the present disclosure, the present disclosure sets the second staggered contact hole to be connected to the gate stack of the pull-up transistor in the second group of field effect transistors, and extends in the intermediate dielectric layer to be connected to the common layer of the first group of field effect transistors. Also, the first staggered contact hole is set to be connected to the gate stack of the pull-up transistor in the first group of field effect transistors, and extends in the intermediate dielectric layer to the lower surface of the substrate and passes through the substrate to be connected to the common layer of the second group of field effect transistors, thereby locally interconnecting the common layer of the second group of field effect transistors with the gate stack of the pull-up transistor in the first group of field effect transistors through the back gate contact. Thus, the first staggered contact hole and the second staggered contact hole opposite to the storage bit of the first staggered contact hole form a staggered structure with symmetrical upper and lower layers in physical space, which greatly reduces the area of ​​the integrated circuit implemented based on the staggered unit in the horizontal plane, and the preparation process is simple. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0017] Figure 1 The diagram schematically shows a development process of an integrated circuit according to an embodiment of the present disclosure.

[0018] Figure 2 A schematic diagram schematically shows an evolution path of an integrated circuit core transistor structure according to an embodiment of the present disclosure.

[0019] Figure 3 The schematic diagram of the sequential integration process according to the embodiment of the present disclosure is schematically shown.

[0020] Figure 4 The diagram schematically shows a self-aligned same-time integration process according to an embodiment of the present disclosure.

[0021] Figure 5A The structural diagram of the staggered-level unit according to an embodiment of the present disclosure is schematically shown.

[0022] Figure 5B The schematic diagram shows the structure of the field effect transistor in the staggered layer unit according to the embodiment of the present disclosure.

[0023] Figure 6 The schematic diagram of a SRAM integrated circuit according to an embodiment of the present disclosure is schematically shown.

[0024] Figure 7 A schematic diagram of a single-layer SRAM structure according to an embodiment of the present disclosure is schematically shown.

[0025] Fig. 8A The schematic diagram of the layer structure of the three-dimensional stacked SRAM structure according to the embodiment of the present disclosure is schematically shown.

[0026] Figure 8B The diagram schematically shows a top structure in a three-dimensional stacked SRAM structure according to an embodiment of the present disclosure.

[0027] Figure 8C The schematic diagram schematically shows a bottom layer structure in a three-dimensional stacked SRAM structure according to an embodiment of the present disclosure.

[0028] Fig.8D The figure schematically shows a backside contact in a three-dimensional stacked SRAM structure according to an embodiment of the present disclosure.

[0029] Fig.9A The schematic diagram of the layer structure of the staggered layer unit according to the embodiment of the present disclosure is schematically shown.

[0030] Fig. 9B A schematic diagram of a top layer structure in a staggered unit according to an embodiment of the present disclosure is schematically shown.

[0031] Fig. 9C A schematic diagram of the underlying structure in a staggered unit according to an embodiment of the present disclosure is schematically shown.

[0032] Fig.9D A schematic diagram of back-side contact in a staggered unit according to an embodiment of the present disclosure is schematically shown.

[0033] Fig. 10A A schematic diagram of the axial direction of the staggered-level unit extending along the first horizontal direction according to an embodiment of the present disclosure is schematically shown.

[0034] Fig. 10B A schematic diagram of the axial direction of the staggered-level unit extending along the second horizontal direction according to an embodiment of the present disclosure is schematically shown.

[0035] Figure 11A to Figure 11E Schematically shows Fig. 8A Schematic diagram of the various axes of the SRAM structure.

[0036] Figure 12A to Figure 12E Schematically shows Fig.9A Schematic diagram of the various axial directions of the staggered unit layer structure.

[0037] Fig.13 A flow chart of a method for preparing a staggered-layer unit according to an embodiment of the present disclosure is schematically shown.

[0038] Figure 14A to Figure 53A , Figure 14B to Figure 53B , Fig.45C , Fig.45D , Fig.51C , Fig.51D , Fig.53C and Fig.53D A schematic cross-sectional view of a staggered-layer unit along the axial direction according to an embodiment of the present disclosure is schematically shown.

[0039] Fig.54 A cross-sectional schematic diagram of a three-dimensional stacked structure according to an embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0040] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0041] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0042] All terms used herein, including technical and scientific terms, have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification, and should not be interpreted in an idealized or overly rigid manner.

[0043] When using expressions such as "at least one of A, B, and C, etc.", it should generally be interpreted as the meaning of the expression generally understood by those skilled in the art. For example, "a system having at least one of A, B, and C" should include but not be limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc. When using expressions such as "at least one of A, B, or C, etc.", it should generally be interpreted as the meaning of the expression generally understood by those skilled in the art. For example, "a system having at least one of A, B, or C" should include but not be limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.

[0044] It should also be noted that the directional terms mentioned in the embodiments, such as "upper", "lower", "front", "back", "left", "right", etc., are only reference directions of the drawings and are not intended to limit the scope of protection of the present disclosure. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or configurations will be omitted when they may cause confusion in the understanding of the present disclosure.

[0045] In the embodiment of the present disclosure, Figure 1 The technology development route shown is used as an example to demonstrate the development process of integrated circuits. Figure 1 In this paper, Tech Node refers to the semiconductor process node, which can be used to indicate the critical dimension that can be achieved by the process of integrated circuits. Figure 1 From the technology development route shown, it can be seen that the preparation processes of integrated circuits are sorted in descending order according to the size represented by the semiconductor process node, namely Planar 11A (i.e., planar transistor structure), Fin FET 11B, NS-GAA FET 11C, VFET 11D and StackedFET 11E. Among them, the sizes represented by the Tech Node 12A of Planar 11A are 90, 65, 45, 32, 28 and 20 from high to low, in nm; the sizes represented by the Tech Node 12B of Fin FET 11B are 14, 10, 7, 5 and 4 from high to low, in nm; the sizes represented by the Tech Node 12C of NS-GAA FET 11C are 3 and 2 from high to low, in nm; the sizes represented by the Tech Node 12D of VFET 11D and Stacked FET 11E are 1 and 0.7 from high to low, in nm.

[0046] Furthermore, if Figure 2 As shown, in the evolution path of the core transistor structure of the integrated circuit, it will develop from Fin FET 201 to NS-GAA FET 202, Forksheet 203, and further to the three-dimensional stacked integrated transistor in a single chip, namely 3DS FET or CFET (Complementary Field Effect Transistor) 204, to obtain higher integration density and overall performance.

[0047] like Figure 3 and Figure 4As shown, the main process methods for realizing 3DS FET include two categories: one is sequential integration process (Sequential 3D), and the other is self-aligned monolithic integration process (Monolithic 3D). Taking two transistors stacked up and down as an example, when the two transistors are made by sequential integration process, the channel materials of the two transistors can be different from each other; when the two transistors are made by self-aligned monolithic integration process, the channel materials of the two transistors can be the same. For example, the operation of the sequential integration process may include: bonding the substrate 301 to the upper part of the bottom device 302 to obtain the middle device 303; based on the bonded substrate in the middle device, manufacturing the top device, thereby obtaining the integrated circuit 304. The self-aligned monolithic process may include growing a polysilicon layer 402 surrounding multiple channel layers directly on the fin structure 401, and then processing it to obtain the integrated circuit 403.

[0048] Based on this, the sequential integration process method is simple, but will be limited by performance and resources; the latter self-aligned same-order integration process method has high integration and superior performance, but this method is complex and has many process technology challenges.

[0049] Specifically, the advantages of sequential integration include: flexible architecture design, channel materials can be adjusted as needed, flexible connection settings between transistors, etc. The disadvantages of sequential integration are mainly reflected in: high resource consumption, limitations of the preparation process, bonding, isolation space between NPs, thermal budget and lithography alignment.

[0050] The advantages of the self-aligned same-order integration process include: low resource consumption, precise process control, such as self-aligned top and bottom devices, and narrow isolation space between NPs, etc. The disadvantages are mainly reflected in: high process difficulty, such as processes with high aspect ratios and interconnections between devices, etc.

[0051] On this basis, the present disclosure provides a staggered-layer unit and a preparation method thereof, so as to obtain a highly integrated CFET device with a staggered-layer structure through a simple process, namely, the above-mentioned staggered-layer unit. Specifically, the staggered-layer unit includes: a first group of field effect transistors and a second group of field effect transistors, each arranged along a first horizontal direction on the upper surface of a substrate; and an intermediate dielectric layer surrounding the substrate, the first group of field effect transistors and the second group of field effect transistors; wherein the first group of field effect transistors and the second group of field effect transistors each include a transmission transistor and a stacked pull-up transistor, and the stacked pull-up transistors include a pull-down transistor and a pull-up transistor stacked along a vertical direction; the transmission transistor, the pull-down transistor and the pull-up transistor each include: a channel layer; a source / drain layer connected to the channel layer on both sides of the channel layer in the first horizontal direction; and a source / drain layer connected to the channel layer on both sides of the channel layer in the first horizontal direction. A gate stack extending in a second horizontal direction intersecting with the first and second directions and surrounding the channel layer; the pull-down transistors, pull-up transistors and transfer transistors belonging to the same group are coupled via a common layer; a first staggered contact hole connected to the gate stack of the pull-up transistor in the first group of field effect transistors extends in the intermediate dielectric layer to the lower surface of the substrate and passes through the substrate to connect with the common layer of the second group of field effect transistors, thereby forming a staggered structure with the second staggered contact hole used to connect the gate stack of the pull-up transistor in the second group of field effect transistors and the common layer of the first group of field effect transistors, so that the first group of field effect transistors and the second group of field effect transistors are cross-coupled with each other.

[0052] Figure 5A A schematic diagram of a staggered-level unit according to an embodiment of the present disclosure is schematically shown. Figure 5B The schematic diagram of the field effect transistor in the staggered unit according to the embodiment of the present disclosure is shown schematically. Figure 5A and Figure 5B In the embodiment of the present disclosure, the extension direction of the X-axis is defined as the first horizontal direction, the extension direction of the Y-axis is defined as the second horizontal direction intersecting the first horizontal direction, and the extension direction of the Z-axis is defined as the vertical direction. In one embodiment of the present disclosure, the first horizontal direction and the second horizontal direction may be perpendicular to each other in the same horizontal plane. The vertical direction may be a direction perpendicular to the horizontal plane.

[0053] like Figure 5A As shown, the staggered unit 500 of this embodiment includes: a first group of field effect transistors and a second group of field effect transistors arranged along a first horizontal direction on the upper surface of a substrate SUB, and an intermediate dielectric layer surrounding the substrate SUB, the first group of field effect transistors and the second group of field effect transistors. The appearance of each field effect transistor in the embodiment of the present disclosure is as follows Figure 5B Shown. Figure 5B The field effect transistor shown includes a gate structure G surrounding a channel layer such as a nanosheet or a nanowire (the channel layer is surrounded by the gate structure G and Figure 5A(not shown in the perspective view), and a source / drain layer L located on both sides of the gate structure G and connected to the channel layer.

[0054] exist Figure 5A Each field effect transistor shown in the figure can be used as a transmission transistor or a pull-up transistor, etc. according to actual needs. Among them, the transmission transistor can be a transistor for transmitting write data from the bit line. The pull-up transistor can include a pull-up transistor and a pull-down transistor. The pull-up transistor can be a transistor for pulling up the node level. The pull-down transistor can be a transistor for pulling down the node level. And, in Figure 5A In order to avoid blocking the structure of the staggered unit 500, Figure 5A It should be understood that the intermediate dielectric layer in the embodiment of the present disclosure can be disposed between the structures of the staggered unit 500 as required to ensure electrical isolation of each field effect transistor in the staggered unit 500.

[0055] Continue to refer Figure 5A ,exist Figure 5A Two substrates SUB arranged along the second horizontal direction are shown. On the two substrates SUB, a plurality of field effect transistors integrated into an integrated structure are respectively arranged. Based on this, for the convenience of description, in this disclosure, Figure 5A The plurality of field effect transistors on the lower left substrate SUB are defined as the first group of field effect transistors, and are defined as Figure 5A In the space shown, it is located in front; and Figure 5A The transistor on the upper right substrate is defined as the second group of field effect transistors mentioned above, and its Figure 5A Located at the rear in the space shown. The first group of field effect transistors and the second group of field effect transistors each include a stacked field effect transistor. For example, the first group of field effect transistors and the second group of field effect transistors each include a transfer transistor and a stacked pull-up transistor, and the stacked pull-up transistor includes a pull-down transistor and a pull-up transistor stacked in a vertical direction. The transfer transistor, the pull-down transistor, and the pull-up transistor each include: a channel layer. A source / drain layer connected to the channel layer on both sides of the channel layer in a first horizontal direction. A gate stack extending in a second horizontal direction intersecting the first horizontal direction and surrounding the channel layer. It should be noted that in the embodiment of the present disclosure, the transfer transistor may also be stacked with another transistor, and the actual function of the other transistor can be determined based on demand, which is not elaborated in the present disclosure.

[0056] The following will Figure 5AThe field effect transistor shown in the figure is defined as a pull transistor or a transmission transistor, so as to facilitate understanding of the structure of the staggered unit 500 of the embodiment of the present disclosure. It should be understood that the following is only an example, and those skilled in the art can set the function of the field effect transistor in the staggered unit 500 as required.

[0057] Exemplarily, the transistor located at the upper left of the first group of field effect transistors is defined as a transmission transistor AC1; the transistor located at the upper right of the first group of field effect transistors is defined as a pull-down transistor PD1; and the transistor located at the lower right of the first group of field effect transistors is defined as a pull-up transistor PU1. Figure 5A It can be seen that the transmission transistor AC1 and the pull-down transistor PD1 are coupled through a common layer. Moreover, the common layer of the upper layer and the common layer of the lower layer in the first group of field effect transistors are coupled through a connection structure. Based on this, the electrical connection among the transmission transistor AC1, the pull-up transistor PU1 and the pull-down transistor PD1 can be realized. Moreover, the common layer used for electrical connection among the transmission transistor AC1, the pull-up transistor PU1 and the pull-down transistor PD1 corresponds to the first source / drain layer of the transmission transistor AC1, the pull-up transistor PU1 and the pull-down transistor PD1 respectively. Among them, the transmission transistor AC1 can be electrically connected to the bit line end through the source layer contact hole connected to the second source / drain layer located on the other side of the gate structure of the transmission transistor AC1, and the transmission transistor AC1 can be electrically connected to the word line end through the gate contact hole connected to its gate structure G. The pull-up transistor PU1 can be electrically connected to the power supply terminal through a source layer contact hole connected to the second source / drain layer on the other side of the gate structure of the pull-up transistor PU1; the pull-down transistor PD1 can be electrically connected to the ground terminal through a source layer contact hole connected to the second source / drain layer on the other side of the gate structure of the pull-down transistor PD1. Based on this, the stacked pull-up transistors in the first group of field effect transistors can be configured as an inverter, the pull-up transistor PU1 can realize the level of the pull-up common layer, and the pull-down transistor PD1 can realize the level of the pull-down common layer.

[0058] Correspondingly, the transistor located at the upper right of the second group of field effect transistors is defined as the transmission transistor AC2; the transistor located at the lower left of the second group of field effect transistors is defined as the pull-down transistor PD2; and the transistor located at the upper left of the second group of field effect transistors is defined as the pull-up transistor PU2. Figure 5AIt can be seen that the transmission transistor AC2 and the pull-down transistor PU2 are coupled through a common layer. Moreover, the common layer of the upper layer and the common layer of the lower layer in the second group of field effect transistors are coupled through a connection structure. Based on this, the electrical connection among the transmission transistor AC2, the pull-up transistor PU2 and the pull-down transistor PD2 can be realized. Moreover, the common layer used for electrical connection among the transmission transistor AC2, the pull-up transistor PU2 and the pull-down transistor PD2 corresponds to the first source / drain layer of the transmission transistor AC2, the pull-up transistor PU2 and the pull-down transistor PD2 respectively. Among them, the transmission transistor AC2 can be electrically connected to the bit line end through a source layer contact hole connected to the second source layer located on the other side of the gate structure of the transmission transistor AC2, and the transmission transistor AC2 can be electrically connected to the word line end through a gate contact hole connected to its gate structure G. The pull-up transistor PU2 can be electrically connected to the power supply terminal through a source layer contact hole connected to the second source / drain layer on the other side of the gate structure of the pull-up transistor PU2; the pull-down transistor PD2 can be electrically connected to the ground terminal through a source layer contact hole connected to the second source / drain layer on the other side of the gate structure of the pull-down transistor PD2. Based on this, the stacked pull-up transistors in the second group of field effect transistors can be configured as an inverter, the pull-up transistor PU2 can realize the level of the pull-up common layer, and the pull-down transistor PD2 can realize the level of the pull-down common layer.

[0059] On this basis, by cross-coupling the first group of field effect transistors and the second group of field effect transistors, an SRAM structure (Static Random-Access Memory) can be formed. Figure 6 As shown in Figure 1, SRAM is the core unit circuit of integrated circuits, and the continuous reduction of SRAM unit area is the main line of development of integrated circuits. The use of a three-dimensional stacked structure of transistors (3DS-FET or CFET) can greatly reduce the SRAM unit area, reducing the SRAM unit area by more than 30%. Figure 7 and Fig. 8A ,contrast Figure 7 Single-layer SRAM structure and Fig. 8A From the double-layer SRAM structure, we can see that Fig. 8A The area of ​​the realized three-dimensional stacked structure is smaller than Figure 7 The area of ​​the two-dimensional structure in . Further, Fig. 8A The three-dimensional stacked structure in can be divided into a top structure and a bottom structure, where the top structure can be implemented based on NMOS and the bottom structure can be implemented based on PMOS. The top structure and the bottom structure can be connected based on the backside contact (BSCON) and the back gate contact (BGC). On this basis, Figure 8B and Figure 8CThey are shown respectively Fig. 8A The top and bottom structures of the three-dimensional stacked structure. Fig.8D The fill pattern is schematically shown in Fig. 8A Backside contact of three-dimensional stacked structures.

[0060] In a cross-coupling mode of an embodiment of the present disclosure, a first staggered contact hole QB connected to the gate stack of the pull-up transistor in the first group of field effect transistors extends to the lower surface of the substrate SUB in the intermediate dielectric layer and passes through the substrate SUB to connect to the common layer of the second group of field effect transistors, thereby forming a staggered structure with a second staggered contact hole Q used to connect the gate stack of the pull-up transistor in the second group of field effect transistors and the common layer of the first group of field effect transistors, so that the first group of field effect transistors and the second group of field effect transistors are cross-coupled with each other. Wherein, in the case of implementing SRAM based on the staggered unit of the present disclosure, the first staggered contact hole QB can be electrically connected to the first signal output terminal, and the second staggered contact hole Q can be electrically connected to the second signal output terminal.

[0061] Specifically, continue to refer to Figure 5A It can be seen that the first group of field effect transistors and the second group of field effect transistors are arranged along the second horizontal direction and there is a spacing space between them. The first staggered contact hole QB extends from the gate stack of the pull-up transistor in the first group of field effect transistors to the spacing space to the lower surface of the substrate SUB, and passes through the inside of the substrate to connect with the common layer in the second group of field effect transistors. The second staggered contact hole Q extends from the gate stack of the pull-up transistor in the second group of field effect transistors to the spacing space to connect with the common layer in the first group of field effect transistors above the substrate. The spacing space is filled with a dielectric material used as an intermediate dielectric layer.

[0062] exist Figure 5A For convenience, the electrical connection configuration of the first staggered contact hole QB and the second staggered contact hole Q is schematically shown, and the physical connection mode thereof is only schematic. The physical morphology of the first staggered contact hole QB and the second staggered contact hole Q and the physical connection between other components can be known by those skilled in the art according to the following description.

[0063] Based on the above cross-coupling method, the area of ​​the SRAM unit can be further reduced on the basis of the three-dimensional stacking structure. Fig.9A A circuit topology diagram of the three-dimensional stacking structure of the above-mentioned staggered units is shown. Fig. 9B and Fig. 9C They are shown respectively Fig.9A The top and bottom structures of the three-dimensional stacked structure. Fig.9D The fill pattern is schematically shown in Fig.9A Backside contact of three-dimensional stacked structures.

[0064] Based on this, the present disclosure sets the second staggered contact hole Q to be connected to the gate stack of the pull-up transistor in the second group of field effect transistors, and extends in the intermediate dielectric layer to be connected to the common layer of the first group of field effect transistors. Also, the first staggered contact hole QB is set to be connected to the gate stack of the pull-up transistor in the first group of field effect transistors, and extends in the intermediate dielectric layer to the lower surface of the substrate SUB and passes through the substrate SUB to be connected to the common layer of the second group of field effect transistors, thereby locally interconnecting the common layer of the second group of field effect transistors with the gate stack of the pull-up transistor in the first group of field effect transistors through the back gate contact. Thus, the first staggered contact hole QB and the second staggered contact hole Q opposite to the storage bit of the first staggered contact hole QB form a staggered structure with upper and lower symmetrical layers in physical space, which greatly reduces the area of ​​the integrated circuit implemented based on the staggered unit in the horizontal plane, and the preparation process is simple. For example, compared Fig. 8A and Fig.9A It can be seen that since the first staggered contact hole QB and the second staggered contact hole Q form a staggered structure, the first staggered contact hole QB and the second staggered contact hole Q have a certain overlap in the Z-axis direction, and therefore, the size is reduced in the horizontal direction, that is, Fig. 8A The 156nm in the Fig.9A This storage bit hierarchical manufacturing structure can significantly reduce the area of ​​SRAM cells based on CFET, etc. It should be noted that the dimensions marked in the drawings of the present disclosure are examples and are not used to limit the actual dimensions of the staggered cells in the present disclosure.

[0065] In the embodiments of the present disclosure, the above-mentioned source layer contact holes can extend in the intermediate dielectric layer and be exposed to the same surface of the intermediate dielectric layer. For example, the source layer contact hole connected to the upper surface of the source layer of the transfer transistor AC1 in the first group of field effect transistors extends downward in the spacing space to the surface of the intermediate dielectric layer, so as to facilitate the electrical connection between the transfer transistor AC1 in the first group of field effect transistors and the bit line terminal. The source layer contact hole connected to the lower surface of the source layer of the transfer transistor AC2 in the second group of field effect transistors passes through the substrate SUB and extends in the spacing space to the surface of the intermediate dielectric layer, so as to facilitate the electrical connection between the transfer transistor AC2 in the second group of field effect transistors and the bit line terminal.

[0066] For another example, the source layer contact hole connected to the lower surface of the source layer of the pull-down transistor PD1 in the first group of field effect transistors extends downward from the upper surface of the substrate SUB through the substrate SUB to the surface of the intermediate dielectric layer, so that the pull-down transistor PD1 in the first group of field effect transistors is electrically connected to the ground terminal. The source layer contact hole connected to the upper surface of the source layer of the pull-up transistor PU1 in the first group of field effect transistors extends downward in the spacing space to the surface of the intermediate dielectric layer, so that the pull-up transistor PU1 in the first group of field effect transistors is electrically connected to the power supply terminal.

[0067] For another example, the source layer contact hole connected to the lower surface of the source layer of the pull-up transistor PU2 in the second group of field effect transistors extends downward from the upper surface of the substrate SUB through the substrate SUB to the surface of the intermediate dielectric layer, so that the pull-up transistor PU2 in the second group of field effect transistors is electrically connected to the power supply terminal. The source layer contact hole connected to the upper surface of the source layer of the pull-down transistor PD2 in the second group of field effect transistors extends downward in the spacing space to the surface of the intermediate dielectric layer, so that the pull-down transistor PD2 in the second group of field effect transistors is electrically connected to the ground terminal.

[0068] In order to better understand the structure of the staggered unit in the present disclosure, the content of the present disclosure is described below in combination with the preparation method of the staggered unit. Fig. 10A and Fig. 10B The various axial directions of the staggered-layer unit defined in the embodiment of the present disclosure are shown.

[0069] Figures 11A to 11E An example is shown Fig. 8A Each axis of the three-dimensional stacked structure. Figures 12A to 12E An example is shown Fig.9A The axial directions of the three-dimensional structure of the staggered unit disclosed in the present invention are as follows. The XX' axial direction is consistent with the extension direction of the X axis in Figure 10. The Y1-Y1' axial direction, the Y2-Y2' axial direction, the Y3-Y3' axial direction, and the Y4-Y4' axial direction are consistent with the extension direction of the Y axis in Figure 10.

[0070] Fig.13 A flow chart of a method for preparing a staggered-layer unit according to an embodiment of the present disclosure is schematically shown.

[0071] like Fig.13 As shown, the method for preparing the staggered unit of this embodiment includes: operations S1301 to S1303.

[0072] In operation S1301, a first group of field effect transistors and a second group of field effect transistors are formed on the upper surface of the substrate, which are spaced from each other and arranged along a first horizontal direction; wherein the first group of field effect transistors and the second group of field effect transistors each include a transfer transistor and a stacked pull-up transistor, and the stacked pull-up transistor includes a pull-down transistor and a pull-up transistor stacked along a vertical direction; the transfer transistor, the pull-down transistor and the pull-up transistor each include: a channel layer, a source / drain layer connected to the channel layer on both sides of the channel layer in the first horizontal direction, and a gate stack extending in a second horizontal direction intersecting the first horizontal direction and surrounding the channel layer; the pull-down transistor, the pull-up transistor and the transfer transistor belonging to the same group are coupled via a common layer.

[0073] In operation S1302, an intervening dielectric layer surrounding the first group of field effect transistors, the second group of field effect transistors, and the substrate is formed.

[0074] In operation S1303, a first staggered contact hole and a second staggered contact hole are formed in the intermediate dielectric layer to obtain a staggered unit; wherein the second staggered contact hole is connected to the gate stack of the pull-up transistor in the second group of field effect transistors, and is simultaneously connected to the common layer of the first group of field effect transistors; the first staggered contact hole is connected to the gate stack of the pull-up transistor in the first group of field effect transistors, and simultaneously extends in the intermediate dielectric layer to the lower surface of the substrate and passes through the substrate to connect to the common layer of the second group of field effect transistors, thereby forming a staggered structure with the second staggered contact hole, so that the first group of field effect transistors and the second group of field effect transistors are cross-coupled with each other.

[0075] In order to better understand the preparation method of the staggered layer unit disclosed in the present invention, the following is a cross-sectional view of each axial direction during the preparation of the staggered layer unit, namely Figure 14A to Figure 53A , Figure 14B to Figure 53B , Fig.45C , Fig.45D , Fig.51C , Fig.51D , Fig.53C and Fig.53D , to explain the contents of the embodiments of the present disclosure. It should be noted that in the following description Figure 14A to Figure 53A , Figure 14B to Figure 53B , Fig.45C , Fig.45D , Fig.51C , Fig.51D , Fig.53C and Fig.53D In the case where the numbers in the captions of multiple figures are the same, the preparation processes corresponding to the multiple figures are the same. In the case where the numbers in the captions of multiple figures are the same but the letters are different, the preparation processes corresponding to the multiple figures are the same, and the axes corresponding to the multiple figures are different. For example, Fig.14A and Fig. 14BThese are two axial cross-sectional views of the same preparation process.

[0076] Take a stacked set of field effect transistors as an example. Figure 14A to Figure 15A It is a cross-sectional view along the XX' axis during the preparation of the staggered unit. Figure 14B~Figure 15B This is a cross-sectional view along the Y4-Y4' axis during the preparation of the staggered unit. Figure 14A to Figure 15A ,as well as Figure 14B~Figure 15B , the material of the substrate SUB may include silicon, etc. The substrate SUB may be subjected to pretreatment operations such as well lithography, ion implantation, annealing and cleaning in sequence. Then, a lower stacked structure, an intermediate layer 103 and an upper stacked structure are sequentially arranged on the pretreated substrate SUB using an epitaxial growth process. The lower stacked structure and the upper stacked structure each include an alternating channel layer 101 and a sacrificial layer 102. Among them, the material of the sacrificial layer 102 and the intermediate layer 103 may be consistent, such as SiGe or Si, etc. The material of the channel layer 101 may be doped silicon, etc. The channel layer 101 located above the intermediate layer 103 and the channel layer 101 located below the intermediate layer 103 may have the same doping elements or different doping elements.

[0077] In the first embodiment of the present disclosure, the material of the channel layer 101 located above the middle layer 103 may be p-type doped silicon; the material of the channel layer 101 located below the middle layer 103 may be n-type doped silicon. In the second embodiment of the present disclosure, the material of the channel layer 101 located above the middle layer 103 may be n-type doped silicon; the material of the channel layer 101 located below the middle layer 103 may be p-type doped silicon. In the third embodiment of the present disclosure, the material of the channel layer 101 located above the middle layer 103 and the material of the channel layer 101 located below the middle layer 103 may both be n-type doped silicon or both be p-type doped silicon.

[0078] Figure 16A to Figure 18A It is a cross-sectional view along the XX' axis during the preparation of the staggered unit. Figure 16B to Figure 18B This is a cross-sectional view along the Y4-Y4' axis during the preparation of the staggered unit. Figure 16A to Figure 18A ,as well as Figure 16B to Figure 18B. The sidewall 104 can be formed by a sidewall transfer (SIT) process. The material of the sidewall 104 can be silicon nitride or the like. In the embodiment of the present disclosure, a core mold 105 can be formed on the upper stacked structure, and the core mold 105 can be patterned by a photolithography process to obtain a linear pattern extending along the X direction. Among them, the material of the core mold 105 can be polycrystalline silicon or amorphous silicon or the like. The sidewall 104 is formed in the above-mentioned area, and the patterned core mold 105 is removed after the sidewall 104 is formed, so that only the sidewall 104 remains on the stacked structure, thereby completing the preparation of the sidewall 104. On this basis, the upper stacked structure, the middle layer 103, the lower stacked structure and the substrate SUB can be etched according to the pattern of the sidewall 104 using an anisotropic etching process to form a fin located on the substrate SUB and a substrate etching area distributed on both sides of the fin along the first horizontal direction. In the substrate etching area, a dielectric material 106 is deposited, and the dielectric material 106 is etched back to a height lower than the upper surface of the lower fin formed by the substrate or equal to the upper surface of the lower fin, so that the dielectric material 106 is used as a shallow trench isolation member. The dielectric material in the embodiment of the present disclosure may include silicon dioxide or silicon nitride.

[0079] Figure 19A to Figure 23A It is a cross-sectional view along the XX' axis during the preparation of the staggered unit. Figure 19B to Figure 23B This is a cross-sectional view along the Y4-Y4' axis during the preparation of the staggered unit. Figure 19A to Figure 23A ,as well as Figure 19B to Figure 23B, a sacrificial gate across the fin can be formed on the dielectric material 106 by processes such as thermal oxidation, chemical vapor deposition or sputtering. The sacrificial gate includes a gate oxide layer 107, a silicon layer 108 and a mask layer 109 from bottom to top, wherein the material of the gate oxide layer 107 can be SiO2 or the like. The material of the silicon layer 108 is amorphous silicon or polycrystalline silicon. The material of the hard mask layer 109 can be oxide, carbide or organic matter or the like. On this basis, a sidewall 110 can be formed on the sidewall of the sacrificial gate by a sidewall formation process. The material of the sidewall can be SiCNO or the like. The upper stacked structure, the middle layer and the lower stacked structure can be etched according to the pattern of the sacrificial gate and the sidewall 110, thereby exposing the sidewalls of the upper stacked structure, the middle layer and the lower stacked structure. The middle layer 103 and the sacrificial layer 102 can be set to have different etching selectivities, so that the middle layer 103 can be etched at a faster rate than the sacrificial layer 102. After the middle layer 103 is etched, an opening 112 is formed. The end of the sacrificial layer 102 in the first horizontal direction is recessed relative to the channel layer 101 to form an opening 111. Based on this, the dielectric material can be filled in the space released in the fin due to the selective etching of the sacrificial layer 102 and the middle layer 103. The portion of the dielectric material filled at the end of the sacrificial layer 102 is used as the inner sidewall 113, and the portion of the dielectric material filled between the lower stacked structure and the upper stacked structure is used as the device isolation layer 114. As a result, the inner sidewall 113 and the device isolation layer 114 are manufactured at the same time, the steps of the manufacturing process are reduced, and the adverse result of the misalignment of the sides of the upper field effect transistor and the lower field effect transistor in the stacked field effect transistor caused by the separate preparation of the inner sidewall 113 and the device isolation layer 114 is avoided.

[0080] Figure 24A to Figure 31A It is a cross-sectional view along the XX' axis during the preparation of the staggered unit. Figure 24B to Figure 31B This is a cross-sectional view along the Y4-Y4' axis during the preparation of the staggered unit. Figure 24A to Figure 31A ,as well as Figure 24B to Figure 31B, a lower source / drain position defining layer 115 in contact with the channel layer 101 is formed on both sides of the channel layer 101 located under the inter-device isolation layer 114, and a sidewall 116 is formed on the lower source / drain position defining layer 115 by a sidewall forming process. Among them, the material of the lower source / drain position defining layer 115 may include but is not limited to aC (amorphous carbon). The method for forming the lower source / drain position defining layer 115 includes but is not limited to spin coating. For example, after depositing aC, the deposited aC can be planarized and the aC can be etched back to a middle position not higher than the inter-device isolation layer 114. The material of the sidewall 116 includes but is not limited to SiNx and the like. Among them, the sidewall 116 is used to protect the channel layer 101 located on the upper part of the inter-device isolation layer to prevent the source / drain from growing at both ends of the channel layer 101 of the upper device during the source / drain growth process of the lower device. In the case of different types of upper and lower devices, the source / drain materials of the upper and lower devices can be different.

[0081] After forming the sidewall 116, the lower source / drain position defining layer 115 is removed to expose the sidewall of the channel layer 101 located below the device isolation layer 114, and on the exposed sidewall of the channel layer 101, the source / drain material is epitaxially grown and in-situ doped, thereby forming a source / drain layer 117 connected to the lower stacked structure. Among them, the source / drain material can be SiGe or Si. A dielectric material 118 can be deposited on the source / drain layer 117, and the dielectric material 118 can be etched to a position not higher than the device isolation layer 114 so as to electrically isolate the source / drain layers of the upper and lower devices. The sidewall 116 can be selectively etched to expose the sidewall of the channel layer 101 located above the device isolation layer 114. On the exposed sidewall of the channel layer 101, the source / drain material is epitaxially grown and in-situ doped, thereby forming a source / drain layer 119 connected to the upper stacked structure. On this basis, the source / drain layer 117 and the source / drain layer 119 are source / drain activated, thereby activating the source / drain layer 117 and the source / drain layer 119 .

[0082] Figure 32A to Figure 41A It is a cross-sectional view along the XX' axis during the preparation of the staggered unit. Figure 32B~Figure 41B This is a cross-sectional view along the Y4-Y4' axis during the preparation of the staggered unit. Figure 32A to Figure 41A ,as well as Figure 32B~Figure 41B , a dielectric material 120 is formed on the substrate SUB and the dielectric material 120 is planarized. The planarization can remove the mask layer 109 in the sacrificial gate and expose the silicon layer 108. Then, the silicon layer 108 and the sacrificial layer 102 are etched back by an etch-back process, so that a cavity 121_1 exposed by etching is formed at the original position of the silicon layer 108 on the inner side of the sidewall 110 and the inner sidewall 113, and a cavity 121_2 exposed by etching is formed at the original position of the sacrificial layer 102.

[0083] A gate stack surrounding the channel layer 101 is sequentially formed on the inner sidewalls of the cavities 121_1 and 121_2. The gate stack includes a gate dielectric layer 122 and a P-type work function layer 123. The material of the gate dielectric layer 122 may be a high-k dielectric material, where K represents a dielectric constant. High-k dielectric materials include HfO2, HfSiO x 、HfON、HfSiON、HfAlO x 、HfLaO x 、Al2O3、ZrO2、ZrSiO x , Ta2O5 or La2O3 or a combination of the above. The material of the P-type work function layer 123 may be titanium nitride or the like. A protective layer 124 is formed on the substrate SUB, and the protective layer 124 is etched until the top surface is located between the top surface and the bottom surface of the inter-device isolation layer 114 to shield the cavity for the lower device, so that the protective layer 124 protects the P-type work function layer 123 located in the cavity below the inter-device isolation layer 114, while exposing the P-type work function layer 123 located in the cavity above the inter-device isolation layer 114.

[0084] The P-type work function layer 123 located above the inter-device isolation layer 114 is etched by using a selective etching process, while the gate dielectric layer 122 located above the inter-device isolation layer 114 is retained. Then, an N-type work function layer 125 is formed around the gate dielectric layer 122 located above the inter-device isolation layer 114. Thus, different gate stacks surrounding the channel layer 101 are formed above and below the inter-device isolation layer 114, respectively. Thus, the channel layer 101, the gate stack, and the source / drain layer 119 located above the inter-device isolation layer constitute an N-type field effect transistor, and the channel layer 101, the gate stack, and the source / drain layer 117 located above the inter-device isolation layer constitute a P-type field effect transistor, thereby obtaining a stacked field effect transistor.

[0085] It should be understood that the above is only one embodiment of the present disclosure, and in the preparation process of other embodiments of the present disclosure, N-type field effect transistors or P-type field effect transistors can be formed as needed by changing the doping type of the source / drain layer and forming a corresponding type of work function layer. For example, the N-type field effect transistor of the upper layer can be formed as a P-type field effect transistor, and / or the P-type field effect transistor of the lower layer can be formed as an N-type field effect transistor.

[0086] After preparing the above-mentioned N-type field effect transistor and P-type field effect transistor, the protective layer 124 is removed to release the cavity below the inter-device isolation layer 114. Then, a conductive material is deposited in all the cavities 121_1 and all the cavities 121_2 to form a conductive layer 126, thereby completing the preparation of the gate structure. The conductive material in the embodiment of the present disclosure may include tungsten and the like. After forming the conductive layer 126, the conductive layer 126 may be planarized, and a dielectric material may be deposited on the planarized conductive layer 126. On this basis, a contact hole 127 connected to the source / drain layer 119 may be formed in the dielectric material 120.

[0087] Specifically, taking the four field effect transistors in the first group of field effect transistors and the four field effect transistors in the second group of field effect transistors as an example, Figure 42A to Figure 45A It is a cross-sectional view along the XX' axis during the preparation of the staggered unit. Figure 42B~Figure 45B It is a cross-sectional view along the Y3-Y3' axis during the preparation of the staggered unit. Fig.45C It is a cross-sectional view along the Y1-Y1' axis during the preparation of the staggered unit. Fig.45D It is a cross-sectional view along the Y2-Y2' axis during the preparation of the staggered unit.

[0088] On this basis, Figure 42A to Figure 4 5. Figure 42B~Figure 45B , Fig.45C and Fig.45D A schematic cross-sectional view of a structure in which the above-mentioned eight field effect transistors are integrated is shown. On the upper surface of the dielectric material 120, the dielectric material 120 is etched until the source / drain layer 119 is exposed, thereby forming openings 128_1, 128_2, and 128_3 located in the dielectric material 120. Among them, the opening 128_2 includes an opening 128_21 corresponding to the first group of field effect transistors and an opening 128_22 corresponding to the second group of field effect transistors. On this basis, according to the position of the source / drain layer 117 as a common layer, the opening 128_2 is further etched, so that the opening 128_2 exposes the source / drain layer 119 and the source / drain layer 117 at the same time. Conductive material is filled in the openings 128_1, 128_2, and 128_3, thereby forming contact holes 127_1, 127_2, and 127_3. The contact hole 127_2 includes a contact hole 127_21 formed by filling the opening 128_21 and a contact hole 127_22 formed by filling the opening 128_22. A dielectric material is deposited on the contact hole 127_1, the contact hole 127_2, and the contact hole 127_3. It should be noted that Fig.45DThere is a structure protruding from the upper surface of the conductive layer 126 above the conductive layer 126 on the right side of the middle. The structure is used as a connection line extending in a direction perpendicular to the paper surface (corresponding to the first horizontal direction). Fig.45D The conductive layer 126 on the left side of the center extends to the left side so as to lead out the pads for connecting the word line terminals from the back side.

[0089] Figure 46A to Figure 48A It is a cross-sectional view along the XX' axis during the preparation of the staggered unit. Figure 46B~Figure 48B This is a cross-sectional view along the Y4-Y4' axis during the preparation of the staggered unit. Figure 46A to Figure 48A ,as well as Figure 46B~Figure 48B It should be noted that Figure 46A to Figure 48A ,as well as Figure 46B~Figure 48B In the figure, the stacked field effect transistors are inverted for ease of description, and the same applies to the other figures below. It should be noted that the "above" and "below" in the following text are described according to the staggered unit before inversion. After the stacked field effect transistors are inverted, another substrate USUB can be bonded above the stack, and the material of the substrate USUB is the same as that of the above-mentioned substrate SUB. In the embodiment of the present disclosure, the first group of field effect transistors and the second group of field effect transistors each include a lower fin formed by etching the substrate SUB; the remaining part of the substrate after etching is connected between the lower fins of the first group of field effect transistors and the second group of field effect transistors. An intermediate dielectric layer surrounding the first group of field effect transistors, the second group of field effect transistors and the substrate is formed, including: etching a portion of the substrate from below until the lower surface of the lower fin of each of the first group of field effect transistors and the second group of field effect transistors is exposed. A dielectric material is deposited on the lower surface of the lower fin of each of the first group of field effect transistors and the second group of field effect transistors to obtain an intermediate dielectric layer. Thus, the lower fins of each of the first group of field effect transistors and the second group of field effect transistors can be electrically isolated from each other.

[0090] Continuing with the example of four field effect transistors in the first group of field effect transistors and four field effect transistors in the second group of field effect transistors, Figure 49A to Figure 51A It is a cross-sectional view along the XX' axis during the preparation of the staggered unit. Figure 49B~Figure 51B It is a cross-sectional view along the Y1-Y1' axis during the preparation of the staggered unit. Fig.51C It is a cross-sectional view along the Y2-Y2' axis during the preparation of the staggered unit. Fig.51D It is a cross-sectional view along the Y3-Y3' axis during the preparation of the staggered unit.

[0091] refer to Figure 49A to Figure 51A , Figure 49B~Figure 51B , Fig.51C and Fig.51DA dielectric material is deposited on the lower layer of the substrate SUB and the dielectric material and the substrate SUB are photolithographically processed together to form an opening 131 exposing the lower source layer, and openings 132_1 and 132_2 exposing the conductive material in contact with the upper source layer. Conductive material is deposited in the above-mentioned openings 131, 132_1, and 132_2, so as to form a contact hole located at the back of the device through the opening 131 exposing the lower source layer, and to form an interlayer contact through hole located at the back of the device through the opening 132_1 and 132_2 exposing the conductive material in contact with the upper source layer. Among them, the conductive material filled in the opening 131 can be used as a back contact hole (BSCON) to be electrically connected to the power supply terminal; the conductive material filled in the openings 132_1 and 132_2 can be used as a back interlayer contact through hole (BSVPR) to be electrically connected to the ground terminal and the bit line terminal respectively.

[0092] After depositing the conductive material, the conductive material exposed outside the dielectric material is planarized. According to an embodiment of the present disclosure, the above-mentioned preparation method also includes: according to the source layer position of the pull-up transistor in the second group of field effect transistors, etching the substrate SUB and the intermediate dielectric layer from below to form a source layer contact hole that passes through the substrate SUB and the intermediate dielectric layer and connects to the lower surface of the source layer of the pull-up transistor PU2 in the second group of field effect transistors, so as to facilitate the pull-up transistor PU2 in the second group of field effect transistors to be electrically connected to the power supply terminal. Based on a similar method, the pull-down transistor PD2 in the first group of field effect transistors can be electrically connected to the ground terminal, which will not be repeated here. Then, a multi-layer back-end interconnection and passivation protection process can be performed.

[0093] According to an embodiment of the present disclosure, the preparation method further includes: etching the intermediate dielectric layer from above to form a first opening exposing the source layer of the pull-down transistor in the second group of field effect transistors and a second opening exposing the source layer of the transmission transistor in the first group of field effect transistors, wherein the spacing space between the first group of field effect transistors and the second group of field effect transistors partially overlaps with the projection surface of the first opening in the vertical direction, and the spacing space partially overlaps with the projection surface of the second opening in the vertical direction. Filling the first opening and the second opening with conductive material, and closing the first opening and the second opening. Thus, a contact hole 127_11 formed based on the first opening and a contact hole 127_12 formed based on the first opening can be obtained.

[0094] The intermediate dielectric layer located in the spacing area between the first group of field effect transistors and the second group of field effect transistors is etched from below to form a third opening 132_1 exposing the conductive material in the first opening and a fourth opening 132_2 exposing the conductive material in the second opening. Conductive material is filled in the third opening 132_1 and the fourth opening 132_2, thereby forming a source layer contact hole connected to the source layer of the pull-down transistor PD2 in the second group of field effect transistors in the intermediate dielectric layer, so that the pull-down transistor PD2 in the second group of field effect transistors is electrically connected to the ground terminal, and forming a source layer contact hole connected to the source layer of the transmission transistor AC1 in the first group of field effect transistors in the intermediate dielectric layer, so that the transmission transistor AC1 in the first group of field effect transistors is electrically connected to the bit line terminal. Based on the same method, the source layer contact hole connected to the source layer of the pull-up transistor PU1 in the first group of field effect transistors in the embodiment of the present disclosure, etc., will not be repeated here.

[0095] Fig.52A It is a cross-sectional view along the XX' axis during the preparation of the staggered unit. Fig.52B It is a cross-sectional view along the Y4-Y4' axis during the preparation of the staggered unit.

[0096] Fig.53A It is a cross-sectional view along the XX' axis during the preparation of the staggered unit. Fig.53B It is a cross-sectional view along the Y1-Y1' axis during the preparation of the staggered unit. Fig.53C It is a cross-sectional view along the Y2-Y2' axis during the preparation of the staggered unit. Fig.53D It is a cross-sectional view along the Y3-Y3' axis during the preparation of the staggered unit. Fig.54 is a cross-sectional view along the Y3-Y3' axis of a three-dimensional stacked structure not involving the first staggered contact hole QB in some embodiments. Fig.53D and Fig.54 , it can be clearly seen that the structural difference between the staggered unit of the present disclosure including the first staggered contact hole QB and the three-dimensional stacking structure not involving the first staggered contact hole QB.

[0097] According to an embodiment of the present disclosure, the pull-up transistor PD2 in the second group of field effect transistors is electrically connected to the transmission transistor AC2 through the first common layer, and the pull-down transistor in the second group of field effect transistors is electrically connected to the transmission transistor through the first common layer and the second common layer. A first staggered contact hole QB and a second staggered contact hole Q are formed in the intermediate dielectric layer to obtain a staggered unit, including: etching the intermediate dielectric layer from above to form a fifth opening that simultaneously exposes the first common layer, the second common layer, and the gate stack of the pull-up transistor in the second group of field effect transistors. A conductive material that contacts the gate stack of the pull-up transistor in the first common layer, the second common layer, and the second group of field effect transistors is filled in the fifth opening, and the fifth opening is closed, thereby forming a second staggered contact hole Q.

[0098] According to an embodiment of the present disclosure, the pull-up transistors in the first group of field effect transistors are electrically connected to the transmission transistors through the third common layer, and the pull-down transistors in the first group of field effect transistors are electrically connected to the transmission transistors through the third common layer and the fourth common layer; the above-mentioned preparation method further includes: etching the intermediate dielectric layer from above along the surface of the intermediate dielectric layer to form a sixth opening exposing the third common layer and the fourth common layer, wherein the spacing space between the first group of field effect transistors and the second group of field effect transistors partially overlaps with the projection surface of the sixth opening in the vertical direction; filling the sixth opening with a conductive material, and closing the sixth opening;

[0099] A first staggered contact hole and a second staggered contact hole are formed in the intermediate dielectric layer to obtain a staggered unit, and the method further includes: etching the intermediate dielectric layer from below along the surface of the intermediate dielectric layer to form a seventh opening that simultaneously exposes at least one of the third common layer and the fourth common layer and the gate stack of the pull-up transistor in the second group of field effect transistors. A conductive material is filled in the seventh opening, and the seventh opening is closed to form a first staggered contact hole QB. On this basis, referring to Fig.53C It is known that in Fig.53C The conductive material on the left side of the figure corresponds to the gate structure of the transfer transistor AC1 in the first group of field effect transistors, and the gate structure is electrically connected to the word line. Fig.53C The conductive material on the right side of the middle corresponds to the gate structure of the pull-up transistor in the second group of field effect transistors, and the gate structure is connected to the second staggered contact hole Q. In addition, the conductive material filled in the opening 134 constitutes a contact hole electrically connected to the first bit line end, the conductive material filled in the opening 133_1 constitutes a contact hole electrically connected to the ground end, and the conductive material filled in the opening 133_2 constitutes a contact hole electrically connected to the second bit line end complementary to the first bit line end. In addition, Fig.53C The conductive layer 126 on the left side of the center is led out from the back of the device, and is electrically connected to the word line terminal WL at the back of the device.

[0100] Based on this, the embodiment of the present disclosure can set the second staggered contact hole Q to be connected to the gate stack of the pull-up transistor in the second group of field effect transistors through the above-mentioned preparation method, and extend to the common layer of the first group of field effect transistors in the intermediate dielectric layer. And, the first staggered contact hole QB is set to be connected to the gate stack of the pull-up transistor in the first group of field effect transistors, and extend to the lower surface of the substrate SUB in the intermediate dielectric layer and pass through the substrate SUB to connect with the common layer of the second group of field effect transistors, thereby realizing the local interconnection of the common layer of the second group of field effect transistors with the gate stack of the pull-up transistor in the first group of field effect transistors through the back gate contact. Thus, the first staggered contact hole QB and the second staggered contact hole Q opposite to the first staggered contact hole QB storage bit form a staggered structure with upper and lower layered symmetry in physical space, which greatly reduces the area of ​​the integrated circuit implemented based on the staggered unit in the horizontal plane, reduces the difficulty of preparation, and is simple in process. Based on this, based on the staggered unit in the present disclosure, an SRAM unit structure in which the back QB and the front Q storage bits are not limited to the same vertical plane can be realized. Furthermore, based on the staggered cells disclosed in the present invention, an equivalent SRAM cell structure in which the back Q and front QB storage bits are reversed can also be realized.

[0101] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present disclosure. Although the embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage. The scope of the present disclosure is defined by the attached claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A split-level unit, comprising: A first group of field effect transistors and a second group of field effect transistors are arranged on the upper surface of the substrate along a first horizontal direction; as well as an intervening dielectric layer surrounding the substrate, the first group of field effect transistors, and the second group of field effect transistors; wherein the first group of field effect transistors and the second group of field effect transistors each include a transmission transistor and a stacked pull-up transistor, and the stacked pull-up transistor includes a pull-down transistor and a pull-up transistor stacked in a vertical direction; The transfer transistor, the pull-down transistor and the pull-up transistor each include: a channel layer; a source / drain layer connected to the channel layer on both sides of the channel layer in the first horizontal direction; a gate stack extending in a second horizontal direction intersecting the first horizontal direction and surrounding the channel layer; the pull-down transistor, the pull-up transistor and the transfer transistor belonging to the same group are coupled via a common layer; A first staggered contact hole connected to the gate stack of the pull-up transistor in the first group of field effect transistors extends in the intermediate dielectric layer to the lower surface of the substrate and passes through the substrate to connect to the common layer of the second group of field effect transistors, thereby forming a staggered structure with a second staggered contact hole used to connect the gate stack of the pull-up transistor in the second group of field effect transistors and the common layer of the first group of field effect transistors, so that the first group of field effect transistors and the second group of field effect transistors are cross-coupled with each other.

2. The split-level unit according to claim 1, wherein: The first group of field effect transistors and the second group of field effect transistors are arranged along the second horizontal direction with spaces between them; The first staggered contact hole extends from the gate stack of the pull-up transistor in the first group of field effect transistors toward the spacing space to the lower surface of the substrate, and passes through the interior of the substrate to connect with the common layer in the second group of field effect transistors; as well as The second staggered contact hole extends from the gate stack of the pull-up transistor in the second group of field effect transistors toward the spacing space to connect with the common layer in the first group of field effect transistors above the substrate.

3. The split-level unit according to claim 2, wherein: The source layer contact hole connected to the upper surface of the source layer of the transmission transistor in the first group of field effect transistors extends downward in the spacing space to the surface of the intermediate dielectric layer to facilitate electrical connection between the transmission transistor in the first group of field effect transistors and the bit line terminal.

4. The split-level unit according to claim 2, wherein: a source layer contact hole connected to the lower surface of the source layer of the pull-up transistor in the second group of field effect transistors, extending downward from the upper surface of the substrate through the substrate to the surface of the intermediate dielectric layer, so that the pull-up transistor in the second group of field effect transistors is electrically connected to the power supply terminal; The source layer contact hole connected to the source layer upper surface of the pull-down transistor in the second group of field effect transistors extends downward in the spacing space to the surface of the intermediate dielectric layer, so that the pull-down transistor in the second group of field effect transistors is electrically connected to the ground terminal.

5. A method for preparing a staggered unit, comprising: A first group of field effect transistors and a second group of field effect transistors are formed on the upper surface of the substrate, which are spaced from each other and arranged along a first horizontal direction; wherein the first group of field effect transistors and the second group of field effect transistors each include a transmission transistor and a stacked pull-up transistor, and the stacked pull-up transistor includes a pull-down transistor and a pull-up transistor stacked along a vertical direction; the transmission transistor, the pull-down transistor and the pull-up transistor each include: a channel layer, a source / drain layer connected to the channel layer on both sides of the channel layer in the first horizontal direction, and a gate stack extending in a second horizontal direction intersecting the first horizontal direction and surrounding the channel layer; the pull-down transistor, the pull-up transistor and the transmission transistor belonging to the same group are coupled via a common layer; forming an intervening dielectric layer surrounding the first group of field effect transistors, the second group of field effect transistors and the substrate; A first staggered-layer contact hole and a second staggered-layer contact hole are formed in the intermediate dielectric layer to obtain a staggered-layer unit; wherein the second staggered-layer contact hole is connected to the gate stack of the pull-up transistor in the second group of field effect transistors, and is simultaneously connected to the common layer of the first group of field effect transistors; the first staggered-layer contact hole is connected to the gate stack of the pull-up transistor in the first group of field effect transistors, and simultaneously extends in the intermediate dielectric layer to the lower surface of the substrate and passes through the substrate to connect to the common layer of the second group of field effect transistors, thereby forming a staggered-layer structure with the second staggered-layer contact hole, so that the first group of field effect transistors and the second group of field effect transistors are cross-coupled with each other.

6. The method according to claim 5, wherein: The intermediate dielectric layer wraps the first group of field effect transistors and the second group of field effect transistors; The method further comprises: Etching the intermediate dielectric layer from above to form a first opening exposing a source layer of a pull-down transistor in the second group of field effect transistors and a second opening exposing a source layer of a transfer transistor in the first group of field effect transistors, wherein a spacing space between the first group of field effect transistors and the second group of field effect transistors partially overlaps with a projection surface of the first opening in a vertical direction, and the spacing space partially overlaps with a projection surface of the second opening in a vertical direction; Filling the first opening and the second opening with a conductive material, and sealing the first opening and the second opening; Etch the intermediate dielectric layer located in the spacing area between the first group of field effect transistors and the second group of field effect transistors from below to form a third opening exposing the conductive material in the first opening and a fourth opening exposing the conductive material in the second opening; Conductive material is filled in the third opening and the fourth opening, thereby forming a source layer contact hole in the intermediate dielectric layer connected to the source layer of the pull-down transistor in the second group of field effect transistors, so that the pull-down transistor in the second group of field effect transistors is electrically connected to the ground terminal, and forming a source layer contact hole in the intermediate dielectric layer connected to the source layer of the transfer transistor in the first group of field effect transistors, so that the transfer transistor in the first group of field effect transistors is electrically connected to the bit line terminal.

7. The method according to claim 5, wherein: The pull-up transistors and the transfer transistors in the second group of field effect transistors are electrically connected via the first common layer, and the pull-down transistors and the transfer transistors in the second group of field effect transistors are electrically connected via the first common layer and the second common layer; The step of forming a first staggered contact hole and a second staggered contact hole in the intermediate dielectric layer to obtain a staggered unit comprises: Etching the intermediate dielectric layer from above to form a fifth opening that simultaneously exposes the first common layer, the second common layer, and the gate stack of the pull-up transistor in the second group of field effect transistors; The fifth opening is filled with a conductive material that contacts the first common layer, the second common layer, and the gate stack of the pull-up transistor in the second group of field effect transistors, and the fifth opening is closed to form the second staggered-layer contact hole.

8. The method according to claim 7, wherein: The pull-up transistors and the transfer transistors in the first group of field effect transistors are electrically connected via the third common layer, and the pull-down transistors and the transfer transistors in the first group of field effect transistors are electrically connected via the third common layer and the fourth common layer; The method further comprises: Etching the intermediate dielectric layer from above along the surface of the intermediate dielectric layer to form a sixth opening exposing the third common layer and the fourth common layer, wherein the spacing space between the first group of field effect transistors and the second group of field effect transistors partially overlaps with a projection surface of the sixth opening in a vertical direction; Filling the sixth opening with a conductive material and closing the sixth opening; The step of forming a first staggered contact hole and a second staggered contact hole in the intermediate dielectric layer to obtain a staggered unit further comprises: Etching the intermediate dielectric layer from below along the surface of the intermediate dielectric layer to form a seventh opening that simultaneously exposes at least one of the third common layer and the fourth common layer and the gate stack of the pull-up transistor in the second group of field effect transistors; A conductive material is filled in the seventh opening, and the seventh opening is closed, thereby forming the first staggered-layer contact hole.

9. The method according to claim 5, wherein: The method further comprises: According to the source layer position of the pull-up transistor in the second group of field effect transistors, the substrate and the intermediate dielectric layer are etched from below to form a source layer contact hole that passes through the substrate and the intermediate dielectric layer and is connected to the lower surface of the source layer of the pull-up transistor in the second group of field effect transistors, so as to facilitate the electrical connection of the pull-up transistor in the second group of field effect transistors with the power supply terminal.

10. The method according to claim 5, wherein: The first group of field effect transistors and the second group of field effect transistors each include a lower fin formed by etching the substrate; The remaining portion of the substrate after etching is connected between the lower fins of the first group of field effect transistors and the second group of field effect transistors; The forming of an intermediate dielectric layer surrounding the first group of field effect transistors, the second group of field effect transistors and the substrate comprises: Etching the portion of the substrate from below until the lower surfaces of the lower fins of the first group of field effect transistors and the second group of field effect transistors are exposed; A dielectric material is deposited on the lower surface of each of the lower fins of the first group of field effect transistors and the second group of field effect transistors to obtain the intermediate dielectric layer.

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