Frequency control method and related device

Abstract

The embodiment of the invention provides a frequency control method and a related device.The frequency control method is achieved based on a system-on-chip comprising a first processor, a second processor and a shared memory, the second processor comprises an application processor core, the application processor core is used for running an application program, and when the frequency control method is implemented, the application processor core is used for running the application program. The second processor configures the frequency modulation mode, and in the hardware frequency modulation mode, the first processor responds to the first adjustment instruction and executes the hardware frequency modulation process, so that in the whole frequency adjustment process, the second processor does not need to generate the frequency adjustment instruction based on a frequency control strategy through a software method; the problem that resources of an application processor core are occupied in the frequency adjustment process is avoided, meanwhile, determination and issuing of the first adjustment instruction do not depend on a scheduling mechanism of an operating system core, and the response speed of frequency adjustment is improved.

Description

Technical Field

[0001] The present specification relates to the field of computer application technology, specifically, to the frequency control technology of processor cores in the field of computer application technology, and more specifically, to a frequency control method and related devices. Background Art

[0002] The frequency of a processor core refers to the speed at which the processor core executes instructions and other target activities per unit time, and is usually measured in Hertz (Hz). How to make the frequency of the processor core meet the requirements of low power consumption while meeting the needs of users has become a research focus for relevant technicians.

[0003] In the related art, the frequency modulation strategy of the processor core is executed by the application processor core through software, which has the problems of slow response speed and occupies the resources of the application processor core itself. Summary of the invention

[0004] The embodiments of this specification provide a frequency control method and related devices to solve the problems of slow response speed and occupation of application processor core resources.

[0005] To achieve the above technical objectives, the embodiments of this specification provide the following technical solutions:

[0006] In a first aspect, an embodiment of the present specification provides a frequency control method, which is applied to a first processor of a system on chip, wherein the system on chip further includes: a second processor and a shared memory, wherein the second processor includes an application processor core, wherein the application processor core is used to run an application program, and the shared memory is used as a communication medium between the first processor and the second processor, wherein the frequency control method includes:

[0007] In response to a target interrupt, read frequency modulation mode parameters from the shared memory, and configure a frequency modulation mode based on the frequency modulation mode parameters, the frequency modulation mode parameters being written into the shared memory by the second processor, the frequency modulation mode parameters comprising: hardware frequency modulation parameters, the target interrupt being triggered by the second processor when a communication channel between the second processor and the application processor core is idle;

[0008] When the frequency modulation mode is the hardware frequency modulation mode corresponding to the hardware frequency modulation parameter, a hardware frequency modulation process is executed in response to the first adjustment instruction.

[0009] Optionally, the hardware frequency modulation process includes:

[0010] Obtaining a working count value of a target counter, where the working count value is used to represent the number of occurrences of a target activity of the application processor core within a target time period;

[0011] determining a load of the application processor core based on a working count value of the target counter;

[0012] Based on the relationship between the load of the application processor core and the load threshold, a frequency adjustment instruction is generated, where the frequency adjustment instruction is used to adjust the operating frequency of the application processor core.

[0013] Optionally, the determining the load of the application processor core based on the working count value of the target counter includes:

[0014] Based on the current operating frequency of the application processor core, obtaining a maximum working count value of the application processor core, wherein the maximum working count value is used to represent a maximum number of occurrences of a target activity of the application processor core within the target time period;

[0015] The load of the application processor core is calculated based on the working count value of the target counter and the maximum working count value of the application processor core.

[0016] Optionally, obtaining a working count value of a target counter includes:

[0017] Acquire a plurality of working count values ​​corresponding to the application processor core and recorded by the target counter, wherein the plurality of working count values ​​include working count values ​​of a plurality of cycles corresponding to the application processor core; the length of each cycle is the target time period;

[0018] The determining the load of the application processor core based on the working count value of the target counter comprises:

[0019] Substituting the current operating frequency of the application processor core and a plurality of working count values ​​corresponding to the application processor core into a target formula to calculate the load of the application processor core;

[0020] The target formula includes:

[0021]

[0022] Among them, load t represents the load of the application processor core, Δt represents the target time period, t represents the number of working count values, E i represents the count value of the i-th job, F i represents the current operating frequency of the application processor core in the i-th cycle, i=1,2…t, k represents a preset constant, and β represents a frequency modulation configuration parameter.

[0023] Optionally, before executing the hardware frequency adjustment process in response to the first adjustment instruction, the method further includes:

[0024] In response to a configuration instruction carrying a target configuration value, configuring a value of a target register;

[0025] The value of the target register is used to determine the frequency modulation configuration parameter.

[0026] Optionally, the load threshold includes a plurality of load sub-thresholds, the plurality of load sub-thresholds constitute a plurality of frequency modulation intervals, the plurality of frequency modulation intervals define a plurality of frequency modulation intervals, and the plurality of frequency modulation intervals respectively correspond to a different frequency modulation strategy;

[0027] The generating the frequency adjustment instruction based on the relationship between the load of the application processor core and the load threshold comprises:

[0028] The frequency adjustment instruction is generated according to the relationship between the load of the application processor core and the multiple frequency modulation intervals and based on the frequency modulation strategy corresponding to the frequency modulation interval into which the load of the application processor core falls.

[0029] Optionally, the operating frequency of the application processor core is divided into multiple operating frequency intervals, and the operating frequency of the multiple operating frequency intervals increases with increasing levels;

[0030] The multiple load sub-thresholds include a first load sub-threshold, a second load sub-threshold, a third load sub-threshold and a fourth load sub-threshold, and the values ​​of the first load sub-threshold, the fourth load sub-threshold, the third load sub-threshold and the second load sub-threshold are decreased in sequence;

[0031] When the load of the application processor core is greater than the first load sub-threshold, the application processor core falls into a first frequency modulation interval, and the frequency modulation strategy corresponding to the first frequency modulation interval includes: setting the operating frequency of the application processor core within the highest level operating frequency interval;

[0032] The load of the application processor core is less than or equal to the first load sub-threshold, and falls into the second frequency modulation interval when it is greater than the fourth load sub-threshold. The frequency modulation strategy corresponding to the second frequency modulation interval includes: raising the operating frequency of the application processor core by one level compared to the operating frequency interval in which the current operating frequency is located;

[0033] The load of the application processor core is less than or equal to the fourth load sub-threshold, and falls into the third frequency modulation interval when it is greater than the third load sub-threshold. The frequency modulation strategy corresponding to the third frequency modulation interval includes: maintaining the operating frequency of the application processor core unchanged in the operating frequency interval where the current operating frequency is located;

[0034] The load of the application processor core is less than or equal to the third load sub-threshold, and falls into a fourth frequency modulation interval when the load is greater than the second load sub-threshold. The frequency modulation strategy corresponding to the fourth frequency modulation interval includes: lowering the operating frequency of the application processor core by one level compared to the operating frequency interval in which the current operating frequency is located;

[0035] When the load of the application processor core is less than or equal to the second load sub-threshold, it falls into the fifth frequency modulation interval, and the frequency modulation strategy corresponding to the fifth frequency modulation interval includes: setting the operating frequency of the application processor core within the lowest level operating frequency interval.

[0036] Optionally, the frequency modulation mode parameter specifically includes: one of a hardware frequency modulation parameter, a software frequency modulation parameter and an automatic frequency modulation parameter;

[0037] The configuring the frequency modulation mode based on the frequency modulation mode parameters comprises: when the frequency modulation mode parameters include the hardware frequency modulation parameters, entering the hardware frequency modulation mode, and generating the first adjustment instruction at predetermined intervals in the hardware frequency modulation mode;

[0038] When the frequency modulation mode parameter includes a software frequency modulation parameter, entering a software frequency modulation mode, in which, in response to a second adjustment instruction carrying a target frequency, the operating frequency of the application processor core is adjusted, the second adjustment instruction being generated by the second processor;

[0039] When the frequency modulation mode parameters include automatic frequency modulation parameters, switching between the hardware frequency modulation mode and the software frequency modulation mode is performed according to the operating parameters of the second processor.

[0040] In a second aspect, an embodiment of the present specification provides a system on chip, including: a first processor, a second processor and a shared memory, the second processor includes an application processor core, the application processor core is used to run an application program, the shared memory is used as a communication medium between the first processor and the second processor, and the first processor is configured as follows:

[0041] In response to a target interrupt, read frequency modulation mode parameters from the shared memory, and configure a frequency modulation mode based on the frequency modulation mode parameters, the frequency modulation mode parameters being written into the shared memory by the second processor, the frequency modulation mode parameters comprising: hardware frequency modulation parameters, the target interrupt being triggered by the second processor when a communication channel between the second processor and the application processor core is idle;

[0042] When the frequency modulation mode is the hardware frequency modulation mode corresponding to the hardware frequency modulation parameter, a hardware frequency modulation process is executed in response to the first adjustment instruction.

[0043] In a third aspect, an embodiment of the present specification further provides a computing device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the frequency control method as described above when executing the computer program.

[0044] In a fourth aspect, an embodiment of the present specification further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the frequency control method as described above is implemented.

[0045] In a fifth aspect, an embodiment of the present specification provides a computer program product or a computer program, wherein the computer program product includes a computer program, and the computer program is stored in a computer-readable storage medium; the processor of the computer device reads the computer program from the computer-readable storage medium, and the processor implements the steps of the above-mentioned frequency control method when executing the computer program.

[0046] It can be seen from the above technical solution that the embodiment of this specification provides a frequency control method and related devices, wherein the frequency control method is implemented based on a system on a chip including a first processor, a second processor and a shared memory, the second processor includes an application processor core, and the application processor core is used to run an application program. When the frequency control method is implemented, the second processor configures the frequency modulation mode. In the hardware frequency modulation mode, the first processor responds to the first adjustment instruction and executes the hardware frequency modulation process. In this way, during the entire frequency adjustment process, there is no need for the second processor to generate a frequency adjustment instruction based on the frequency control strategy through a software method, thereby avoiding the problem of the frequency adjustment process occupying the resources of the application processor core. At the same time, the determination and issuance of the first adjustment instruction do not need to rely on the scheduling mechanism of the operating system kernel, which is conducive to improving the response speed of the frequency adjustment. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of this specification or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this specification. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0048] Figure 1 A schematic diagram of the structure of a system on a chip provided for one embodiment of the present specification;

[0049] Figure 2 A flow chart of a frequency control method provided for one embodiment of this specification;

[0050] Figure 3 A signaling flow diagram of a frequency control method provided for one embodiment of this specification;

[0051] Figure 4 A flow chart of a frequency control method provided for another embodiment of the present specification;

[0052] Figure 5 A feasible process for generating a frequency adjustment instruction based on a load is provided for one embodiment of the present specification;

[0053] Figure 6 A feasible process for generating a frequency adjustment instruction based on power consumption is provided for one embodiment of the present specification;

[0054] Figure 7 A schematic diagram of the structure of a computing device provided for one embodiment of the present specification. DETAILED DESCRIPTION

[0055] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of this specification shall have the common meanings understood by persons with ordinary skills in the field to which this specification belongs. The words "first", "second" and similar words used in the embodiments of this specification do not indicate any order, quantity or importance, but are only used to avoid confusion of constituent elements.

[0056] Unless the context requires otherwise, throughout the specification, "plurality" means "at least two", and "including" is interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples", "specific examples" or "some examples" are intended to indicate that a particular feature, structure, material or characteristic associated with the embodiment or example is included in at least one embodiment or example of the specification. The schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0057] The following will be combined with the drawings in the embodiments of this specification to clearly and completely describe the technical solutions in the embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this specification.

[0058] Overview

[0059] As described in the background technology, frequency adjustment of the processor core is of great significance for reducing the power consumption of the processor core. DVFS (Dynamic Voltage and Frequency Scaling) is essentially a low-power technology. Its purpose is to set the operating voltage and clock frequency according to the actual power consumption of the processor core at that time, so as to ensure that the power provided meets the requirements and does not have excess performance, thereby reducing power consumption. At present, in the relevant technology, dynamic voltage and frequency adjustment is mostly achieved through software-level processor frequency control. The application processor core monitors the current load of itself or other application processor cores through software, and calculates and sets the appropriate operating frequency of the processor core based on the current frequency modulation strategy (such as ondemand (on-demand frequency modulation strategy), performance (high-performance frequency modulation strategy) and powersave (energy-saving frequency modulation strategy), etc.), and then sends a frequency modulation request to the controller through the kernel cpufreq driver to request adjustment of the operating frequency of the processor core. In this process, there are at least two problems:

[0060] 1. Limited response speed and frequency adjustment accuracy: Since the software control method relies on the scheduling mechanism of the operating system kernel, the response speed is slow. For rapidly changing loads, the frequency adjustment may lag behind the actual demand, affecting the performance or energy efficiency of the processor core.

[0061] 2. Resource usage and performance overhead of the application processor core: Software control requires the operating system kernel to participate in frequency adjustment decisions and request issuance, which increases the kernel burden and may cause additional performance overhead. Especially in high-load scenarios, frequent software control operations may occupy processor core resources and affect system performance.

[0062] In order to solve the above problems, the inventors have found that a frequency control method can be provided based on an on-chip system including a first processor, a second processor and a shared memory. The second processor includes an application processor core, and the application processor core is used to run an application program. When the frequency control method is implemented, the second processor configures the frequency modulation mode. In the hardware frequency modulation mode, the first processor responds to the first adjustment instruction and executes the hardware frequency modulation process. In this way, during the entire frequency adjustment process, there is no need for the second processor to generate a frequency adjustment instruction based on the frequency control strategy through a software method, thereby avoiding the problem of the frequency adjustment process occupying the resources of the application processor core. At the same time, the determination and issuance of the first adjustment instruction do not need to rely on the scheduling mechanism of the operating system kernel, which is conducive to improving the response speed of the frequency adjustment.

[0063] Based on the above concept, an embodiment of the present specification provides a frequency control method, and the frequency control method provided in the embodiment of the present specification will be exemplarily described below in conjunction with the accompanying drawings.

[0064] Exemplary Methods

[0065] The frequency control method provided in the embodiments of this specification can be based on Figure 1 The system-on-chip 100 shown implements Figure 1 In the embodiment, the second processor 20 includes an application processor core 211 , and the second processor 20 and the first processor 10 are communicatively connected via an on-chip network 30 .

[0066] The on-chip network 30 is a communication network between various components within the entire processor architecture, and is used to provide communication links between various components within the processor architecture. Various types of buses, bus interfaces, etc. can be integrated in the on-chip network 30 to meet the communication requirements of various processor architecture components such as the first processor 10 and the second processor 20 based on any type of bus.

[0067] The second processor 20 can be used as an application processor (AP) in the processor architecture, and the application processor core 211 in the second processor 20 can be the operation and control center of the entire processor architecture, used to execute instructions and operations. In some embodiments, the application processor core 211 can be used to start and control other processor cores in the processor architecture, such as the processor core in the first processor 10. For example, before the processor core in the first processor 10 is started, the application processor core 211 of the second processor 20 can copy the firmware program stored in the memory to the SRAM (Static Random-Access Memory) of the first processor 10, so that the processor core in the first processor 10 can load the firmware program from the SRAM to start running.

[0068] The second processor 20 may include one or more application processor cores 211. Figure 1 In the embodiment, multiple application processor cores 211 are divided into multiple processor core clusters 21, and each processor core cluster 21 includes at least one application processor core 211. Different processor core clusters 21 can be powered by different power supplies, so a processor core cluster can also be called a power domain. When the frequency and power consumption of the application processor cores 211 are controlled, the voltages of the application processor cores 211 in the same processor core cluster 21 can be adjusted to a consistent value, and the voltages of the application processor cores 211 in different processor core clusters 21 can be adjusted to different values.

[0069] The first processor 10 may include at least one dedicated processor core, which may be responsible for the frequency control method of the application processor core, etc. The architecture of the dedicated processor core and the application processor core may be the same or different. In some embodiments, the first processor 10 may also be responsible for programs related to the security of the second processor 20. At this time, the first processor 10 may serve as a secure coprocessor (SCP) of the system on chip, and its security level may be higher than the security level of the second processor 20. The first processor 10 may be equipped with a security measurement service module to meet the needs of security measurement of other modules. In other embodiments, the first processor 10 may not integrate security-related functions. At this time, the computing burden of the dedicated processor core is lower than that of the application processor core. Therefore, a RISC-V (Reduced Instruction Set Computer-Five, the fifth generation of reduced instruction set computer) core, that is, a processor core with a relatively simple architecture such as the RISC-V instruction architecture, may be used as the dedicated processor core to reduce the operating power consumption of the dedicated processor core.

[0070] In some embodiments, in addition to being able to interact with the second processor 20 through the on-chip network 30, in order to improve communication efficiency, after the on-chip system is started, the second processor 20 can establish a communication channel with the first processor 10, and can apply for a shared memory as a communication medium between the first processor 10 and the second processor 20. Instructions or interrupts can be transmitted through the communication channel, and specific parameters and other information can be transmitted through the shared memory. The communication channel can provide a security mechanism, and the two parties of communication based on the communication channel are relatively independent. Data transmission is carried out through clear messages, which reduces the competition for shared resources. Therefore, the security mechanism provided by the communication channel can ensure the safe and reliable transmission of important information such as instructions or interrupts; and the shared memory can support data sharing directly in the memory, which is conducive to reducing the overhead of data replication. In addition, the two parties communicating based on the shared memory do not need a complex protocol stack, and can directly read data based on the shared memory. Therefore, the high performance and flexibility of the shared memory in information transmission are used to ensure the fast and efficient transmission of information such as parameters.

[0071] Based on Figure 1 The system on chip shown in the figure, an embodiment of the present specification provides a feasible frequency control method, such as Figure 2 As shown, the frequency control method includes:

[0072] S201: In response to a target interrupt, read frequency modulation mode parameters from the shared memory, and configure a frequency modulation mode based on the frequency modulation mode parameters, the frequency modulation mode parameters being written into the shared memory by the second processor, the frequency modulation mode parameters comprising: hardware frequency modulation parameters, the target interrupt being triggered by the second processor when a communication channel between the second processor and the application processor core is idle;

[0073] S202: When the frequency modulation mode is the hardware frequency modulation mode corresponding to the hardware frequency modulation parameter, in response to a first adjustment instruction, execute a hardware frequency modulation process.

[0074] refer to Figure 3 , Figure 3 A schematic diagram of the signaling process between the first processor and the second processor is shown. Before the second processor sends a target interrupt to the first processor, it needs to ensure that the communication channel is in an idle state. When the communication channel is idle, the target interrupt can be sent to the first processor through the communication channel, and the frequency modulation mode parameters can be written into the shared memory. After receiving the target interrupt, the first processor saves and switches the context, responds to the target interrupt, reads the frequency modulation mode parameters from the shared memory, and configures the frequency modulation mode based on the frequency modulation mode parameters.

[0075] In the subsequent operation process, if the frequency modulation mode is the hardware frequency modulation mode, the hardware frequency modulation process is executed in response to the first adjustment instruction. In this way, in the entire frequency adjustment process, there is no need for the second processor to generate a frequency adjustment instruction based on the frequency control strategy through a software method, thereby avoiding the problem of the frequency adjustment process occupying the resources of the application processor core. At the same time, the determination and issuance of the first adjustment instruction do not need to rely on the scheduling mechanism of the operating system kernel, which is conducive to improving the response speed of the frequency adjustment. The first adjustment instruction can be generated periodically or randomly by the first processor in the hardware frequency modulation mode. This specification does not limit this, and it depends on the actual situation.

[0076] In addition to the hardware frequency modulation mode, some embodiments of the present specification may also include a software frequency modulation mode corresponding to the software frequency modulation parameters. In the software frequency modulation mode, the second processor core may determine the frequency and generate a second adjustment instruction carrying the target frequency to adjust the operating frequency of the application processor core. In addition, the frequency modulation mode parameters may also include automatic frequency modulation parameters. The automatic frequency modulation parameters correspond to the automatic frequency modulation mode. In the automatic frequency modulation mode, the hardware naughty mode and the software naughty mode may be switched according to the operating parameters of the second processor. Specifically, the system on chip also includes: a shared memory, the shared memory serving as a communication medium between the first processor and the second processor;

[0077] The step of executing the hardware frequency adjustment process in response to the first adjustment instruction also includes:

[0078] In response to a target interrupt, a frequency modulation mode parameter is read from the shared memory, the frequency modulation mode parameter is written into the shared memory by the second processor, the frequency modulation mode parameter includes: one of a hardware frequency modulation parameter, a software frequency modulation parameter and an automatic frequency modulation parameter; the target interrupt is triggered by the second processor when a communication channel between the second processor and the application processor core is idle;

[0079] When the frequency modulation mode parameter includes the hardware frequency modulation parameter, configuring to enter the hardware frequency modulation mode, and generating the first adjustment instruction at a predetermined time interval;

[0080] When the frequency modulation mode parameter includes a software frequency modulation parameter, configuring to enter a software frequency modulation mode, and adjusting the operating frequency of the application processor core in response to a second adjustment instruction carrying a target frequency, wherein the second adjustment instruction is generated by the second processor;

[0081] When the frequency modulation mode parameters include automatic frequency modulation parameters, switching between the hardware frequency modulation mode and the software frequency modulation mode is performed according to the operating parameters of the second processor.

[0082] Thus, in this embodiment, a plurality of configurable frequency modulation modes are provided to the user, which can increase the user's freedom of choice. The hardware frequency modulation process may refer to a process in which the first processor monitors the load of the application processor core, determines the target frequency corresponding to the application processor core based on the load, and adjusts the frequency of the application processor core to the target frequency. For more specific definitions of the hardware frequency modulation process, please refer to the relevant description below.

[0083] In addition to the aforementioned method of configuring the frequency modulation mode through the communication channel and the shared memory, in some implementations, the hardware frequency modulation mode may also be the default.

[0084] For example, in some embodiments, another frequency control method is provided, which is applied to a first processor of a system on chip, wherein the system on chip further includes: a second processor, wherein the second processor includes an application processor core, and the application processor core is used to run an application program, such as Figure 4 As shown, the frequency control method includes:

[0085] S401: In response to a first adjustment instruction, executing a hardware frequency adjustment process;

[0086] The hardware frequency modulation process includes:

[0087] Obtaining a working count value of a target counter, where the working count value is used to represent the number of occurrences of a target activity of the application processor core within a target time period;

[0088] determining a load of the application processor core based on a working count value of the target counter;

[0089] Based on the relationship between the load of the application processor core and the load threshold, a frequency adjustment instruction is generated, where the frequency adjustment instruction is used to adjust the operating frequency of the application processor core.

[0090] In this embodiment, the first processor executes the hardware frequency adjustment process in response to the generated first adjustment instruction, and there is no need for the second processor to generate the frequency adjustment instruction based on the frequency control strategy through a software method, thereby avoiding the problem of the frequency adjustment process occupying the resources of the application processor core. At the same time, the determination and issuance of the first adjustment instruction do not need to rely on the scheduling mechanism of the operating system kernel, which is conducive to improving the response speed of frequency adjustment.

[0091] Specifically, the target counter includes but is not limited to an AMU (Activity Monitoring Unit) counter, and the count value of the AMU is used to characterize the number of clock cycles of the application processor core, the number of instructions executed, and other quantities, which characterize the number of occurrences of the target activity of the application processor core within the target time period (correspondingly, the target activity may include activities such as executing instructions). Based on the working count value, the working state parameters of the application processor core can be determined, and the working state parameters include but are not limited to at least one of load and power consumption. After determining the working state parameters of the application processor core, a frequency adjustment instruction can be generated based on the relationship between the working state parameters and the parameter threshold, and the frequency adjustment instruction can be used to adjust the working frequency of the application processor core. Specifically, in one embodiment, based on the frequency adjustment instruction, a specific phase-locked loop real clock can be generated and given to the corresponding application processor core, so that the application processor core can reach the corresponding target frequency. Optionally, in one embodiment, reference Figure 1 When the second processor includes one or more processor core clusters, the frequency adjustment instruction can correspond to the processor core cluster, that is, the frequency adjustment instruction can be used to adjust the frequency of all processor cores in a processor core cluster, and the frequency of processor cores in different processor core clusters can be adjusted respectively by different frequency adjustment instructions.

[0092] In one embodiment of the present specification, a feasible method for calculating the load of an application processor core based on the working count value of a target counter is proposed when the working status parameter includes the load. Specifically:

[0093] The determining the load of the application processor core based on the working count value of the target counter comprises:

[0094] Based on the current operating frequency of the application processor core, obtaining a maximum working count value of the application processor core, wherein the maximum working count value is used to represent a maximum number of occurrences of a target activity of the application processor core within the target time period;

[0095] The load of the application processor core is calculated based on the working count value of the target counter and the maximum working count value of the application processor core.

[0096] Specifically, in this implementation, the process of determining the working state parameter of the application processor core based on the working count value of the target counter can be expressed as the following formula:

[0097]

[0098] Wherein, load represents the load of the application processor core, E represents the working counter, F represents the current working frequency of the application processor core, ΔtF represents the maximum working count value of the application processor core, and k is a constant.

[0099] In this embodiment, the load of the application processor core can be determined by the working count value of the target counter, without the need to monitor the load based on the program running on the application processor core, which is beneficial to reducing the computing burden of the application processor core and improving the execution speed and efficiency of the method.

[0100] In one embodiment, in order to configure the frequency adjustment strategy, obtaining the working count value of the target counter includes:

[0101] Acquire a plurality of working count values ​​corresponding to the application processor core and recorded by the target counter, wherein the plurality of working count values ​​include working count values ​​of a plurality of cycles corresponding to the application processor core; the length of each cycle is the target time period;

[0102] The determining the load of the application processor core based on the working count value of the target counter comprises:

[0103] Substituting the current operating frequency of the application processor core and a plurality of working count values ​​corresponding to the application processor core into a target formula to calculate the load of the application processor core;

[0104] The target formula includes:

[0105]

[0106] Among them, load t represents the load of the application processor core, Δt represents the target time period, t represents the number of working count values, E i represents the count value of the i-th job, Fi represents the current operating frequency of the application processor core in the i-th cycle, i=1,2…t, k represents a preset constant, and β represents a frequency modulation configuration parameter.

[0107] In this embodiment, the load of the application processor core is characterized by the average value of the load in multiple unit times, so that the load of the application processor core will not be less sensitive to the drastic fluctuation of the load in a single unit time, and the load of the application processor core will be prevented from fluctuating abnormally with the drastic fluctuation of the load in a unit time. The larger the frequency modulation configuration parameter, the more loads per unit time are used when solving the load of the application processor core, and the less sensitive the solved load of the application processor core is to the fluctuation of the load in a single unit time; correspondingly, the smaller the frequency modulation configuration parameter, the more sensitive the solved load of the application processor core is to the fluctuation of the load in a single unit time. By selecting the frequency modulation configuration parameter, the policy configuration of the frequency control method can be implemented.

[0108] In an optional implementation, a feasible configuration process of frequency modulation configuration parameters is provided. Specifically, before executing the hardware frequency modulation process in response to the first adjustment instruction, the process further includes:

[0109] In response to a configuration instruction carrying a target configuration value, configuring a value of a target register;

[0110] The value of the target register is used to determine the frequency modulation configuration parameter.

[0111] In this embodiment, the frequency modulation configuration parameters are determined by the value of a specific target register. There is no need to configure the program running through the application processor core or rely on the scheduling mechanism of the operating system kernel. The parameters configured through the program are sent down, which is beneficial to increasing the implementation speed and efficiency of the method.

[0112] In a feasible implementation, a feasible generation process of a frequency adjustment instruction is provided, such as Figure 5 As shown, the load threshold includes a plurality of load sub-thresholds, the plurality of load sub-thresholds constitute a plurality of frequency modulation intervals, the plurality of frequency modulation intervals define a plurality of frequency modulation intervals, and the plurality of frequency modulation intervals respectively correspond to a different frequency modulation strategy;

[0113] The generating the frequency adjustment instruction based on the relationship between the load of the application processor core and the load threshold comprises:

[0114] The frequency adjustment instruction is generated according to the relationship between the load of the application processor core and the multiple frequency modulation intervals and based on the frequency modulation strategy corresponding to the frequency modulation interval into which the load of the application processor core falls.

[0115] Specifically, still refer to Figure 5, the operating frequency of the application processor core is divided into multiple operating frequency intervals, and the operating frequency of the multiple operating frequency intervals increases with the increase of the level;

[0116] The multiple load sub-thresholds include a first load sub-threshold, a second load sub-threshold, a third load sub-threshold and a fourth load sub-threshold, and the values ​​of the first load sub-threshold, the fourth load sub-threshold, the third load sub-threshold and the second load sub-threshold are decreased in sequence;

[0117] When the load of the application processor core is greater than the first load sub-threshold, the application processor core falls into a first frequency modulation interval, and the frequency modulation strategy corresponding to the first frequency modulation interval includes: setting the operating frequency of the application processor core within the highest level operating frequency interval;

[0118] The load of the application processor core is less than or equal to the first load sub-threshold, and falls into the second frequency modulation interval when it is greater than the fourth load sub-threshold. The frequency modulation strategy corresponding to the second frequency modulation interval includes: raising the operating frequency of the application processor core by one level compared to the operating frequency interval in which the current operating frequency is located;

[0119] The load of the application processor core is less than or equal to the fourth load sub-threshold, and falls into the third frequency modulation interval when it is greater than the third load sub-threshold. The frequency modulation strategy corresponding to the third frequency modulation interval includes: maintaining the operating frequency of the application processor core unchanged in the operating frequency interval where the current operating frequency is located;

[0120] The load of the application processor core is less than or equal to the third load sub-threshold, and falls into a fourth frequency modulation interval when the load is greater than the second load sub-threshold. The frequency modulation strategy corresponding to the fourth frequency modulation interval includes: lowering the operating frequency of the application processor core by one level compared to the operating frequency interval in which the current operating frequency is located;

[0121] When the load of the application processor core is less than or equal to the second load sub-threshold, it falls into the fifth frequency modulation interval, and the frequency modulation strategy corresponding to the fifth frequency modulation interval includes: setting the operating frequency of the application processor core within the lowest level operating frequency interval.

[0122] In this embodiment, the operating frequency interval of the application processor core can be set to multiple levels (for example, 100 levels). Each time the adjustment is made, the corresponding level adjustment is made according to the frequency modulation interval that the load falls into. In this way, when the load is not too high or too low (i.e., when it falls into the second to fourth frequency modulation intervals), the operating frequency interval is kept unchanged or adjusted up or down by one level, so as to achieve gradual adjustment of the frequency of the application processor core and avoid frequent and large-scale frequency adjustments. At the same time, when the load is too high (falling into the first frequency modulation interval), it is supported to set the operating frequency of the application processor core at the highest level to ensure normal operation under high load and meet the user's high performance requirements for the system on chip; at the same time, when the load is too low (falling into the fifth frequency modulation interval), it is supported to set the operating frequency of the application processor core to the lowest level of the operating frequency interval, so that when the performance requirements are low, the system on chip is guaranteed to run in a low power consumption state.

[0123] In addition, in this embodiment, a "dead zone" (ie, the third frequency modulation interval) in which the frequency remains unchanged is set to avoid invalid repeated frequency adjustments.

[0124] In addition to adjusting the frequency of the application processor core based on the load, the frequency of the application processor core can also be adjusted based on the power consumption. Prior to this, the implementation method of this specification provides a feasible calculation process of the current power consumption. Specifically, the working state parameter includes the current power consumption;

[0125] The determining the load of the application processor core based on the working count value of the target counter comprises:

[0126] Based on the current operating frequency of the application processor core, obtaining a maximum working count value of the application processor core, wherein the maximum working count value is used to represent a maximum number of occurrences of a target activity of the application processor core within the target time period;

[0127] Calculating a load of the application processor core based on a working count value of the target counter and a maximum working count value of the application processor core;

[0128] Determining an operating voltage corresponding to the application processor core based on a load of the application processor core;

[0129] Based on the operating voltage and the operating current corresponding to the application processor core, the current power consumption of the application processor core is determined.

[0130] In this embodiment, similarly, the load of the application processor core is calculated by the working counter of the target counter, and the current power consumption of the application processor core is further calculated. In this way, there is no need to monitor the load through the program running on the application processor core, which is beneficial to reducing the burden on the application processor core. At the same time, there is no need to rely on the scheduling mechanism of the operating system kernel, which is beneficial to improving the response speed of the method.

[0131] In one embodiment, a feasible way to generate frequency adjustment instructions based on power consumption is provided, such as Figure 6 As shown, the parameter threshold includes a power consumption threshold, the power consumption threshold includes a first power consumption sub-threshold and a second power consumption sub-threshold, and the first power consumption sub-threshold is greater than the second power consumption sub-threshold;

[0132] The generating the frequency adjustment instruction based on the relationship between the load of the application processor core and the load threshold comprises:

[0133] When the current power consumption of the application processor core is greater than the first power consumption sub-threshold, and the duration for which the current power consumption of the application processor core is greater than the first power consumption sub-threshold exceeds a first preset duration, generating a first instruction, wherein the first instruction is used to control the frequency of the application processor core to decrease so that the power consumption of the application processor core is less than the first power consumption sub-threshold;

[0134] When the current power consumption of the application processor core is less than or equal to the first power consumption sub-threshold, and greater than the second power consumption sub-threshold, and the application processor core has passed the first operation stage but has not passed the second operation stage, a second instruction is generated, wherein the second instruction is used to control the frequency of the application processor core to be reduced so that the power consumption of the application processor core is less than the second power consumption sub-threshold, and the power consumption of the application processor core is limited to not exceed the first power consumption sub-threshold; the first operation stage includes: the power consumption of the application processor core exceeds the first power consumption sub-threshold and runs for a first preset time; the second operation stage includes: the power consumption of the application processor core is lower than the second power consumption sub-threshold and runs for a second preset time;

[0135] When the current power consumption of the application processor core is less than the second power consumption sub-threshold, and the duration for which the current power consumption of the application processor core is less than the second power consumption sub-threshold exceeds a second preset duration, generating a third instruction, wherein the third instruction is used to control the frequency of the application processor core to increase so as to allow the power consumption of the application processor core to be greater than the second power consumption sub-threshold;

[0136] When the current power consumption of the application processor core is less than or equal to the first power consumption sub-threshold and greater than the second power consumption sub-threshold, and the application processor core passes through the first operation stage and the second operation stage, a fourth instruction is generated, wherein the fourth instruction is used to control the frequency of the application processor core to remain unchanged or to increase, so as to allow the power consumption of the application processor core to operate within a target range or greater than the second power consumption sub-threshold;

[0137] The target interval includes being greater than the second power consumption sub-threshold and less than the first power consumption sub-threshold.

[0138] exist Figure 6 In the figure, the first power consumption sub-threshold is represented by Power Limit3, the second power consumption sub-threshold is represented by Power Limit1, and the "dead zone" between the first power consumption sub-threshold and the third power consumption sub-threshold is used, that is, the power consumption wall is between the first power consumption sub-threshold and the third power consumption sub-threshold (that is, the power consumption range of the application processor core allowed under normal circumstances), and PowerLimit2 is the average of the first power consumption sub-threshold and the third power consumption sub-threshold, that is, Power Limit3 = Power Limit 2 + p, Power Limit1 = Power Limit2 - p.

[0139] T1 is the upper limit of the time when the running power consumption of the running application processor core exceeds the power consumption wall, that is, the first preset duration. When the user performs a high-power operation (such as opening an application, etc.), the running power consumption of the application processor core is temporarily allowed to exceed the first power consumption sub-threshold for a maximum of T1 time. T1 is approximately equal to T5, and T5 is the second preset duration. When the current power consumption of the application processor core exceeds the first power consumption sub-threshold each time, the current power consumption of the application processor core is required to be lower than the second power consumption sub-threshold for T5 time before the running power consumption of the application processor core is allowed to exceed the first power consumption sub-threshold again. Otherwise, even if the user continuously performs high-power consumption operations, the power consumption of the application processor core will only be limited to below the first power consumption sub-threshold.

[0140] T2 and T3 may represent examples of time intervals for adjusting the frequency of the application processor core each time the power consumption is monitored, and there may be multiple such processes between T1 and T4. T4 is the duration during which the current power consumption of the application processor core is running smoothly within the power consumption wall.

[0141] In this embodiment, through this power consumption control strategy, the application processor core can be allowed to be briefly turbo-clocked to meet the user's performance requirements for the application processor core, while ensuring that the power consumption of the application processor core operates within the power consumption wall range most of the time, thereby avoiding damage to the life of the application processor core that may be caused by long-term or frequent turbo-clocking.

[0142] Exemplary Devices

[0143] In an exemplary embodiment of the present specification, a frequency control device is further provided, which is applied to a first processor of a system on chip, wherein the system on chip further includes: a second processor, wherein the second processor includes an application processor core, wherein the application processor core is used to run an application program, and the frequency control device includes:

[0144] A first frequency modulation module, configured to execute a hardware frequency modulation process in response to a first adjustment instruction;

[0145] The hardware frequency modulation process includes:

[0146] Obtaining a working count value of a target counter, where the working count value is used to represent the number of occurrences of a target activity of the application processor core within a target time period;

[0147] determining a load of the application processor core based on a working count value of the target counter;

[0148] Based on the relationship between the load of the application processor core and the load threshold, a frequency adjustment instruction is generated, where the frequency adjustment instruction is used to adjust the operating frequency of the application processor core.

[0149] In an exemplary embodiment of the present specification, a frequency control device is further provided, which is applied to a first processor of a system on chip, wherein the system on chip further includes: a second processor and a shared memory, wherein the second processor includes an application processor core, wherein the application processor core is used to run an application program, and the shared memory is used as a communication medium between the first processor and the second processor, wherein the frequency control device includes:

[0150] a second frequency modulation module, configured to read frequency modulation mode parameters from the shared memory in response to a target interrupt, and configure a frequency modulation mode based on the frequency modulation mode parameters, the frequency modulation mode parameters being written into the shared memory by the second processor, the frequency modulation mode parameters comprising: hardware frequency modulation parameters, the target interrupt being triggered by the second processor when a communication channel between the second processor and the application processor core is idle;

[0151] When the frequency modulation mode is the hardware frequency modulation mode corresponding to the hardware frequency modulation parameter, a hardware frequency modulation process is executed in response to the first adjustment instruction.

[0152] For the specific definition of the frequency control device, please refer to the definition of the frequency control method above, which will not be repeated here. Each module in the above frequency control device can be implemented in whole or in part by software, hardware and a combination thereof. Each of the above modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to each of the above modules.

[0153] Exemplary Devices

[0154] The embodiments of the present specification also provide a system on a chip, such as Figure 1 As shown, it includes: a first processor and a second processor, the second processor includes an application processor core, the application processor core is used to run an application program, and the first processor is configured as follows:

[0155] In response to the first adjustment instruction, executing a hardware frequency adjustment process;

[0156] The hardware frequency modulation process includes:

[0157] Obtaining a working count value of a target counter, where the working count value is used to represent the number of occurrences of a target activity of the application processor core within a target time period;

[0158] determining a load of the application processor core based on a working count value of the target counter;

[0159] Based on the relationship between the load of the application processor core and the load threshold, a frequency adjustment instruction is generated, where the frequency adjustment instruction is used to adjust the operating frequency of the application processor core.

[0160] Regarding the relevant limitations of the system on chip, please refer to the relevant description of the frequency control method in the above text, and this specification will not go into details here.

[0161] Another embodiment of the present application further provides a computing device, see Figure 7 As shown, an exemplary embodiment of the present specification also provides a computing device, including: a memory and a processor, the memory storing a computer program, and the processor executing the computer program when executing the computer program performs the steps of the frequency control method according to various embodiments of the present specification described in the above embodiments of the present specification.

[0162] The internal structure of the computing device can be as follows Figure 7As shown, the computing device includes a processor, a memory, a network interface and an input device connected through a system bus. Among them, the processor of the computing device is used to provide computing and control capabilities. The memory of the computing device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computing device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the steps of the frequency control method according to various embodiments of the present specification described in the above embodiments of the present specification are performed.

[0163] The processor may include a main processor and may also include a baseband chip, a modem, etc.

[0164] The memory stores a program for executing the technical solution of the present invention, and may also store an operating system and other key services. Specifically, the program may include a program code, and the program code includes computer operation instructions. More specifically, the memory may include a read-only memory (ROM), other types of static storage devices that can store static information and instructions, a random access memory (RAM), other types of dynamic storage devices that can store information and instructions, a disk storage, a flash, and the like.

[0165] The processor may be a general-purpose processor, such as a general-purpose central processing unit (CPU), a microprocessor, etc., or an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the scheme of the present invention. It may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component.

[0166] The input device may include a device for receiving data and information input by a user, such as a keyboard, a mouse, a camera, a scanner, a light pen, a voice input device, a touch screen, a pedometer, or a gravity sensor.

[0167] Output devices may include means that allow information to be output to a user, such as display screens, printers, speakers, etc.

[0168] The communication interface may include using any transceiver or the like to communicate with other devices or communication networks, such as Ethernet, Radio Access Network (RAN), Wireless Local Area Network (WLAN), etc.

[0169] The processor executes the program stored in the memory and calls other devices, which can be used to implement each step of any frequency control method provided in the above embodiments of the present application.

[0170] The computing device may also include a display component and a voice component. The display component may be a liquid crystal display or an electronic ink display. The input device of the computing device may be a touch layer covered on the display component, or a button, trackball or touchpad provided on the housing of the computing device, or an external keyboard, touchpad or mouse.

[0171] Those skilled in the art will understand that Figure 7 The structure shown in the figure is only a block diagram of a part of the structure related to the scheme of this specification, and does not constitute a limitation on the computing device to which the scheme of this specification is applied. The specific computing device may include more or fewer components than shown in the figure, or combine certain components, or have a different arrangement of components.

[0172] Exemplary computer program products and storage media

[0173] In addition to the above-mentioned methods and devices, the frequency control method provided in the embodiments of the present specification may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the frequency control method according to various embodiments of the present specification described in the above-mentioned "Exemplary Method" section of the present specification.

[0174] The computer program product may be written in any combination of one or more programming languages ​​to write program code for performing the operations of the embodiments of the present specification, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0175] In addition, an embodiment of the present specification also provides a computer-readable storage medium on which a computer program is stored, and the computer program is executed by a processor to execute the steps of the frequency control method according to various embodiments of the present specification described in the above "Exemplary Method" section of the present specification.

[0176] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this specification can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0177] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0178] The above-mentioned embodiments only express several implementation methods of this specification, and the descriptions are relatively specific and detailed, but they cannot be understood as limiting the scope of the solutions provided by the embodiments of this specification. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of this specification, which all belong to the protection scope of this specification. Therefore, the protection scope of the patent of this specification shall be based on the attached claims.

Claims

1. A frequency control method, characterized in that: A first processor applied to a system on chip, the system on chip further comprising: a second processor and a shared memory, the second processor comprising an application processor core, the application processor core being used to run an application program, the shared memory being used as a communication medium between the first processor and the second processor, the frequency control method comprising: In response to a target interrupt, read frequency modulation mode parameters from the shared memory, and configure a frequency modulation mode based on the frequency modulation mode parameters, the frequency modulation mode parameters being written into the shared memory by the second processor, the frequency modulation mode parameters comprising: hardware frequency modulation parameters, the target interrupt being triggered by the second processor when a communication channel between the second processor and the application processor core is idle; When the frequency modulation mode is the hardware frequency modulation mode corresponding to the hardware frequency modulation parameter, a hardware frequency modulation process is executed in response to the first adjustment instruction.

2. The method according to claim 1, characterized in that The hardware frequency modulation process includes: Obtaining a working count value of a target counter, where the working count value is used to represent the number of occurrences of a target activity of the application processor core within a target time period; determining a load of the application processor core based on a working count value of the target counter; Based on the relationship between the load of the application processor core and the load threshold, a frequency adjustment instruction is generated, where the frequency adjustment instruction is used to adjust the operating frequency of the application processor core.

3. The method according to claim 2, characterized in that The determining the load of the application processor core based on the working count value of the target counter comprises: Based on the current operating frequency of the application processor core, obtaining a maximum working count value of the application processor core, wherein the maximum working count value is used to represent a maximum number of occurrences of a target activity of the application processor core within the target time period; The load of the application processor core is calculated based on the working count value of the target counter and the maximum working count value of the application processor core.

4. The method according to claim 2, characterized in that: The obtaining of the working count value of the target counter comprises: Acquire a plurality of working count values ​​corresponding to the application processor core and recorded by the target counter, wherein the plurality of working count values ​​include working count values ​​of a plurality of cycles corresponding to the application processor core; the length of each cycle is the target time period; The determining the load of the application processor core based on the working count value of the target counter comprises: Substituting the current operating frequency of the application processor core and a plurality of working count values ​​corresponding to the application processor core into a target formula to calculate the load of the application processor core; The target formula includes: Among them, load t represents the load of the application processor core, Δt represents the target time period, t represents the number of working count values, E i represents the count value of the i-th job, F i represents the current operating frequency of the application processor core in the i-th cycle, i=1,2…t, k represents a preset constant, and β represents a frequency modulation configuration parameter.

5. The method according to claim 4, characterized in that Before executing the hardware frequency adjustment process in response to the first adjustment instruction, the method further includes: In response to a configuration instruction carrying a target configuration value, configuring a value of a target register; The value of the target register is used to determine the frequency modulation configuration parameter.

6. The method according to claim 2, characterized in that The load threshold includes a plurality of load sub-thresholds, the plurality of load sub-thresholds constitute a plurality of frequency modulation intervals, the plurality of frequency modulation intervals define a plurality of frequency modulation intervals, and the plurality of frequency modulation intervals respectively correspond to a different frequency modulation strategy; The generating the frequency adjustment instruction based on the relationship between the load of the application processor core and the load threshold comprises: The frequency adjustment instruction is generated according to the relationship between the load of the application processor core and the multiple frequency modulation intervals and based on the frequency modulation strategy corresponding to the frequency modulation interval into which the load of the application processor core falls.

7. The method according to claim 6, characterized in that The operating frequency of the application processor core is divided into multiple operating frequency intervals, and the operating frequency of the multiple operating frequency intervals increases with the increase of the level; The multiple load sub-thresholds include a first load sub-threshold, a second load sub-threshold, a third load sub-threshold and a fourth load sub-threshold, and the values ​​of the first load sub-threshold, the fourth load sub-threshold, the third load sub-threshold and the second load sub-threshold are decreased in sequence; When the load of the application processor core is greater than the first load sub-threshold, the application processor core falls into a first frequency modulation interval, and the frequency modulation strategy corresponding to the first frequency modulation interval includes: setting the operating frequency of the application processor core within the highest level operating frequency interval; When the load of the application processor core is less than or equal to the first load sub-threshold and greater than the fourth load sub-threshold, the application processor core falls into a second frequency modulation interval. The frequency modulation strategy corresponding to the second frequency modulation interval includes: increasing the operating frequency of the application processor core by one level compared to the operating frequency interval in which the current operating frequency is located; The load of the application processor core is less than or equal to the fourth load sub-threshold, and falls into the third frequency modulation interval when it is greater than the third load sub-threshold. The frequency modulation strategy corresponding to the third frequency modulation interval includes: maintaining the operating frequency of the application processor core in the operating frequency interval where the current operating frequency is located; The load of the application processor core is less than or equal to the third load sub-threshold, and falls into a fourth frequency modulation interval when the load is greater than the second load sub-threshold. The frequency modulation strategy corresponding to the fourth frequency modulation interval includes: lowering the operating frequency of the application processor core by one level compared to the operating frequency interval in which the current operating frequency is located; When the load of the application processor core is less than or equal to the second load sub-threshold, it falls into the fifth frequency modulation interval, and the frequency modulation strategy corresponding to the fifth frequency modulation interval includes: setting the operating frequency of the application processor core within the lowest level operating frequency interval.

8. The method according to claim 1, characterized in that The frequency modulation mode parameter specifically includes: one of a hardware frequency modulation parameter, a software frequency modulation parameter and an automatic frequency modulation parameter; The configuring the frequency modulation mode based on the frequency modulation mode parameters comprises: when the frequency modulation mode parameters include the hardware frequency modulation parameters, entering the hardware frequency modulation mode, and generating the first adjustment instruction at predetermined intervals in the hardware frequency modulation mode; When the frequency modulation mode parameter includes a software frequency modulation parameter, entering a software frequency modulation mode, in which the operating frequency of the application processor core is adjusted in response to a second adjustment instruction carrying a target frequency, the second adjustment instruction being generated by the second processor; When the frequency modulation mode parameters include automatic frequency modulation parameters, switching between the hardware frequency modulation mode and the software frequency modulation mode is performed according to the operating parameters of the second processor.

9. A system on chip, characterized in that: include: A first processor, a second processor and a shared memory, wherein the second processor includes an application processor core, the application processor core is used to run an application program, the shared memory is used as a communication medium between the first processor and the second processor, and the first processor is configured as follows: In response to a target interrupt, read frequency modulation mode parameters from the shared memory, and configure a frequency modulation mode based on the frequency modulation mode parameters, the frequency modulation mode parameters being written into the shared memory by the second processor, the frequency modulation mode parameters comprising: hardware frequency modulation parameters, the target interrupt being triggered by the second processor when a communication channel between the second processor and the application processor core is idle; When the frequency modulation mode is the hardware frequency modulation mode corresponding to the hardware frequency modulation parameter, a hardware frequency modulation process is executed in response to the first adjustment instruction.

10. A computing device, characterized in that The invention comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the frequency control method according to any one of claims 1 to 8 when executing the computer program.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the frequency control method according to any one of claims 1 to 8 is implemented.

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