PWM signal processing method and device, electronic equipment and storage medium

Abstract

The invention provides a PWM signal processing method and device, electronic equipment and a storage medium, and the method comprises the steps: receiving a first PWM signal and a second PWM signal which are subjected to dead zone configuration, and determining a target mode corresponding to a level state composed of the two signals from at least one predefined mode, each mode represents a group of specific level state combinations; and then, based on a pre-configured output rule, determining an output mode corresponding to the target mode, and performing output processing on the first PWM signal and the second PWM signal according to the output mode. According to the invention, the abnormal pulse mode can be monitored and processed in real time.

Description

Technical Field

[0001] The present application relates to the field of signal processing, and in particular to a PWM signal processing method, device, electronic device and storage medium. Background Art

[0002] In modern electronic systems, the management and control of output pulses plays a vital role. Pulse width modulation (PWM) technology, as a common control method, is widely used in many fields such as motor drive, LED lighting adjustment, power management, etc. However, with the increase of system complexity, the mode management of output pulses faces many challenges.

[0003] Traditional output pulse management systems often rely on fixed program logic and preset parameter settings, lacking the ability to monitor pulse patterns in real time and detect anomalies. When the system is subject to external interference or internal failures, the output pulses may exhibit unexpected patterns, such as frequency anomalies, duty cycle distortion, etc. If these abnormal patterns are not discovered and handled in a timely manner, they may cause serious damage to the system and even lead to safety accidents.

[0004] To meet this challenge, the industry has begun to explore more intelligent and flexible output pulse management systems. These systems usually have real-time monitoring capabilities, which can continuously track the pattern of output pulses and trigger corresponding processing mechanisms when anomalies are detected. However, existing solutions still have shortcomings in anomaly detection accuracy, response speed, and system recovery capabilities after anomaly processing. Summary of the invention

[0005] In view of this, the embodiments of the present application provide a PWM signal processing method, device, electronic device and storage medium, which can monitor and process abnormal pulse patterns in real time.

[0006] The technical solution of the embodiment of the present application is implemented as follows:

[0007] In a first aspect, an embodiment of the present application provides a PWM signal processing method, the method comprising:

[0008] Receive a first PWM signal and a second PWM signal, and determine a target mode from at least one mode according to the first PWM signal and the second PWM signal; wherein the first PWM signal and the second PWM signal are PWM signals generated by a PWM generator and configured with a dead zone, and each mode in the at least one mode represents a set of level states composed of the first PWM signal and the second PWM signal, and the level states in different modes are different;

[0009] An output mode corresponding to the target mode is determined based on a preconfigured output rule, and the first PWM signal and the second PWM signal are output according to the output mode.

[0010] In a second aspect, an embodiment of the present application further provides a PWM signal processing device, the device comprising:

[0011] a mode detection module, configured to receive a first PWM signal and a second PWM signal, and determine a target mode from at least one mode according to the first PWM signal and the second PWM signal; wherein the first PWM signal and the second PWM signal are PWM signals generated by a PWM generator and configured with a dead zone, and each mode in the at least one mode represents a set of level states composed of the first PWM signal and the second PWM signal, and the level states in different modes are different;

[0012] The mode processing module is used to determine the output mode corresponding to the target mode based on a preconfigured output rule, and output the first PWM signal and the second PWM signal according to the output mode.

[0013] In a third aspect, an embodiment of the present application further provides an electronic device, comprising: a processor, a storage medium and a bus, wherein the storage medium stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor communicates with the storage medium via the bus, and the processor executes the machine-readable instructions to execute the PWM signal processing method described in any one of the first aspects.

[0014] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the PWM signal processing method described in any one of the first aspects is executed.

[0015] The embodiments of the present application have the following beneficial effects:

[0016] (1) Real-time monitoring and efficient response: The embodiments of the present application can continuously monitor the output pulse pattern and immediately trigger the preset processing mechanism once an unexpected pulse pattern is found. This real-time monitoring and efficient response capability ensures that the system can quickly identify and respond to potential anomalies, thereby effectively reducing the risk of system damage caused by abnormal patterns.

[0017] (2) Comprehensive exception recording and tracking: When an abnormal pattern is detected, the embodiment of the present application will not only automatically trigger the processing mechanism, but also record the status information of the abnormal pattern in detail, including the time when the abnormality occurred, the characteristics of the pulse pattern, etc. These detailed records provide developers with valuable abnormal information, helping them to quickly locate the problem and conduct in-depth analysis and resolution.

[0018] (3) Seamless automatic recovery function: When the abnormal mode is restored, the embodiment of the present application can automatically exit the abnormal mode processing state and seamlessly connect to subsequent work without manual intervention. This automatic recovery function ensures that the system can quickly return to normal working state after the abnormal processing is completed, avoiding problems such as system downtime or performance degradation caused by abnormal processing.

[0019] (4) Improve overall system performance and user experience: The embodiments of the present application significantly improve the stability and reliability of the output pulse management system. This not only enables the system to respond quickly and restore normal working conditions when faced with abnormal modes, but also reduces maintenance costs and downtime caused by system abnormalities. At the same time, the improvement of system stability and reliability also brings users a smoother and more stable user experience.

[0020] To sum up, the embodiments of the present application bring significant beneficial effects to the output pulse management system through innovative designs such as real-time monitoring, rapid response, abnormal recording and tracking, and automatic recovery functions, improve the stability and reliability of the system, and provide users with a better user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 It is a dead zone configuration schematic diagram in the prior art;

[0023] Figure 2 is a schematic diagram of the dead zone effect provided in an embodiment of the present application;

[0024] Figure 3 It is a flowchart of steps S101-S102 provided in an embodiment of the present application;

[0025] Figure 4 is a schematic diagram of a mode detection module provided in an embodiment of the present application;

[0026] Figure 5 is a schematic diagram of a mode processing module provided in an embodiment of the present application;

[0027] Figure 6 It is a schematic diagram of a mode counting and interrupt generation control module provided in an embodiment of the present application;

[0028] Figure 7 is a structural schematic diagram of a PWM signal processing device provided in an embodiment of the present application;

[0029] Figure 8 It is a schematic diagram of the composition structure of the electronic device provided in the embodiment of the present application. DETAILED DESCRIPTION

[0030] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of explanation and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn in real proportion. The flowchart used in this application shows the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowchart can be implemented out of sequence, and the steps without logical context can be reversed in order or implemented simultaneously. In addition, those skilled in the art can add one or more other operations to the flowchart under the guidance of the content of the present application, or remove one or more operations from the flowchart.

[0031] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0032] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0033] In the following description, the terms "first\second\third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0034] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0036] When implementing the embodiments of the present application, the applicant discovered that the prior art has the following problems:

[0037] PWM pulse width modulation technology is widely used in motor drive, power management, inverter, frequency converter and other applications. Usually, the terminals of the above devices are H-bridges or 3-phase bridges composed of high-power MOS tubes, IGBTs, etc. The voltage and current are controlled by controlling the switch of each bridge arm power tube.

[0038] See also Figure 1 , Figure 1 It is a dead zone configuration schematic diagram in the prior art, such as Figure 1 As shown in the figure, in some typical applications, one scenario that needs to be avoided is the situation where the upper and lower half bridges of the two bridge arms are turned on at the same time, otherwise a short circuit will occur and damage the system. Through the dead zone configuration, the PWM pulses (PWM_A1 and PWM_B1) can be inserted with a configurable delay (PWM_A and PWM_B) when flipping, thereby avoiding the situation of simultaneous conduction. The effect after using the dead zone configuration is as follows Figure 2 The dead zone effect schematic is shown in the figure, where the dotted line represents the inserted delay.

[0039] See also Figure 3 , Figure 3 is a flow chart of steps S101-S102 of the PWM signal processing method provided in the embodiment of the present application, which will be combined with Figure 3 Steps S101-S102 are shown for explanation.

[0040] In step S101, a first PWM signal and a second PWM signal are received, and a target mode is determined from at least one mode according to the first PWM signal and the second PWM signal; wherein the first PWM signal and the second PWM signal are PWM signals generated by a PWM generator and configured with a dead zone, and each mode in the at least one mode represents a group of level states composed of the first PWM signal and the second PWM signal, and the level states in different modes are different.

[0041] In step S102, an output mode corresponding to the target mode is determined based on a preconfigured output rule, and the first PWM signal and the second PWM signal are output according to the output mode.

[0042] Here, the two PWM signals are first received, and a target mode is determined from at least one predefined mode according to the received first PWM signal and the second PWM signal. These modes represent various possible level state combinations composed of the first PWM signal and the second PWM signal, and different modes correspond to different level state combinations.

[0043] The output rule depends on the application requirements. According to the determined output mode, the first PWM signal and the second PWM signal are output processed.

[0044] In some embodiments, the at least one mode includes a first mode, a second mode, a third mode and a fourth mode, wherein the first mode represents that the first PWM signal is at a low level and the second PWM signal is at a low level; the second mode represents that the first PWM signal is at a low level and the second PWM signal is at a high level; the third mode represents that the first PWM signal is at a high level and the second PWM signal is at a low level; the fourth mode represents that the first PWM signal is at a high level and the second PWM signal is at a high level;

[0045] The output rules are preconfigured as:

[0046] For the first PWM signal, directly output without processing in the first mode, output a low level in the second mode, output a high level in the third mode, and output a high impedance in the fourth mode;

[0047] For the second PWM signal, the signal is directly output without being processed in the first mode, a high level signal is output in the second mode, a low level signal is output in the third mode, and a high impedance signal is output in the fourth mode.

[0048] Here, the embodiment of the present application adopts pure combinational logic, which has a fast response time. For PWM_A (first PWM signal) and PWM_B (second PWM signal), four modes can be detected:

[0049] First mode: the first PWM signal is at a low level, and the second PWM signal is also at a low level.

[0050] Second mode: the first PWM signal is at a low level, and the second PWM signal is at a high level.

[0051] The third mode: the first PWM signal is at a high level, and the second PWM signal is at a low level.

[0052] Fourth mode: the first PWM signal is at a high level, and the second PWM signal is also at a high level.

[0053] These modes cover all possible level combinations of the first PWM signal and the second PWM signal. Figure 4 As shown, in actual detection, the four modes can be detected by the mode detection module.

[0054] For each PWM signal, the output rules are as follows:

[0055] For the first PWM signal:

[0056] The first mode: no processing is performed and the original low level state is directly output.

[0057] Second mode: Output low level regardless of its original state.

[0058] The third mode: outputs high level regardless of its original state.

[0059] The fourth mode: output high-impedance state (High-Z), which means that the signal neither drives a high level nor a low level, and is an off state or a high-impedance state of a tri-state gate.

[0060] For the second PWM signal:

[0061] The first mode: no processing is performed and the original low level state is directly output.

[0062] Second mode: output high level regardless of its original state.

[0063] The third mode: outputs low level regardless of its original state.

[0064] The fourth mode: outputs a high impedance state, which is the same as the processing of the first PWM signal in the fourth mode.

[0065] The above-mentioned output rules are only one application method in the embodiment of the present application. In actual applications, for each mode, the output rules of the first PWM signal / the second PWM signal can be flexibly adjusted among the above-mentioned four rules, and different modes are also allowed to output according to the same rules. In specific applications, flexible adjustments need to be made according to the actual application scenarios.

[0066] See also Figure 5 , Figure 5 is a schematic diagram of a mode processing module provided in an embodiment of the present application, such as Figure 5As shown, PWM_A and PWM_B are judged as the xth mode (x can be any one of the first / second / third / fourth modes) after mode judgment. According to the preset output rule (flexibly set), PWM_A outputs in one of the four output modes of direct output, output high level, output low level, and output high configuration. Similarly, PWM_B also outputs in one of the four output modes of direct output, output high level, output low level, and output high configuration. Finally, four results will be obtained according to the output results of PWM_A and PWM_B, namely 00, 01, 10 and 11.

[0067] In the above manner, in the first mode, both PWM signals maintain their original low level state without any processing. In the second mode and the third mode, the first PWM signal and the second PWM signal are forced to be set to a low level and a high level respectively, which can be used to ensure that only one signal is active under certain conditions. In the fourth mode, both PWM signals are set to a high impedance state, which can be used to disconnect any load or device connected to the two signals to avoid unnecessary power consumption or potential short circuits.

[0068] In some embodiments, the method further comprises:

[0069] Determine an output continuity mode; wherein the output continuity mode includes a single mode and a cyclic mode, wherein the single mode indicates that after determining the target mode, the output is continuously performed according to the corresponding output mode until the flag of the target mode is cleared; the cyclic mode indicates that when the current target mode is detected to have disappeared at the next target mode detection point, the output is switched to normal output, otherwise, the output is continuously performed according to the corresponding output mode;

[0070] The first PWM signal and the second PWM signal are outputted in the one-shot mode or the cyclic mode.

[0071] Here, the output continuous mode determines how the PWM signal will be continuously output after the target mode is determined. The embodiment of the present application provides two modes: a single mode and a cycle mode.

[0072] Single-shot mode: After determining the target mode, the system will continue to output PWM signals according to the corresponding output mode. This mode will continue until the target mode flag is cleared. The flag clearing can be triggered by an external event or determined by internal logic. Once the flag is cleared, the system will stop the output of the current mode and may return to the default state or wait for the next instruction.

[0073] Cyclic mode: After determining the target mode, the system will continue to output PWM signals according to the corresponding output mode. Unlike the single-shot mode, the cyclic mode checks whether the current target mode still exists at each target mode detection point. If it is detected that the current target mode has disappeared (for example, due to changes in the input signal), the system will switch back to the normal output state (which may mean the default output when no specific mode is applied). If it is detected that the current target mode still exists, the system will continue to output PWM signals according to the corresponding output mode.

[0074] After determining the output continuity mode, the system will output the first PWM signal and the second PWM signal according to the selected mode (single mode or cyclic mode). In the single mode, the output will continue until the flag is cleared. In the cyclic mode, the output will be dynamically adjusted according to the presence or absence of the target mode.

[0075] The one-shot mode is suitable for scenarios where a specific operation needs to be performed once, for example, the output mode of the PWM signal needs to be changed briefly when the motor starts. The cyclic mode is suitable for scenarios where input signal changes need to be continuously monitored and responded to, for example, the output of the PWM signal needs to be dynamically adjusted according to the load conditions during the operation of the motor.

[0076] In some embodiments, after determining the target mode according to the first PWM signal and the second PWM signal, the method further includes:

[0077] Determine whether the target mode satisfies an interrupt condition, and if so, generate an interrupt output signal and interrupt the output of the first PWM signal and the second PWM signal through the interrupt output signal; wherein, an interrupt function is enabled in any mode of the at least one mode, and the interrupt condition is met when the target mode matches a mode with an interrupt function enabled.

[0078] Here, once the target mode is determined according to the first PWM signal and the second PWM signal, the system will further check whether the target mode satisfies the interrupt condition.

[0079] An interrupt condition is one or more preset conditions used to determine whether the current target mode needs to trigger an interrupt. In this scenario, the interrupt condition is usually related to whether the target mode matches a mode that has the interrupt function enabled. If the target mode happens to be one of those modes that are set to trigger an interrupt, then the interrupt condition is considered to be met.

[0080] Once the interrupt condition is met, the system will immediately generate an interrupt output signal. This signal is a special signal used to notify other parts of the system (such as the CPU or interrupt service routine) that there is currently an interrupt event that needs to be processed. The generation of an interrupt output signal usually means that the current output of the PWM signal will be interrupted or paused immediately so that the system can turn to handle this interrupt event.

[0081] By interrupting the output signal, the system will interrupt or pause the current output of the first PWM signal and the second PWM signal. This means that before the interrupt is processed, the two PWM signals will not continue to be output in the previous mode. After the interrupt is processed, the system may resume the output of the PWM signal or adjust the output mode according to the new conditions.

[0082] The above method allows the system to respond quickly according to specific conditions and interrupt the output of the PWM signal when necessary to ensure the safety and efficiency of the system.

[0083] In some embodiments, the method further comprises:

[0084] Counting the pattern length of the target pattern; wherein each pattern in the at least one pattern is counted by an independent counter, each counter corresponds to a latch register, and the latch register is used to latch the count value;

[0085] The pattern length of the target pattern is determined based on the latch register, and is cleared when the target pattern disappears.

[0086] See also Figure 6 , Figure 6 is a schematic diagram of a mode counting and interrupt generation control module provided in an embodiment of the present application, such as Figure 6 As shown, here, for each of at least one pattern, a separate counter is provided for counting. The function of these counters is to record the length of time (usually expressed in the number of clock cycles) that each target pattern lasts from the beginning to the end. Each counter corresponds to a latch register, and the function of the latch register is to save the current count value of the counter when needed, which usually occurs at the end of the target pattern or when the system needs to read the current count value for further processing. When the system detects a target pattern, the corresponding counter starts counting. The counting is based on the system clock, so the count value directly reflects the length of time the target pattern lasts.

[0087] By reading the value in the latch register, the system can determine the pattern length of the target pattern. This length can be used for various purposes, such as fault detection, performance analysis, or optimizing control strategies. When the target pattern disappears (that is, the system detects a change in the pattern and the current target pattern is no longer valid), the corresponding counter will be cleared. This ensures that each counter only records the length of the current target pattern and is not affected by the previous pattern.

[0088] By monitoring the changes in pattern length, the system can detect potential faults or abnormal conditions. For example, if the length of a certain target pattern is abnormally long or short, this may indicate a problem with the system. Pattern length counts can be used to analyze the performance of the system. By comparing the changes in pattern length under different operating conditions, the system can optimize its control strategy to improve efficiency. In some applications, knowing the length of the target pattern can help the system adjust its control strategy. For example, in motor control, knowing the change in motor speed under different loads can help the system more accurately adjust the duty cycle of the PWM signal to optimize performance.

[0089] In some embodiments, the method further comprises:

[0090] When the counter overflows, an overflow flag is generated;

[0091] A pattern length of the target pattern is determined based on the overflow flag and the count of the counter.

[0092] Please continue to see Figure 6 , where the counter has a preset maximum count value (usually determined by the bit width of the counter). When the counter reaches this maximum value and continues to increase, it overflows, that is, the count value wraps around to 0 or some starting value. To indicate that this has occurred, the system sets an overflow flag. When the counter overflows, the overflow flag is set (that is, set to 1). This indicates that the current count value of the counter has exceeded its maximum range and has wrapped around. The system needs to consider the state of the overflow flag when determining the pattern length of the target pattern. If the overflow flag is set, it means that the count value of the counter has wrapped around, so the pattern length cannot be determined based on the current value of the counter alone. One approach is to check the overflow flag when reading the count value of the counter. If the overflow flag is set, the system needs to add one or more maximum count values ​​(depending on the number of overflows) to the current value of the counter to get the actual pattern length. Another approach is to use an additional register or counter to track the number of overflows. This additional counter is incremented by 1 on each overflow. Then, when determining the pattern length, the current value of the counter can be added to the number of overflows multiplied by the maximum count value.

[0093] In some embodiments, the method further comprises:

[0094] When the count value latched by the latch register is greater than or equal to a preset value and / or the count value of the counter is greater than or equal to a preset value, an interrupt output signal is generated and the output of the first PWM signal and the second PWM signal is interrupted by the interrupt output signal;

[0095] Send alarm instructions to the host computer.

[0096] Please continue to see Figure 6 , the system presets one or more thresholds to determine whether the count value latched by the latch register or the count value of the counter has reached the condition that requires triggering an interrupt. When the count value latched by the latch register is greater than or equal to the preset value, or the count value of the counter is greater than or equal to the preset value, the system considers that the interrupt condition is met. Once the interrupt condition is met, the system will immediately generate an interrupt output signal. This signal is used to notify other parts of the system (such as the CPU or interrupt service program) that there is an emergency event that needs to be handled. The generation of the interrupt output signal will cause the output of the first PWM signal and the second PWM signal to be immediately interrupted or paused to ensure that the system can turn to handle this emergency. In addition to generating an interrupt output signal, the system will also send an alarm instruction to the host computer. This instruction contains the specific reason for triggering the interrupt (such as the count value exceeds the preset value) and related status information. After receiving the alarm instruction, the host computer can take corresponding measures based on this information, such as displaying alarm information, recording logs, triggering other safety mechanisms, etc.

[0097] Based on the same inventive concept, an embodiment of the present application also provides a PWM signal processing device corresponding to the PWM signal processing method in the first embodiment. Since the principle of solving the problem by the device in the embodiment of the present application is similar to that of the above-mentioned PWM signal processing method, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be repeated.

[0098] like Figure 7 As shown, Figure 7 : is a schematic diagram of the structure of a PWM signal processing device 700 provided in an embodiment of the present application. The PWM signal processing device 700 includes:

[0099] A mode detection module 701 is used to receive a first PWM signal and a second PWM signal, and determine a target mode from at least one mode according to the first PWM signal and the second PWM signal; wherein the first PWM signal and the second PWM signal are PWM signals generated by a PWM generator and configured with a dead zone, and each mode in the at least one mode represents a set of level states composed of the first PWM signal and the second PWM signal, and the level states in different modes are different;

[0100] The mode processing module 702 is used to determine the output mode corresponding to the target mode based on a preconfigured output rule, and output the first PWM signal and the second PWM signal according to the output mode.

[0101] Those skilled in the art should understand that Figure 7 The implementation functions of each unit in the PWM signal processing device 700 shown can be understood by referring to the relevant description of the aforementioned PWM signal processing method. Figure 7 The functions of the various units in the PWM signal processing device 700 shown may be implemented by a program running on a processor, or may be implemented by a specific logic circuit.

[0102] In a possible implementation manner, the at least one mode includes a first mode, a second mode, a third mode and a fourth mode, wherein the first mode represents that the first PWM signal is at a low level and the second PWM signal is at a low level; the second mode represents that the first PWM signal is at a low level and the second PWM signal is at a high level; the third mode represents that the first PWM signal is at a high level and the second PWM signal is at a low level; the fourth mode represents that the first PWM signal is at a high level and the second PWM signal is at a high level;

[0103] The output rules are preconfigured as:

[0104] For the first PWM signal, directly output without processing in the first mode, output a low level in the second mode, output a high level in the third mode, and output a high impedance in the fourth mode;

[0105] For the second PWM signal, the signal is directly output without being processed in the first mode, a high level signal is output in the second mode, a low level signal is output in the third mode, and a high impedance signal is output in the fourth mode.

[0106] In a possible implementation, the mode processing module 702 further includes:

[0107] Determine an output continuity mode; wherein the output continuity mode includes a single mode and a cyclic mode, wherein the single mode indicates that after determining the target mode, the output is continuously performed according to the corresponding output mode until the flag of the target mode is cleared; the cyclic mode indicates that when the current target mode is detected to have disappeared at the next target mode detection point, the output is switched to normal output, otherwise, the output is continuously performed according to the corresponding output mode;

[0108] The first PWM signal and the second PWM signal are outputted in the one-shot mode or the cyclic mode.

[0109] In a possible implementation manner, the PWM signal processing device 700 further includes an interrupt generation module 703. After determining the target mode according to the first PWM signal and the second PWM signal, the interrupt generation module 703 further includes:

[0110] Determine whether the target mode satisfies an interrupt condition, and if so, generate an interrupt output signal and interrupt the output of the first PWM signal and the second PWM signal through the interrupt output signal; wherein, an interrupt function is enabled in any mode of the at least one mode, and the interrupt condition is met when the target mode matches a mode with an interrupt function enabled.

[0111] In a possible implementation, the PWM signal processing device 700 further includes a mode counting module 704, and the mode counting module 704 further includes:

[0112] Counting the pattern length of the target pattern; wherein each pattern in the at least one pattern is counted by an independent counter, each counter corresponds to a latch register, and the latch register is used to latch the count value;

[0113] The pattern length of the target pattern is determined based on the latch register, and is cleared when the target pattern disappears.

[0114] In a possible implementation, the pattern counting module 704 further includes:

[0115] When the counter overflows, an overflow flag is generated;

[0116] A pattern length of the target pattern is determined based on the overflow flag and the count of the counter.

[0117] In a possible implementation, the pattern counting module 704 further includes:

[0118] When the count value latched by the latch register is greater than or equal to a preset value and / or the count value of the counter is greater than or equal to a preset value, an interrupt output signal is generated and the output of the first PWM signal and the second PWM signal is interrupted by the interrupt output signal;

[0119] Send alarm instructions to the host computer.

[0120] The above PWM signal processing device has the following beneficial effects:

[0121] (1) Real-time monitoring and efficient response: The embodiments of the present application can continuously monitor the output pulse pattern and immediately trigger the preset processing mechanism once an unexpected pulse pattern is found. This real-time monitoring and efficient response capability ensures that the system can quickly identify and respond to potential anomalies, thereby effectively reducing the risk of system damage caused by abnormal patterns.

[0122] (2) Comprehensive exception recording and tracking: When an abnormal pattern is detected, the embodiment of the present application will not only automatically trigger the processing mechanism, but also record the status information of the abnormal pattern in detail, including the time when the abnormality occurred, the characteristics of the pulse pattern, etc. These detailed records provide developers with valuable abnormal information, helping them to quickly locate the problem and conduct in-depth analysis and resolution.

[0123] (3) Seamless automatic recovery function: When the abnormal mode is restored, the embodiment of the present application can automatically exit the abnormal mode processing state and seamlessly connect to subsequent work without manual intervention. This automatic recovery function ensures that the system can quickly return to normal working state after the abnormal processing is completed, avoiding problems such as system downtime or performance degradation caused by abnormal processing.

[0124] (4) Improve overall system performance and user experience: The embodiments of the present application significantly improve the stability and reliability of the output pulse management system. This not only enables the system to respond quickly and restore normal working conditions when faced with abnormal modes, but also reduces maintenance costs and downtime caused by system abnormalities. At the same time, the improvement of system stability and reliability also brings users a smoother and more stable user experience.

[0125] To sum up, the embodiments of the present application bring significant beneficial effects to the output pulse management system through innovative designs such as real-time monitoring, rapid response, abnormal recording and tracking, and automatic recovery functions, improve the stability and reliability of the system, and provide users with a better user experience.

[0126] like Figure 8 As shown, Figure 8 The present invention provides a schematic diagram of the structure of an electronic device 800 according to an embodiment of the present invention. The electronic device 800 includes:

[0127] A processor 801, a storage medium 802 and a bus 803, wherein the storage medium 802 stores machine-readable instructions executable by the processor 801. When the electronic device 800 is running, the processor 801 communicates with the storage medium 802 via the bus 803, and the processor 801 executes the machine-readable instructions to perform the steps of the PWM signal processing method described in the embodiment of the present application.

[0128] In actual application, the components in the electronic device 800 are coupled together via bus 803. It is understood that bus 803 is used to realize the connection and communication between these components. Bus 803 includes not only a data bus, but also a power bus, a control bus and a status signal bus. However, for the sake of clarity, Figure 8 Various buses are labeled as bus 803.

[0129] The above electronic device has the following beneficial effects:

[0130] (1) Real-time monitoring and efficient response: The embodiments of the present application can continuously monitor the output pulse pattern and immediately trigger the preset processing mechanism once an unexpected pulse pattern is found. This real-time monitoring and efficient response capability ensures that the system can quickly identify and respond to potential anomalies, thereby effectively reducing the risk of system damage caused by abnormal patterns.

[0131] (2) Comprehensive exception recording and tracking: When an abnormal pattern is detected, the embodiment of the present application will not only automatically trigger the processing mechanism, but also record the status information of the abnormal pattern in detail, including the time when the abnormality occurred, the characteristics of the pulse pattern, etc. These detailed records provide developers with valuable abnormal information, helping them to quickly locate the problem and conduct in-depth analysis and resolution.

[0132] (3) Seamless automatic recovery function: When the abnormal mode is restored, the embodiment of the present application can automatically exit the abnormal mode processing state and seamlessly connect to subsequent work without manual intervention. This automatic recovery function ensures that the system can quickly return to normal working state after the abnormal processing is completed, avoiding problems such as system downtime or performance degradation caused by abnormal processing.

[0133] (4) Improve overall system performance and user experience: The embodiments of the present application significantly improve the stability and reliability of the output pulse management system. This not only enables the system to respond quickly and restore normal working conditions when faced with abnormal modes, but also reduces maintenance costs and downtime caused by system abnormalities. At the same time, the improvement of system stability and reliability also brings users a smoother and more stable user experience.

[0134] To sum up, the embodiments of the present application bring significant beneficial effects to the output pulse management system through innovative designs such as real-time monitoring, rapid response, abnormal recording and tracking, and automatic recovery functions, improve the stability and reliability of the system, and provide users with a better user experience.

[0135] The embodiment of the present application further provides a computer-readable storage medium, which stores executable instructions. When the executable instructions are executed by at least one processor 801, the PWM signal processing method described in the embodiment of the present application is implemented.

[0136] In some embodiments, the storage medium can be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface storage, an optical disk, or a compact disc read-only memory (CDROM); it can also be various devices including one or any combination of the above memories.

[0137] In some embodiments, executable instructions may be in the form of a program, software, software module, script or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine or other unit suitable for use in a computing environment.

[0138] As an example, executable instructions may, but do not necessarily, correspond to a file in a file system, may be stored as part of a file that stores other programs or data, for example, in one or more scripts in a HyperText Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple coordinated files (for example, files storing one or more modules, subroutines, or code portions).

[0139] By way of example, executable instructions may be deployed to be executed on one computing device, or on multiple computing devices located at one site, or on multiple computing devices distributed across multiple sites and interconnected by a communication network.

[0140] The computer-readable storage medium has the following advantages:

[0141] (1) Real-time monitoring and efficient response: The embodiments of the present application can continuously monitor the output pulse pattern and immediately trigger the preset processing mechanism once an unexpected pulse pattern is found. This real-time monitoring and efficient response capability ensures that the system can quickly identify and respond to potential anomalies, thereby effectively reducing the risk of system damage caused by abnormal patterns.

[0142] (2) Comprehensive exception recording and tracking: When an abnormal pattern is detected, the embodiment of the present application will not only automatically trigger the processing mechanism, but also record the status information of the abnormal pattern in detail, including the time when the abnormality occurred, the characteristics of the pulse pattern, etc. These detailed records provide developers with valuable abnormal information, helping them to quickly locate the problem and conduct in-depth analysis and resolution.

[0143] (3) Seamless automatic recovery function: When the abnormal mode is restored, the embodiment of the present application can automatically exit the abnormal mode processing state and seamlessly connect to subsequent work without manual intervention. This automatic recovery function ensures that the system can quickly return to normal working state after the abnormal processing is completed, avoiding problems such as system downtime or performance degradation caused by abnormal processing.

[0144] (4) Improve overall system performance and user experience: The embodiments of the present application significantly improve the stability and reliability of the output pulse management system. This not only enables the system to respond quickly and restore normal working conditions when faced with abnormal modes, but also reduces maintenance costs and downtime caused by system abnormalities. At the same time, the improvement of system stability and reliability also brings users a smoother and more stable user experience.

[0145] To sum up, the embodiments of the present application bring significant beneficial effects to the output pulse management system through innovative designs such as real-time monitoring, rapid response, abnormal recording and tracking, and automatic recovery functions, improve the stability and reliability of the system, and provide users with a better user experience.

[0146] In the several embodiments provided in the present application, it should be understood that the disclosed methods and electronic devices can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0147] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0148] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0149] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a platform server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard drives, ROM, RAM, magnetic disks, or optical disks.

[0150] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A PWM signal processing method, characterized in that: The method comprises: Receive a first PWM signal and a second PWM signal, and determine a target mode from at least one mode according to the first PWM signal and the second PWM signal; wherein the first PWM signal and the second PWM signal are PWM signals generated by a PWM generator and configured with a dead zone, and each mode in the at least one mode represents a set of level states composed of the first PWM signal and the second PWM signal, and the level states in different modes are different; An output mode corresponding to the target mode is determined based on a preconfigured output rule, and the first PWM signal and the second PWM signal are output according to the output mode.

2. The method according to claim 1, characterized in that The at least one mode includes a first mode, a second mode, a third mode and a fourth mode, wherein the first mode represents that the first PWM signal is at a low level and the second PWM signal is at a low level; the second mode represents that the first PWM signal is at a low level and the second PWM signal is at a high level; the third mode represents that the first PWM signal is at a high level and the second PWM signal is at a low level; the fourth mode represents that the first PWM signal is at a high level and the second PWM signal is at a high level; The output rules are preconfigured as: For the first PWM signal, directly output without processing in the first mode, output a low level in the second mode, output a high level in the third mode, and output a high impedance in the fourth mode; For the second PWM signal, the signal is directly output without being processed in the first mode, a high level signal is output in the second mode, a low level signal is output in the third mode, and a high impedance signal is output in the fourth mode.

3. The method according to claim 1, characterized in that The method further comprises: Determine an output continuity mode; wherein the output continuity mode includes a single mode and a cyclic mode, wherein the single mode indicates that after determining the target mode, the output is continuously performed according to the corresponding output mode until the flag of the target mode is cleared; the cyclic mode indicates that when the current target mode is detected to have disappeared at the next target mode detection point, the output is switched to normal output, otherwise, the output is continuously performed according to the corresponding output mode; The first PWM signal and the second PWM signal are outputted in the one-shot mode or the cyclic mode.

4. The method according to claim 1, characterized in that: After determining the target mode according to the first PWM signal and the second PWM signal, the method further includes: Determine whether the target mode satisfies an interrupt condition, and if so, generate an interrupt output signal and interrupt the output of the first PWM signal and the second PWM signal through the interrupt output signal; wherein, an interrupt function is enabled in any mode of the at least one mode, and the interrupt condition is met when the target mode matches a mode with an interrupt function enabled.

5. The method according to claim 1, characterized in that The method further comprises: Counting the pattern length of the target pattern; wherein each pattern in the at least one pattern is counted by an independent counter, each counter corresponds to a latch register, and the latch register is used to latch the count value; The pattern length of the target pattern is determined based on the latch register, and is cleared when the target pattern disappears.

6. The method according to claim 5, characterized in that The method further comprises: When the counter overflows, an overflow flag is generated; A pattern length of the target pattern is determined based on the overflow flag and the count of the counter.

7. The method according to claim 5, characterized in that The method further comprises: When the count value latched by the latch register is greater than or equal to a preset value and / or the count value of the counter is greater than or equal to a preset value, an interrupt output signal is generated and the output of the first PWM signal and the second PWM signal is interrupted by the interrupt output signal; Send alarm instructions to the host computer.

8. A PWM signal processing device, characterized in that: The device comprises: a mode detection module, configured to receive a first PWM signal and a second PWM signal, and determine a target mode from at least one mode according to the first PWM signal and the second PWM signal; wherein the first PWM signal and the second PWM signal are PWM signals generated by a PWM generator and configured with a dead zone, and each mode in the at least one mode represents a set of level states composed of the first PWM signal and the second PWM signal, and the level states in different modes are different; The mode processing module is used to determine the output mode corresponding to the target mode based on a preconfigured output rule, and output the first PWM signal and the second PWM signal according to the output mode.

9. An electronic device, characterized in that: include: A processor, a storage medium and a bus, wherein the storage medium stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor communicates with the storage medium via the bus, and the processor executes the machine-readable instructions to perform the PWM signal processing method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the PWM signal processing method according to any one of claims 1 to 7 is executed.

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