SEM image-based field effect transistor device structure critical dimension detection method

Abstract

The invention relates to the technical field of image processing, in particular to a field-effect transistor device structure key size detection method based on an SEM image, and the method comprises the steps: obtaining an SEM image of a field-effect transistor, and carrying out the preprocessing of the SEM image; extracting a grid contour in the SEM image by adopting a neural network; and calculating the offset of the field effect transistor device structure by using the grid contour and a preset layout contour. The invention aims to avoid defects generated when time and manpower are consumed to detect, adjust and align a semiconductor gate structure in the MOSFET structure design process, and the overall quality of an MOSFET semiconductor device is improved.

Description

Technical Field

[0001] The present application relates to the field of image processing technology, and in particular to a method for detecting key dimensions of a field effect transistor device structure based on a SEM image. Background Art

[0002] In the field of semiconductor device manufacturing, metal oxide semiconductor field effect transistor (MOSFET) is an important semiconductor device, and its performance and quality directly affect the performance of electronic equipment. With the development of science and technology, silicon-based silicon carbide (SiC) materials are widely used in the manufacture of high-performance MOSFET devices due to their superior physical and chemical properties. In the manufacturing process, precise control and measurement of the structural dimensions of MOSFET devices, especially the dimensions of the gate structure, are the key to ensuring device performance and quality. In the field of image processing, scanning electron microscope (SEM) is a commonly used imaging device that can provide high-resolution images, allowing researchers to observe details at the micron or even nanometer level. In the field of precision measurement, the size and shape information of the target object can be quickly and accurately obtained by processing and analyzing SEM images through intelligent analysis algorithms.

[0003] Existing technologies usually use manual methods to observe and analyze SEM images, and then compare the SEM images with the preset MOSFET structure layout outline to determine whether the two are aligned and whether adjustments are needed. Although this method can achieve the purpose, it takes a lot of time and manpower, and is easily affected by human factors, resulting in low accuracy and repeatability of the test results.

[0004] In addition, due to the special properties of SiC materials, it has high requirements for environmental factors such as temperature and pressure during the manufacturing process. Therefore, it is necessary to more accurately control and measure the structural dimensions of MOSFET devices to ensure the performance and quality of the devices. Summary of the invention

[0005] In order to solve the above technical problems, the present application provides a method for detecting key dimensions of a field effect transistor device structure based on SEM images to solve the existing problems.

[0006] The method for detecting key dimensions of field effect transistor device structures based on SEM images of the present application adopts the following technical solutions:

[0007] An embodiment of the present application provides a method for detecting key dimensions of a field effect transistor device structure based on a SEM image, the method comprising the following steps:

[0008] Obtain SEM images of field effect transistors and perform preprocessing;

[0009] A neural network is used to extract the gate contour in the SEM image;

[0010] The offset of the field effect transistor device structure is calculated using the gate contour and the preset layout contour.

[0011] Preferably, the preprocessing includes denoising and grayscale adjustment operations.

[0012] Preferably, the denoising method adopts median filtering technology.

[0013] Preferably, the grayscale adjustment method adopts linear stretching technology.

[0014] Preferably, before using a neural network to extract the gate contour in the SEM image, a data set consisting of a plurality of SEM images with annotated gate contours is prepared for training the neural network model.

[0015] Preferably, the neural network adopts a convolutional neural network.

[0016] Preferably, the preset layout outline is a layout outline of a standard metal oxide semiconductor field effect transistor gate structure.

[0017] Preferably, the offset is determined by a difference between a gate contour and a preset layout contour.

[0018] Preferably, after the offset is calculated, the method further includes adjusting the critical dimensions of the field effect transistor device structure using the offset.

[0019] Preferably, the critical dimension is further determined as a dimension of a gate structure.

[0020] This application has at least the following beneficial effects:

[0021] 1. This application automatically obtains the gate contour in the SEM image through a neural network, and calculates the offset between the SEM image and the preset MOSFET gate structure layout contour in real time, which greatly reduces the need for manual intervention, improves work efficiency, and saves time and labor costs.

[0022] 2. This application uses neural networks for image processing and analysis, avoiding the influence of human factors, thereby improving the accuracy and repeatability of the detection results.

[0023] 3. This application can accurately control and measure the structural dimensions of MOSFET devices, especially the dimensions of the gate structure, which meets the demand for high-precision measurement in the SiC material manufacturing process and helps to improve the overall quality of MOSFET semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions and advantages in the embodiments of the present application or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 A flow chart of a method for detecting critical dimensions of a field effect transistor device structure based on SEM images provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to further explain the technical means and effects adopted by the present application to achieve the predetermined invention purpose, the following is a detailed description of the method for detecting the key dimensions of the field effect tube device structure based on the SEM image proposed in the present application, its specific implementation method, structure, features and effects, in combination with the accompanying drawings and preferred embodiments. In the following description, different "one embodiment" or "another embodiment" does not necessarily refer to the same embodiment. In addition, specific features, structures or characteristics in one or more embodiments may be combined in any suitable form.

[0027] Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

[0028] The specific scheme of the method for detecting key dimensions of field effect transistor device structures based on SEM images provided by the present application is described in detail below in conjunction with the accompanying drawings.

[0029] An embodiment of the present application provides a method for detecting critical dimensions of a field effect transistor device structure based on SEM images.

[0030] Specifically, the following method for detecting the key dimensions of field effect transistor structures based on SEM images is provided. Figure 1 , the method comprises the following steps:

[0031] Step 1: Obtain the SEM image of the field effect tube and perform preprocessing.

[0032] A scanning electron microscope (SEM) is used to obtain a SEM image of a metal oxide semiconductor field effect transistor (MOSFET) after the nth scan.

[0033] In this embodiment, the SEM model is JSM-7800F, the acceleration voltage is 15 kV, the working distance is 8 mm, and the size of the acquired SEM image is 1024x1024 pixels.

[0034] Next, the acquired SEM images are preprocessed, including denoising and grayscale adjustment operations, to facilitate subsequent intelligent analysis.

[0035] In this embodiment, the median filtering technique is used to remove noise from the acquired SEM image, and the linear stretching method is used to adjust the grayscale of the acquired SEM image. In other embodiments, the Gaussian filtering technique and the histogram equalization method can be used to implement the denoising and grayscale adjustment operations of the SEM image.

[0036] At this point, the pre-processed SEM image can be obtained by the above method.

[0037] Step 2: Use neural network to extract the gate outline in the SEM image.

[0038] Deep learning algorithms, especially convolutional neural networks (CNNs), are used to quickly extract gate contours from SEM images.

[0039] In this embodiment, a data set including a large number of SEM images with gate contours annotated is first prepared for training a neural network model.

[0040] Then, the neural network model is trained using the PyTorch framework and the Adam optimizer.

[0041] During the training process, the batch size (Batch Size) is set to 32, the learning rate (Learning Rate) is set to 0.001, and the number of training rounds (Epochs) is set to 50.

[0042] Among them, convolutional neural networks and their training process are well-known technologies and will not be described in detail.

[0043] At this point, the gate contour in the SEM image can be extracted by the above method.

[0044] Step 3: Calculate the offset of the field effect transistor device structure using the gate contour and the preset layout contour.

[0045] The gate contour extracted in step 2 is compared with the preset layout contour, and the difference between the two is calculated to obtain the offset of the field effect transistor device structure. The preset layout contour is the layout contour of the standard metal oxide semiconductor field effect transistor (MOSFET) gate structure.

[0046] It should be understood that, in this embodiment, the distance between the gate contour and the preset layout contour quality inspection is calculated as the difference between the two, and the distance adopts the Euclidean distance.

[0047] In this embodiment, the preset layout outline is designed by CAD software and has a size of 1000x1000 pixels.

[0048] Step 4: Use the offset to adjust the critical dimensions of the field effect transistor device structure.

[0049] According to the offset calculated in step three, the size of the MOSFET device structure is adjusted, especially the size of the gate structure.

[0050] This can be achieved by adjusting process parameters during the manufacturing process, such as temperature, pressure, etc. In this embodiment, the temperature is set to 200° C. and the pressure is set to 10 MPa.

[0051] The various embodiments in the present application are described in a progressive manner, and the same or similar parts between the various embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0052] It should be noted that, unless otherwise specified and limited, terms such as "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a circuit structure, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such article or device. In the absence of further restrictions, an element defined by the sentence "including one..." does not exclude the existence of other identical elements in the article or device including the element. In addition, the term "and\or" used herein includes any and all combinations of one or more related listed items.

[0053] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention herein. The present application is intended to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include common knowledge or customary technical means in the art that are not invented by the present application.

[0054] It should be understood that the present application is not limited to the exact construction that has been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof.

Claims

1. A method for detecting key dimensions of field effect tube device structures based on SEM images, characterized in that: The method comprises the following steps: Obtain SEM images of field effect transistors and perform preprocessing; A neural network is used to extract the gate contour in the SEM image; The offset of the field effect transistor device structure is calculated using the gate contour and the preset layout contour.

2. The method for detecting critical dimensions of a field effect transistor device structure based on SEM images according to claim 1, characterized in that: The preprocessing includes denoising and grayscale adjustment operations.

3. The method for detecting critical dimensions of a field effect transistor device structure based on SEM images according to claim 2, characterized in that: The denoising method adopts median filtering technology.

4. The method for detecting critical dimensions of a field effect transistor device structure based on SEM images according to claim 2, characterized in that: The grayscale adjustment method adopts linear stretching technology.

5. The method for detecting critical dimensions of a field effect transistor device structure based on SEM images according to claim 1, characterized in that: Before using a neural network to extract the gate contour in the SEM image, a data set consisting of several SEM images with annotated gate contours is prepared for training the neural network model.

6. The method for detecting critical dimensions of a field effect transistor device structure based on SEM images according to claim 5, characterized in that: The neural network adopts a convolutional neural network.

7. The method for detecting critical dimensions of a field effect transistor structure based on SEM images according to claim 1, characterized in that: The preset layout outline is a layout outline of a standard metal oxide semiconductor field effect transistor gate structure.

8. The method for detecting critical dimensions of a field effect transistor structure based on SEM images according to claim 7, characterized in that: The offset is determined by the difference between the gate contour and a preset layout contour.

9. The method for detecting critical dimensions of a field effect transistor device structure based on SEM images according to claim 1, characterized in that: After the offset is calculated, the method further includes adjusting the critical dimensions of the field effect transistor device structure using the offset.

10. The method for detecting critical dimensions of a field effect transistor device structure based on SEM images according to claim 9, characterized in that: The critical dimension is further determined as the dimension of the gate structure.

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