Cavity filling process for glass panel level embedded packaging

Abstract

The invention discloses a cavity filling process for glass panel level embedded packaging, and belongs to the field of semiconductor devices. The process comprises the following steps: manufacturing a glass cavity mask pattern through a photoetching process; performing wet etching by using a hydrofluoric acid solution to manufacture a glass cavity; bonding a chip bonding film at the bottom of the chip; picking up the chip and placing the chip in the glass cavity; and dielectric lamination and curing. After the cavity is filled through the process, the surface flatness of the dielectric layer is good, the fine-pitch RDL layer can be continuously manufactured on the dielectric layer without a further fly cutting or surface leveling process, and the process has practical value.

Description

Technical Field

[0001] The invention relates to an embedded packaging technology, in particular to a blind cavity filling process of glass panel-level embedded packaging, and belongs to the field of semiconductor devices. Background Art

[0002] As Moore's Law slows down, the demand for high performance at low power and low cost for consumer electronics is driving the development of heterogeneous integrated advanced packaging. Power efficiency, high I / O density, and miniaturization drive heterogeneous integration in digital applications to achieve logic-memory integration. However, the target carrier frequency of RF modules for next-generation radar and terahertz applications is as high as 140 GHz, which requires low-loss materials and robust low-parasitic packaging architectures to enable the integration of antennas and components.

[0003] Wafer-level fan-out (WLFO) packaging achieves exceptional power and signal performance with its ability to scale to very fine I / O pitches. Although WLFO was originally designed to fan out the I / O on a chip to a larger package area, the scope of WLFO technology has expanded significantly in recent years to include multi-chip system-in-package (SiP) modules for high-density digital applications, as well as for low-parasitic high-frequency applications. However, most current WLFO packaging technologies use epoxy mold compounds (EMC) as fan-out substrates. However, such WLFO packages are fundamentally limited in supporting future heterogeneous integration needs due to the following reasons: (1) chemical shrinkage of the EMC causes large chip offsets; (2) it is very difficult to arrange high-density redistribution layers (RDLs) on the molding compound due to warpage caused by the mismatch between the coefficient of thermal expansion (CTE) of the molding material and silicon; and (3) vias in the EMC cause losses, and it is difficult to achieve high-yield fine-pitch via structures through the EMC. These reasons limit the expansion of WLFO in the digital and RF fields. Large chip offsets need to be compensated by relaxing the pad spacing, which limits the I / O density, and larger pads and non-center blind vias affect signal integrity at higher frequencies. Chip offset is also an important factor limiting the potential of WLFO packaging. The EMC surface itself is relatively rough, which affects the ability to route fine pitches at higher densities and increases signal losses at high frequencies where the skin effect is severe. The liquid EMC in the current WLFO technology is formed by compression molding, which leads to uneven distribution of EMC particles and makes the sidewalls of fine pitch through holes rough. For these reasons, the current WLFO technology is difficult to use for large-size (>40×40 mm) SiP modules.

[0004] Glass is used as a carrier for chip embedding, which is not only superior to organic carriers, but also has many unique advantages over existing WLFO. The smooth surface and high dimensional stability of glass enable high-density silicon-like RDL wiring and back-end I / O on large panels, thereby improving productivity and reducing costs, which is not possible in fan-out packaging based on molding compounds. The thermal expansion coefficient of glass can be customized, thereby improving reliability and enabling it to be directly surface-mounted to the substrate, unlike some high-density fan-out packages that need to be connected to the substrate through organic packaging. Compared with molding compounds, the loss factor of glass is about 2-3 times lower, making glass panel embedded (GPE) packaging an ideal choice for high-speed and high-frequency applications. Compared with molding compounds, glass also has the advantages of high resistivity, excellent moisture resistance and high surface smoothness.

[0005] When making a glass panel embedded packaging structure, the surface flatness of the dielectric layer after curing is very important. RDL cannot be made on the surface of a dielectric layer with poor flatness. Since the cavity size is usually slightly larger than the chip, there is a gap between the chip and the cavity after the chip is embedded in the glass cavity, and the gap causes the surface to be uneven after the dielectric is filled. For GPE, the accuracy of the glass cavity directly affects the alignment accuracy between the chip and the package, thereby affecting the minimum wiring accuracy and density of the RDL layer. GPE is usually divided into through-cavity GPE and blind-cavity GPE structures. The advantage of blind-cavity GPE is that the cost is relatively low. The mask plate is made by photolithography. After the mask plate is bonded to the glass substrate, the HF etching process can be used to etch multiple samples at one time to form multiple glass cavities. Therefore, the size and morphology of the glass cavity are more uniform. The use of the mask plate makes the calibration accuracy of the blind cavity better, and the distance between cavities and the position accuracy of the cavity are higher, but the disadvantage is that the slope of the cavity sidewall is large and there is an inclination angle. The through-type glass cavity formed by the process of combining laser cutting with mechanical cutting has vertical side walls, and the through-type cavity obtained by laser cutting is more accurate in size. Although the glass cavity formed by the through-type GPE and blind-type GPE structures have their own advantages, the dielectric formed after filling the dielectric has a depression, and it is usually necessary to flatten the panel surface after filling the dielectric. For example, the literature "First Demonstration of Panel Glass Fan-out (GFO) Packages for High I / O Density and High Frequency Multi-Chip Integration" and "2.5D glass panel embedded (GPE) packages with better I / O density, performance, cost and reliability than current silicon interposers and high-density fan-out packages" both use a surface flattening instrument to flatten the panel surface after the dielectric layer is cured to avoid non-coplanarity that may be caused by polymer filling the cavity. However, flattening the panel surface increases the steps and cost of the glass panel embedded packaging process, which is not conducive to the promotion and application of GPE technology.

[0006] Therefore, how to optimize the cavity filling conditions of glass panel-level embedded packaging to obtain a flat panel surface and reduce the non-coplanarity caused by the filling process is a problem that needs to be solved urgently. Summary of the invention

[0007] The object of the present invention is to address the deficiencies of the above-mentioned background technology and provide a method for filling a glass cavity. By optimizing the cavity filling conditions of glass panel-level embedded packaging, especially optimizing the process parameters and methods of the laminated dielectric layer, the technical problem of non-coplanarity of the panel caused by polymer filling the cavity is solved, and the purpose of the invention is to improve the surface flatness of the glass cavity after the dielectric material is filled.

[0008] The present invention adopts the following technical solutions to achieve the above-mentioned invention object: A cavity filling process for glass panel level embedded packaging, the process comprising the following steps: Step 1, laminating a photoresist dry film on a glass substrate, and manufacturing a glass cavity mask pattern by a photolithography process; Step 2, using a hydrofluoric acid solution to etch the glass substrate with the glass cavity mask pattern formed in step 1 to form a glass cavity; Step 3, bonding the chip bonding film to the bottom of the chip, and then picking up the chip with the chip bonding film and placing it in the glass cavity formed in step 2; Step 4, heating the glass substrate processed in step 3. Adhere the chip to the glass cavity; Step 5: Laminating the same number of layers of dielectric material onto the upper and lower sides of the glass panel processed in step 4 and curing.

[0009] As a further optimization solution for the cavity filling process of glass panel level embedded packaging, the glass panel in step one has a through-glass hole.

[0010] As a further optimization solution for the cavity filling process of glass panel-level embedded packaging, the glass cavity formed in step 2 is 7.7×7.7mm in area. 2 , a glass blind cavity with a depth of 110μm; the embedded chip size is 7.2 × 7.2mm 2 , height is 100μm.

[0011] As a further optimization solution for the cavity filling process of glass panel-level embedded packaging, the chip bonding film used in step three has a thickness of 10 μm.

[0012] As a further optimization scheme for the cavity filling process of glass panel-level embedded packaging, in step three, a chip pick and place instrument is used to place the chip with the chip bonding film in the glass cavity formed in step two; when the chip is placed in the glass blind cavity, the instrument applies a pressure of 1 MPa and a temperature of 150°C to the chip for 5 seconds.

[0013] As a further optimization solution for the cavity filling process of glass panel-level embedded packaging, step four heats the chip bonding film at 130° C. for 4 hours to solidify the DAF.

[0014] As a further optimization scheme for the cavity filling process of glass panel-level embedded packaging, in step five, the same number of layers of dielectric material are attached to the upper and lower sides of the glass panel. The number of layers of dielectric material depends on the required dielectric layer thickness. The glass panel with the dielectric material attached is then placed in a vacuum laminator for two laminations. After the two-step lamination is completed, curing is performed to allow the adhesive film to fill the TGV and the cavity and form a flat adhesive film surface.

[0015] As a further optimization scheme for the cavity filling process of glass panel-level embedded packaging, the two-step lamination method in step five includes the following steps: step one, using rubber as a lamination gasket, vacuuming for 90 seconds, and then laminating, the lamination temperature is 100°C, the lamination pressure is 0.7MPa, and the lamination time is 60s; step two, using a silicon wafer as a lamination gasket, vacuuming for 90 seconds, and then laminating, the lamination temperature is 100°C, the lamination pressure is 0.7Mpa, and the lamination time is 180s.

[0016] The present invention adopts the above technical solution and has the following beneficial effects: (1) Compared with the traditional glass cavity filling process method, the flatness of the glass space after filling the polymer is improved by optimizing the process parameters and methods of the laminated dielectric layer. The dielectric layer attached to the upper and lower surfaces of the glass substrate is laminated by a two-step lamination method. The optimization of the process parameters of the laminated dielectric layer specifically includes the selection of the lamination substrate, lamination temperature and lamination time. At the same time, the silicon wafer is used as the lamination pad during the second lamination, which improves the lamination flatness. The present invention reduces the non-coplanarity of the dielectric material on the panel surface from 40μm in the traditional method to less than 5μm after the dielectric is cured. Since the dielectric sag on the panel surface is small and has good flatness, a fine pitch RDL layer can be continuously produced on the dielectric layer without further fly cutting or surface flattening process, which simplifies the process steps and reduces the process cost.

[0017] (2) Compared with the molding compounds used in wafer-level fan-out packaging, dielectric materials can provide smooth sidewalls for fine-pitch copper interconnects, reducing signal loss at high frequencies where the skin effect is severe, and improving the electrical performance of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a structural diagram of a glass substrate for making a glass cavity pattern through a photolithography process according to the process proposed by the present invention.

[0019] Figure 2This is a structural diagram of a glass substrate after forming a glass blind cavity through wet etching and removing the photoresist according to the process of the present invention.

[0020] Figure 3 This is a structural diagram of a chip after laminating the chip to the chip bonding film according to the process of the present invention.

[0021] Figure 4 This is a structural diagram of a glass substrate after the chip is adhered to the glass cavity according to the process of the present invention.

[0022] Figure 5 This is a structural diagram of a glass substrate after a layer of ABF is attached to both sides of the glass panel according to the process of the present invention.

[0023] Figure 6 This is a structural diagram of a glass substrate after two layers of ABF are attached to both sides of the glass panel according to the process of the present invention.

[0024] Figure 7 Figure 2 is a structural diagram of a glass substrate after ABF is laminated and cured by a conventional method.

[0025] Figure 8 This is a structural diagram of a glass substrate after ABF is laminated and cured according to the present invention.

[0026] Fig. 9 The present invention is a flow chart of the process.

[0027] Explanation of the numbers in the figure: 1. photoresist, 2. glass substrate with through-glass hole, 3. chip, 4. chip bonding film, 5. dielectric material, 6. recess, 7. glass substrate with glass cavity. DETAILED DESCRIPTION

[0028] The technical solution of the invention is described in detail below with reference to the accompanying drawings.

[0029] The present invention proposes a cavity filling process for glass panel level embedded packaging. Fig. 9 As shown, first, a glass cavity is formed by photolithography and hydrofluoric acid solution etching; then, a die attach film is bonded to the bottom of the chip, and the chip with the die attach film is placed in the cavity by a pick and place instrument and the die attach film is cured; finally, a dielectric is laminated by a two-step lamination method and then cured to completely fill the glass through hole and the cavity with the dielectric, and to form a dielectric surface with high flatness and small depressions.

[0030] The cavity filling process of a glass panel-level embedded package proposed in the present invention can realize electrolyte filling of both the through-glass cavity and the blind-glass cavity. The following is an example of the technical solution proposed in the present invention using the glass blind-cavity electrolyte filling process as an example. The blind-cavity filling process of the glass panel-level embedded package includes the following five steps.

[0031] Step 1: Make the glass cavity mask pattern through photolithography First, a glass cavity pattern is made, specifically: spin coating photoresist, developing and exposing the photoresist, removing the exposed photoresist, and obtaining a glass cavity mask pattern. Then, the glass cavity mask pattern is connected to a glass substrate 2 with a through glass via (TGV), such as Figure 1 As shown. The glass cavity mask pattern has an area of ​​7.7mm 2 square pattern.

[0032] Step 2: Wet-etch the glass substrate with the glass cavity mask pattern using a hydrofluoric acid solution like Figure 2 As shown, a glass substrate with a glass cavity mask pattern attached is wet-etched using a hydrofluoric acid solution, and the etching is stopped when the etching depth reaches 110 μm, and then the Figure 1 The remaining photoresist 1 shown has an area of ​​7.7×7.7 mm 2 And a blind cavity with a depth of 110μm.

[0033] Step 3: Glue the chip bonding film to the bottom of the chip, then pick up the chip with the chip bonding film and place it in the glass blind cavity formed in step 2. like Figure 3 As shown, the size of the chip 3 used is 7.2 × 7.2 mm 2 , the height is 100μm, the thickness of the die attach film 4 is 10μm, the die attach film (DAF) comes from Nitto Denko, the functional layer of the chip is facing up, and the non-functional layer of the chip is bonded to the die attach film 4. The chip pick-up and placement instrument used is Finetech's FINEPLACE Matrix, which is used to accurately place the chip in the glass blind cavity. When placing the chip in the glass blind cavity, the instrument applies a pressure of 1MPa to the chip at a temperature of 150°C for 5s.

[0034] Step 4: Attach the chip to the glass blind cavity The glass substrate with the chip placed in it was heated at 130°C for 4 hours to solidify the DAF. Figure 4 As shown, the chip 3 is tightly adhered to the bottom of the glass blind cavity through the chip bonding film 4.

[0035] Step 5: Laminate the dielectric material onto the upper and lower surfaces of the glass panel and cure it like Figure 5 and Figure 6As shown, one or more layers of Ajinomoto Bonding Film (ABF) as dielectric material 5 are attached to both the upper and lower surfaces of the glass panel. Here, only schematic diagrams of attaching one or two layers of ABF to both the upper and lower surfaces of the glass panel are given, but it does not mean that only one or two layers of ABF are used in this process method. More layers of ABF can be attached according to the thickness of the dielectric layer required by the subsequent processing technology.

[0036] If the conventional lamination and curing process is used, the ABF surface formed after curing is as follows Figure 7 As shown, there is a large depression 6 on the ABF surface in the upper portion between the vertical interface of the glass cavity and the edge of the chip.

[0037] The lamination and curing process of this process is as follows: the glass panel with ABF attached is placed in a vacuum laminator and laminated twice. After the two-step lamination is completed, it is cured so that the ABF completely fills the TGV and glass cavity and forms a dielectric surface with small concavity and high flatness, such as Figure 8 shown.

[0038] The two-step lamination process includes the following steps: Step 1, using rubber as a lamination gasket, vacuuming for 90 seconds, and then laminating, the lamination temperature is 100°C, the lamination pressure is 0.7MPa, and the lamination time is 60 seconds. When heated to 100°C, ABF is in a semi-solid and semi-liquid state. The gap between the chip and the glass cavity is preliminarily filled with the semi-solid and semi-liquid ABF; Step 2, use silicon wafer as lamination pad, evacuate for 90s, then laminate, the lamination temperature is 100°C, the lamination pressure is 0.7Mpa, the lamination time is 180s, and the ABF formed by the initial filling is laminated again under the process parameter conditions of 100°C to make the surface of the initially filled ABF smooth.

[0039] The curing conditions were as follows: curing at 100°C for 30 minutes and then further curing at 130°C for 30 minutes.

[0040] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above specific embodiments. The above specific embodiments and the description in the specification are only for further illustrating the principles and preparation effects of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements. For example, other materials may be used as chip bonding films and dielectrics, and the sizes of the glass cavity and the chip may be changed. These changes and improvements fall within the scope of the present invention. The scope of the present invention is defined by the claims and their equivalents.

Claims

1. A cavity filling process for glass panel level embedded packaging, characterized in that: The steps include: Step 1, making a glass cavity mask pattern; Step 2, wet etching the glass substrate with the glass cavity mask pattern attached thereto to form a glass cavity; Step 3, bonding the chip bonding film to the bottom of the chip, picking up the chip with the chip bonding film and placing it in the glass cavity formed in step 2; Step 4, heating the glass substrate processed in step 3 until the chip bonding film is solidified; Step 5: attaching the same number of layers of dielectric material to the upper and lower surfaces of the glass substrate processed in step 4, performing a two-step lamination process on the attached dielectric material, and curing the dielectric material layer after the two-step lamination process.

2. A cavity filling process for glass panel level embedded packaging according to claim 1, characterized in that: The glass substrate is provided with a through-glass hole.

3. A cavity filling process for glass panel level embedded packaging according to claim 1 or 2, characterized in that: The specific method of performing two-step lamination on the attached dielectric material in step 5 is: Step 1, placing a glass substrate with the same number of layers of dielectric material attached to the upper and lower surfaces in a vacuum laminator, using rubber as a laminating pad, evacuating for 90 seconds, and laminating for 60 seconds in a laminating environment of 100° C. and 0.7 MPa; Step 2, for the glass substrate after the lamination process in step 1, use a silicon wafer as a lamination pad, evacuate for 90 seconds, and laminate for 180 seconds in a lamination environment of 100° C. and 0.7 MPa.

4. The cavity filling process of glass panel level embedded package according to claim 3, characterized in that: The dielectric material is an Ajinomoto adhesive film.

5. The cavity filling process of glass panel level embedded package according to claim 3, characterized in that: The specific method of curing the dielectric material layer after the two-step lamination process in step five is: firstly curing at 100° C. for 30 minutes, and then continuing to cure at 130° C. for 30 minutes.

6. The cavity filling process of glass panel level embedded packaging according to claim 5, characterized in that: The specific method of making the glass cavity mask pattern in step 1 is: spin coating photoresist on the surface of the glass substrate, developing and exposing the photoresist, removing the exposed photoresist, and making the glass cavity mask pattern.

7. The cavity filling process for glass panel level embedded packaging according to claim 5, characterized in that: The second step is to use a hydrofluoric acid solution to wet-etch the glass substrate with the glass cavity mask pattern attached thereto.

8. The cavity filling process for glass panel level embedded packaging according to claim 5, characterized in that: In the step three, the functional layer of the chip is placed upward, and the non-functional layer of the chip is bonded to the chip bonding film.

9. The cavity filling process for glass panel level embedded packaging according to claim 5, characterized in that: In the step three, a chip pick-up and placement instrument is used to pick up the chip with the chip bonding film and place it in the glass cavity formed in the step two. Specifically, a pressure of 1 MPa is continuously applied to the chip at a temperature of 150° C. for 5 seconds.

10. The cavity filling process of glass panel level embedded package according to claim 5, characterized in that: The fourth step is to heat the glass substrate processed in the third step at 130° C. for 4 hours until the chip bonding film is cured.

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