Package substrate and manufacturing method thereof

Abstract

A package substrate and a manufacturing method are provided, the package substrate includes a core plate body and dielectric layers formed on two opposite surfaces of the core plate body, and the dielectric layers serve as surface covering layers to prevent the substrate from cracking. The packaging substrate further comprises a plurality of through holes penetrating through the core plate body and the dielectric layer, barrier layers formed on the inner walls of the plurality of through holes, and seed crystal layers formed on the barrier layers on the inner walls of the plurality of through holes, so that the circuit parts and the circuit structures on the two opposite surfaces of the core plate body are electrically connected.

Description

Technical Field

[0001] The invention relates to a packaging substrate for carrying a chip, and in particular to a packaging substrate with low warpage and high dimensional stability and a manufacturing method thereof. Background Art

[0002] With the booming development of the electronics industry, electronic products tend to be thinner, lighter, shorter and smaller in shape, and their functions are developing towards high performance, high functionality and high speed. Therefore, in order to meet the needs of high integration and miniaturization of semiconductor devices, packaging substrates with thinner, low warpage and high-density wiring designs are often used in the packaging process.

[0003] The existing organic material substrates have low glass transition temperature (Tg), which makes them easy to soften and deform during processing, and their dimensional stability is poor. Moreover, traditional substrates are made of composite materials such as resin and glass fiber pressed together with copper foil. Due to the differences in thermal expansion coefficient (CTE), elasticity and stress performance of each material, the substrates are heated to different degrees during processing and are prone to warpage. Furthermore, substrates may deform due to stacking or moisture absorption in a humid storage environment, especially thin substrates are more prone to substrate warpage, which affects the substrate structure and performance.

[0004] To improve the substrate warping problem, hard substrates such as glass, ceramics, silicon carbide (SiC) and other high-rigidity materials with good heat resistance and bending resistance can be selected to strengthen the mechanical strength of the core substrate and reduce the degree of substrate warping and expansion deformation. However, such materials are relatively brittle and prone to cracking after through-holes. In addition, the material processing is difficult and requires high-precision production technology and equipment. The existing technology is still not conducive to reducing production costs.

[0005] Therefore, how to overcome the various problems of the above-mentioned prior art has become a topic that needs to be solved urgently. Summary of the invention

[0006] An object of the present invention is to provide a packaging substrate and a manufacturing method thereof to solve at least one of the above problems.

[0007] In view of the various defects of the above-mentioned prior art, the present invention provides a packaging substrate, including: a core board body, having a first surface and a second surface relative to each other; a first dielectric layer, formed on the first surface and the second surface of the core board body; a plurality of through holes, penetrating the core board body and the first dielectric layer and connecting the first surface and the second surface of the core board body; a barrier layer, formed on the inner walls of the plurality of through holes; a seed layer, formed on the barrier layer on the inner walls of the plurality of through holes; a circuit portion, formed on the first dielectric layer on the first surface and the second surface of the core board body, and electrically connected to the seed layer on the inner walls of the plurality of through holes; and a circuit structure, formed on the first dielectric layer and the circuit portion on the first surface and the second surface of the core board body, the circuit structure comprising at least one second dielectric layer, at least one circuit layer arranged on the second dielectric layer, and a plurality of conductive blind holes formed in the second dielectric layer to electrically connect the circuit layer and the circuit portion, wherein the second dielectric layer is also filled into the plurality of through holes.

[0008] The present invention also provides a method for manufacturing a packaging substrate, comprising: providing a core board having a first surface and a second surface relative to each other; forming a first dielectric layer on the first surface and the second surface of the core board; forming a plurality of through holes penetrating the core board and the first dielectric layer, so that the plurality of through holes connect the first surface and the second surface of the core board; forming a barrier layer on the first dielectric layer and on the inner walls of the plurality of through holes; forming a seed layer on the barrier layer, and patterning the seed layer on the first dielectric layer on the first surface and the second surface of the core board to form a circuit portion, and electrically connecting the circuit portion to the seed layer on the inner walls of the plurality of through holes; and forming a circuit structure on the first dielectric layer and the circuit portion on the first surface and the second surface of the core board, the circuit structure comprising at least one second dielectric layer, at least one circuit layer disposed on the second dielectric layer, and a plurality of conductive blind holes formed in the second dielectric layer to electrically connect the circuit layer and the circuit portion, wherein the second dielectric layer is also filled into the plurality of through holes.

[0009] In some specific embodiments of the aforementioned packaging substrate and the manufacturing method thereof, the material forming the core board is glass, ceramic, silicon carbide (SiC) or a composite material.

[0010] In some specific embodiments of the aforementioned packaging substrate and the manufacturing method thereof, the first dielectric layer is a prepreg material (PP) with glass fiber.

[0011] In some specific embodiments of the aforementioned packaging substrate and the method for manufacturing the same, the glass fiber prepreg (PP) includes an epoxy group, has a thickness of ≥1 nm, and has a coefficient of thermal expansion (CTE) of ≥2 ppm / °C.

[0012] In some specific embodiments of the aforementioned packaging substrate and its manufacturing method, the material forming the barrier layer is tantalum, titanium nitride, tantalum nitride, tungsten nitride, silicon oxynitride, silicon carbonitride or diamond-like carbon (DLC), and the thickness of the barrier layer is ≥1 nm.

[0013] In some specific embodiments of the aforementioned packaging substrate and the manufacturing method thereof, the material forming the seed layer is copper, manganese-doped copper or ruthenium, and the thickness of the seed layer is ≥0.5 um.

[0014] In some specific embodiments of the aforementioned packaging substrate and the method for manufacturing the same, the circuit portion comprises the same material as the seed layer, and the barrier layer is a dielectric material.

[0015] In some specific embodiments of the aforementioned packaging substrate and its manufacturing method, the barrier layer is a conductive material, and the step of patterning the seed layer also includes patterning the barrier layer on the first dielectric layer located on the first surface and the second surface of the core board body, so that the circuit portion contains the same material as the barrier layer and the seed layer.

[0016] In some specific embodiments of the aforementioned packaging substrate and the manufacturing method thereof, a solder mask is formed on the circuit structure.

[0017] From the above, it can be seen that in the packaging substrate and its manufacturing method of the present invention, because the core board body adopts high hardness materials such as glass, ceramics, silicon carbide (SiC) or composite materials, it has advantages over existing organic boards such as low coefficient of thermal expansion (CTE) and good heat resistance. The core board body of the present invention has high mechanical strength, and is not prone to problems such as warping and deformation, and has excellent dimensional stability.

[0018] Furthermore, the package substrate of the present invention uses dielectric materials such as prepreg (PP) with glass fiber to fill holes, replacing the existing method of directly filling through holes with copper in the substrate, greatly simplifying the production process. Dielectric materials such as PP can also be used during lamination of the substrate and subsequent layer addition, without the need to use plugging ink and directly filling the prepreg resin into the through holes, effectively reducing production costs.

[0019] In addition, a high-hardness substrate may develop cracks during the through-hole process. Forming a dielectric material such as PP on the surface of the core board and in the through-hole as a surface covering layer can prevent the cracks from continuing to expand and thus damaging the substrate. Therefore, the dielectric layer of the present invention can protect the substrate structure and prevent the substrate from breaking due to cracks in the through-hole.

[0020] In addition, the core board and the first dielectric layer of the present invention are provided with a barrier layer and a seed layer at the same time, so as to facilitate the electrical connection of the circuit parts and circuit structures on the two opposite surfaces of the core board. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figures 1A to 1FIt is a cross-sectional schematic diagram of a method for manufacturing a packaging substrate of the present invention.

[0022] The reference numerals are as follows: 1 Package substrate 10 Core board 10a First surface 10b Second surface 100 Through Hole 11. First dielectric layer 12 Barrier layer 13 Seed layer 14 Line Department 15 Line structure 151 Second dielectric layer 1510 Opening 152 Line Layer 153 Conductive blind vias 16 Solder mask 154 Electrical connection pads DETAILED DESCRIPTION

[0023] The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0024] It should be noted that the structures, proportions, sizes, etc. shown in the attached drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size, without affecting the effects and purposes that can be produced by the present invention, should still fall within the scope of the technical contents disclosed in the present invention. At the same time, the terms such as "upper", "inside", "outside", "one", etc. quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical contents.

[0025] Figures 1A to 1F It is a cross-sectional schematic diagram of a method for manufacturing a package substrate 1 of the present invention.

[0026] like Figure 1A As shown, a core board 10 is provided, which has a first surface 10 a and a second surface 10 b opposite to each other, and a first dielectric layer 11 is laminated on the first surface 10 a and the second surface 10 b of the core board 10 .

[0027] In this embodiment, the core board 10 may be made of glass, ceramic, silicon carbide (SiC) or other composite materials.

[0028] Furthermore, the material forming the first dielectric layer 11 may be a glass fiber prepreg (PP), which may include an epoxy group and have a coefficient of thermal expansion (CTE) of ≥2 ppm / °C. The thickness of the first dielectric layer 11 may be adjusted according to the type of prepreg, for example, the thickness is ≥1 nm, but not limited thereto.

[0029] like Figure 1B As shown, a plurality of through holes 100 are formed penetrating the core board 10 and the first dielectric layer 11, so that the plurality of through holes 100 connect the first surface 10a and the second surface 10b of the core board 10 and the first dielectric layer 11 on the two opposite surfaces. The plurality of through holes 100 can be formed by laser burning, hydrofluoric acid (HF) etching, plasma etching, mechanical drilling, etc.

[0030] like Figure 1C As shown, a barrier layer 12 is formed on the first dielectric layer 11 and the inner walls of the plurality of through holes 100, so that the barrier layer 12 simultaneously covers the inner walls of the plurality of through holes 100 of different materials and the surface of the first dielectric layer 11. Next, a seed layer 13 is formed on the surface of the barrier layer 12. The barrier layer 12 and the seed layer 13 can be formed by sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0031] In this embodiment, the barrier layer 12 may be a dielectric barrier layer or a conductive barrier layer, and the material forming the dielectric barrier layer includes silicon nitride, silicon oxynitride, silicon carbonitride or diamond-like carbon (DLC), but is not limited thereto. The material forming the conductive barrier layer includes tantalum, titanium nitride, tantalum nitride, tungsten nitride or other metal nitride conductive materials, but is not limited thereto. The material forming the seed layer 13 includes copper, manganese-doped copper or ruthenium, but is not limited thereto.

[0032] In addition, the thickness of the barrier layer 12 may be ≥1 nm, but is not limited thereto. The thickness of the barrier layer 12 may be ≥0.5 um, but is not limited thereto.

[0033] like Figure 1D As shown, a patterning process is performed to pattern the barrier layer 12 of the conductive material located on the first surface 10a and the second surface 10b of the core board 10 and the seed layer 13 on the barrier layer 12 to form a circuit portion 14 and electrically connect the unpatterned barrier layer 12 and seed layer 13 on the inner walls of multiple through holes 100.

[0034] In another specific embodiment, if the material forming the barrier layer 12 is a dielectric material (dielectric barrier layer), the barrier layer 12 is not patterned, and only the seed layer 13 is patterned (not shown) to form a circuit portion 14 and electrically connect the unpatterned seed layer 13 on the inner walls of the multiple through holes 100.

[0035] like Figure 1E As shown, a circuit structure 15 is formed on the first dielectric layer 11 and the circuit portion 14 on the first surface 10 a and the second surface 10 b of the core board 10 .

[0036] In this embodiment, the circuit structure 15 is manufactured by a build-up process, and includes at least one second dielectric layer 151 formed on the first dielectric layer 11 and the circuit portion 14, at least one circuit layer 152 disposed on the second dielectric layer 151, and a plurality of conductive blind vias 153 formed in the second dielectric layer 151, so that the conductive blind vias 153 electrically connect the circuit layer 152 and the circuit portion 14. For example, a plurality of openings 1510 exposing the circuit portion 14 are formed on the second dielectric layer 151 by laser, plasma etching or other methods, so when the circuit layer 152 is manufactured on the second dielectric layer 151 by a patterned circuit process (such as copper electroplating), a plurality of conductive blind vias 153 are formed by electroplating in the plurality of openings 1510.

[0037] Furthermore, the material forming the second dielectric layer 151 may be a prepreg (PP) with glass fiber, so that during the heating and pressing process, the prepreg may flow into the plurality of through holes 100 and fill the plurality of through holes 100 after curing. In addition, the material forming the second dielectric layer 151 may be the same as or different from the material forming the first dielectric layer 11, for example, the second dielectric layer 151 may also be a PP having a coefficient of thermal expansion (CTE) of ≥2 ppm / °C, and the thickness of the second dielectric layer 151 may be adjusted according to the type of prepreg and the number of layers, for example, the thickness is ≥1 nm, but is not limited thereto.

[0038] It should be understood that, by using the build-up method, the number of layers of the second dielectric layer 151 of the circuit structure 15 can be designed according to requirements to manufacture the required number of circuit layers 152 .

[0039] like Figure 1F As shown, a solder mask 16 may be formed on the outermost side of the circuit structure 15 to form a symmetrical packaging substrate 1 .

[0040] In this embodiment, the solder mask layer 16 can be a dry film solder mask material or any photosensitive material (such as photosensitive polyimide), but is not limited thereto. Part of the solder mask material can be removed by exposure and development to expose part of the circuit layer 152 to form an electrical connection pad 154 as an external contact.

[0041] Therefore, the manufacturing method of the present invention mainly adopts glass, ceramic, silicon carbide (SiC) or composite materials to make the core board 10, so that it has advantages over existing organic boards such as low thermal expansion coefficient (CTE) and good heat resistance. The core board 10 of the present invention has high mechanical strength, so it is not easy to cause problems such as warping and deformation, and has excellent dimensional stability.

[0042] Furthermore, the package substrate 1 of the present invention is mainly filled with dielectric materials such as prepreg (PP) with glass fiber, replacing the existing method of filling through holes with copper in the substrate, greatly simplifying the production process. In addition, dielectric materials such as PP are also used during lamination of the substrate and subsequent layer addition, and the prepreg resin is directly filled into the through hole 100 without the need for plugging ink, effectively reducing the production cost.

[0043] In addition, a high-hardness substrate may develop cracks during the through-hole process. Forming a dielectric material such as PP on the surface of the core board 10 and in the through-hole 100 as a surface covering layer can prevent the cracks from continuing to expand and thus damaging the substrate. Therefore, the first dielectric layer 11 and the second dielectric layer 151 of the present invention can protect the substrate structure and prevent the substrate from breaking due to cracks in the through-hole 100.

[0044] In addition, the core board 10 and the first dielectric layer 11 of the present invention have a barrier layer 12 and a seed layer 13 to facilitate electrical connection between the circuit portion 14 and the circuit structure 15 on two opposite surfaces of the core board 10 .

[0045] The present invention also provides a packaging substrate 1 , including a core board 10 , a first dielectric layer 11 , a plurality of through holes 100 , a barrier layer 12 , a seed layer 13 , a circuit portion 14 , and a circuit structure 15 .

[0046] The core board 10 has a first surface 10 a and a second surface 10 b opposite to each other.

[0047] The first dielectric layer 11 is formed on the first surface 10 a and the second surface 10 b of the core board 10 .

[0048] The plurality of through holes 100 penetrate the core board 10 and the first dielectric layer 11 and connect the first surface 10 a and the second surface 10 b of the core board 10 .

[0049] The barrier layer 12 is formed on the first dielectric layer 11 and on the inner walls of the plurality of through holes 100 .

[0050] The seed layer 13 is formed on the barrier layer 12 on the inner walls of the plurality of through holes 100 .

[0051] The circuit portion 14 is formed on the first dielectric layer 11 on the first surface 10 a and the second surface 10 b of the core board 10 , and is electrically connected to the seed layer 13 on the inner walls of the plurality of through holes 100 .

[0052] The circuit structure 15 is formed on the circuit portion 14 on the first surface 10a and the second surface 10b of the core board 10. The circuit structure 15 includes at least one second dielectric layer 151, at least one circuit layer 152 arranged on the second dielectric layer 151, and a plurality of conductive blind holes 153 formed in the second dielectric layer 151 to electrically connect the circuit layer 152 and the circuit portion 14, wherein the second dielectric layer 151 is also filled into the plurality of through holes 100.

[0053] In one embodiment, the core plate is made of glass, ceramic, silicon carbide (SiC) or a composite material.

[0054] In one embodiment, the first dielectric layer is a prepreg material (PP) with glass fiber.

[0055] In one embodiment, the glass fiber prepreg (PP) includes an epoxy group, has a thickness of ≥1 nm, and has a coefficient of thermal expansion (CTE) of ≥2 ppm / °C.

[0056] In one embodiment, the barrier layer is formed of tantalum, titanium nitride, tantalum nitride, tungsten nitride, silicon oxynitride, silicon carbonitride or diamond-like carbon (DLC), and the thickness of the barrier layer is ≥1 nm.

[0057] In one embodiment, the seed layer is made of copper, manganese-doped copper or ruthenium, and the thickness of the seed layer is ≥0.5 um.

[0058] In one embodiment, a solder mask is formed on the circuit structure.

[0059] In summary, the packaging substrate and its manufacturing method of the present invention adopts glass, ceramic, silicon carbide (SiC) or composite materials to make the core board, so that it has the advantages of low coefficient of thermal expansion (CTE) and good heat resistance. The core board of the present invention has high mechanical strength, so it is not easy to cause problems such as warping, expansion and deformation during the substrate processing process and subsequent storage and transportation process, and has excellent dimensional stability without affecting the performance of the substrate.

[0060] Furthermore, the package substrate of the present invention mainly uses dielectric materials such as prepreg (PP) with glass fiber to fill holes, replacing the existing method of filling through holes with copper in the substrate, greatly simplifying the production process. Dielectric materials such as PP are also used during lamination of the substrate and subsequent layer addition. There is no need to use plugging ink, and the prepreg resin is directly filled into the through hole for curing. The process is simple and the production cost is effectively reduced.

[0061] In addition, a high-hardness substrate may develop cracks during the through-hole process. Forming a dielectric material such as PP on the surface of the core board and in the through-hole as a surface covering layer can prevent the cracks from continuing to expand and thus damaging the substrate. Therefore, the dielectric layer of the present invention can protect the substrate structure and prevent the substrate from breaking due to cracks in the through-hole.

[0062] In addition, the core board and the first dielectric layer of the present invention have a barrier layer and a seed layer at the same time to ensure that the circuit parts and circuit structures on the two opposite surfaces of the core board are electrically connected through the barrier layer and the seed layer.

[0063] The above embodiments are used to illustrate the principles and effects of the present invention, but are not used to limit the present invention. Those skilled in the art may modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the claims.

Claims

1. A packaging substrate, comprising: The core plate has a first surface and a second surface opposite to each other; A first dielectric layer is formed on the first surface and the second surface of the core board; A plurality of through holes, penetrating the core board and the first dielectric layer and connecting the first surface and the second surface of the core board; A barrier layer formed on the inner walls of the plurality of through holes; A seed layer formed on the barrier layer on the inner walls of the plurality of through holes; A circuit portion is formed on the first dielectric layer on the first surface and the second surface of the core board and is electrically connected to the seed layer on the inner walls of the plurality of through holes; as well as A circuit structure is formed on the first dielectric layer and the circuit portion on the first surface and the second surface of the core board. The circuit structure includes at least one second dielectric layer, at least one circuit layer arranged on the second dielectric layer, and a plurality of conductive blind holes formed in the second dielectric layer to electrically connect the circuit layer and the circuit portion, wherein the second dielectric layer is also filled into the plurality of through holes.

2. The packaging substrate according to claim 1, wherein: The core plate is made of glass, ceramic, silicon carbide or a composite material.

3. The packaging substrate according to claim 1, wherein: The first dielectric layer is a prepreg material with glass fiber.

4. The packaging substrate according to claim 3, characterized in that: The glass fiber prepreg comprises an epoxy group, has a thickness of ≥1 nm, and has a thermal expansion coefficient of ≥2 ppm / °C.

5. The packaging substrate according to claim 1, wherein: The barrier layer is made of tantalum, titanium nitride, tantalum nitride, tungsten nitride, silicon oxynitride, silicon carbonitride or diamond-like carbon, and the thickness of the barrier layer is ≥1 nm.

6. The packaging substrate according to claim 1, wherein: The seed layer is made of copper, manganese-doped copper or ruthenium, and the thickness of the seed layer is greater than or equal to 0.5 um.

7. The packaging substrate according to claim 1, wherein: The line portion includes the same material as the seed layer.

8. The packaging substrate according to claim 7, wherein: The circuit portion includes the same material as the barrier layer and the seed layer, and the barrier layer is a conductive material.

9. The packaging substrate according to claim 1, wherein: A solder resist layer is formed on the circuit structure.

10. A method for manufacturing a packaging substrate, comprising: Providing a core plate having a first surface and a second surface opposite to each other; Forming a first dielectric layer on the first surface and the second surface of the core board; Forming a plurality of through holes penetrating the core board and the first dielectric layer, so that the plurality of through holes connect the first surface and the second surface of the core board; forming a barrier layer on the first dielectric layer and on the inner walls of the plurality of through holes; Forming a seed layer on the barrier layer, and patterning the seed layer on the first dielectric layer on the first surface and the second surface of the core board to form a circuit portion, and making the circuit portion electrically connected to the seed layer on the inner walls of the plurality of through holes; as well as A circuit structure is formed on the first dielectric layer and the circuit portion on the first surface and the second surface of the core board, wherein the circuit structure includes at least one second dielectric layer, at least one circuit layer arranged on the second dielectric layer, and a plurality of conductive blind holes formed in the second dielectric layer to electrically connect the circuit layer and the circuit portion, wherein the second dielectric layer is also filled into the plurality of through holes.

11. The method for manufacturing a packaging substrate according to claim 10, wherein: The core plate is made of glass, ceramic, silicon carbide or a composite material.

12. The method for manufacturing a packaging substrate according to claim 10, wherein: The first dielectric layer is a prepreg material with glass fiber.

13. The method for manufacturing a packaging substrate according to claim 12, wherein: The glass fiber prepreg comprises an epoxy group, has a thickness of ≥1 nm, and has a thermal expansion coefficient of ≥2 ppm / °C.

14. The method for manufacturing a packaging substrate according to claim 10, wherein: The barrier layer is made of tantalum, titanium nitride, tantalum nitride, tungsten nitride, silicon oxynitride, silicon carbonitride or diamond-like carbon, and the thickness of the barrier layer is ≥1 nm.

15. The method for manufacturing a packaging substrate according to claim 10, wherein: The seed layer is made of copper, manganese-doped copper or ruthenium, and the thickness of the seed layer is greater than or equal to 0.5 um.

16. The method for manufacturing a packaging substrate according to claim 10, wherein: The circuit portion includes the same material as the seed layer, and the barrier layer is a dielectric material.

17. The method for manufacturing a packaging substrate according to claim 16, wherein: The barrier layer is a conductive material, and the step of patterning the seed layer further includes patterning the barrier layer on the first dielectric layer on the first surface and the second surface of the core board so that the circuit portion includes the same material as the barrier layer and the seed layer.

18. The method for manufacturing a packaging substrate according to claim 10, wherein: A solder resist layer is formed on the circuit structure.

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