Overvoltage protection circuit for LDO (Low Dropout Regulator) output voltage

Abstract

The invention discloses an overvoltage protection circuit for LDO output voltage. The overvoltage protection circuit comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a first resistor, a second resistor, a first bias current and a second bias current. Wherein the first MOS tube and the fifth MOS tube are NMOS (N-channel metal oxide semiconductor) tubes, and the second MOS tube, the third MOS tube and the fourth MOS tube are PMOS (P-channel metal oxide semiconductor) tubes; the circuit provided by the invention has overvoltage automatic detection and rapid discharge functions, and realizes that the output voltage of the LDO can rapidly return to the normal output voltage from an overvoltage state in the power-off process of the LDO, so that a load device is protected; the circuit is simple in structure, clear in logic, easy to implement and convenient to use.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an overvoltage protection circuit for an LDO output voltage. Background Art

[0002] Usually, when the external power supply of the chip is only high voltage, an LDO that converts high voltage to low voltage is needed to provide power for the low voltage devices on the chip. When the LDO load current changes greatly instantly during the LDO power-off process, the LDO output voltage overshoots. The greater the current change, the greater the overshoot. Since the LDO feedback loop is limited by the loop bandwidth and cannot keep up with this rapid change, the output voltage is in an overvoltage state for a period of time, which may cause device reliability problems. Summary of the invention

[0003] The object of the present invention is to provide an overvoltage protection circuit for an LDO output voltage to solve the problems in the background technology.

[0004] In order to solve the above technical problems, the present invention provides an overvoltage protection circuit for an LDO output voltage, comprising: a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a first resistor, a second resistor, a first bias current, and a second bias current; wherein the first MOS tube and the fifth MOS tube are NMOS tubes, and the second MOS tube, the third MOS tube, and the fourth MOS tube are PMOS tubes; The positive end of the first bias current is connected to the power supply voltage, the negative end is connected to the drain end of the first MOS tube, the gate end of the first MOS tube is connected to the first end of the first resistor, and the source end of the first MOS tube is grounded; The source terminal of the second MOS tube is connected to the power supply voltage, the gate terminal is connected to its own drain terminal and the gate terminal of the third MOS tube at the same time, the drain terminal of the second MOS tube is connected to the gate terminal of the first MOS tube and the first terminal of the second resistor at the same time, and the second terminal of the second resistor is grounded; The source terminal of the third MOS tube is connected to the power supply voltage, the drain terminal is connected to the first end of the second resistor, and the second end of the second resistor is grounded; The source terminal of the fourth MOS tube is connected to the output voltage VOUT of the LDO, the gate terminal is connected to the current mirror bias voltage VB, the drain terminal is connected to the first terminal of the second resistor and the positive terminal of the second bias current at the same time, and the negative terminal of the second bias current is grounded; The drain terminal of the fifth MOS tube is connected to the output voltage VOUT of the LDO, the gate terminal is connected to the drain terminal of the fourth MOS tube, and the source terminal is grounded.

[0005] In one implementation, the second MOS tube and the first resistor provide a gate bias voltage for the first MOS tube, so that the first MOS tube always operates in a saturation region when a first bias current is input, and the gate voltage of the first MOS tube is determined by the first bias current flowing through the first MOS tube and the width-to-length ratio W / L of the first MOS tube: , The current flowing through the second MOS tube ; Through the mirror relationship between the second MOS tube and the third MOS tube, the current of the second MOS tube is mirrored to the third MOS tube: , the gate control voltage of the fifth MOS tube is provided by the voltage VR across the second resistor, that is: .

[0006] In one embodiment, the second bias current is used to absorb the current flowing through the fourth MOS tube, so that the current of the third MOS tube flows entirely through the second resistor; the fourth MOS tube is used for overvoltage detection, and the fifth MOS tube is a current discharge path when overvoltage occurs.

[0007] In one implementation, the process parameters of the fifth MOS transistor and the first MOS transistor are consistent.

[0008] The present invention provides an overvoltage protection circuit for an LDO output voltage. The circuit has the functions of automatic overvoltage detection and rapid discharge, so that the LDO output voltage can quickly return to a normal output voltage from an overvoltage state during a power-off process of the LDO, thereby protecting load devices. The circuit has a simple structure, clear logic, is easy to implement, and is convenient to use. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 The present invention provides a schematic diagram of an overvoltage protection circuit structure of an LDO output voltage.

[0010] Figure 2 This is a schematic diagram of LDO output current and voltage. DETAILED DESCRIPTION

[0011] The following is a further detailed description of an LDO output voltage overvoltage protection circuit proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0012] The present invention provides an overvoltage protection circuit for LDO output voltage, the structure of which is as follows: Figure 1As shown in FIG. 1 , in the LDO structure, VOUT is the LDO output voltage and Iout is the load current. When the output voltage of the circuit is overshot, the overvoltage protection circuit can protect the load device.

[0013] Please continue reading Figure 1 The overvoltage protection circuit includes an NMOS tube M1, a PMOS tube M2, a PMOS tube M3, a PMOS tube M4, an NMOS tube M5, resistors R1 and R2, and bias currents I1 and I2; and: , , .

[0014] Where n is 2, m is 1.5, k is 10, and W / L is the width-to-length ratio of the MOS tube.

[0015] The positive end of the bias current I1 is connected to the power supply voltage, the negative end is connected to the drain end of the NMOS tube M1, the gate end of the NMOS tube M1 is connected to the first end of the resistor R1, and the source end of the NMOS tube M1 is grounded. The source end of the PMOS tube M2 is connected to the power supply voltage, the gate end is connected to its own drain end and the gate end of the PMOS tube M3 at the same time, the drain end of the PMOS tube M2 is connected to the gate end of the NMOS tube M1 and the first end of the resistor R1 at the same time, and the second end of the resistor R1 is grounded. The source end of the PMOS tube M3 is connected to the power supply voltage, the drain end is connected to the first end of the resistor R2, and the second end of the resistor R2 is grounded. The source end of the PMOS tube M4 is connected to the output voltage VOUT of the LDO, the gate end is connected to the current mirror bias voltage VB, the drain end is connected to the first end of the resistor R2 and the positive end of the bias current I2 at the same time, and the negative end of the bias current I2 is grounded. The drain end of the NMOS tube M5 is connected to the output voltage VOUT of the LDO, the gate end is connected to the drain end of the PMOS tube M4, and the source end is grounded.

[0016] The PMOS tube M2 and the resistor R1 provide a gate bias voltage for the NMOS tube M1, so that the NMOS tube M1 always works in the saturation region under the input current I1. The gate voltage of the NMOS tube M1 is determined by the bias current I1 flowing through the NMOS tube M1 and the W / L size of the NMOS tube M1, that is: , The current flowing through PMOS tube M2 .

[0017] Through the mirror relationship between PMOS tube M2 and PMOS tube M3, the current of PMOS tube M2 is mirrored to PMOS tube M3: , the gate control voltage of the NMOS tube M5 is provided by the voltage VR across the second resistor, that is: .

[0018] The function of bias current I2 is to absorb the current flowing through PMOS tube M4, and , so that all the current of the PMOS tube M3 flows through the resistor R2.

[0019] The PMOS tube M4 serves as an overvoltage detection circuit, and the NMOS tube M5 serves as a current discharge path when overvoltage occurs.

[0020] When in normal working state, the PMOS tube M4 and the NMOS tube M5 work in the saturation region. Keeping the NMOS tube M5 always turned on requires consuming a part of static current. By adjusting the parameters m and n to adjust the gate voltage of the NMOS tube M5, the NMOS tube M5 can consume a relatively small current when kept turned on.

[0021] When the LDO load current changes greatly instantaneously, the LDO output voltage is instantly pulled up (such as Figure 2 As shown by the dotted line VOUT in the figure), through the PMOS tube M4, the gate end of the NMOS tube M5 will also be pulled up, the current of the NMOS tube M5 will increase instantly, and VOUT will be discharged quickly. The VOUT voltage will also be quickly pulled down. During the discharge process, the current of the NMOS tube M5 will gradually decrease and finally return to the normal state, as shown in the figure below. Figure 2 VOUT is shown as the solid line.

[0022] The present invention provides a protection circuit for LDO under overvoltage conditions. The circuit is divided into three main parts, an overvoltage detection circuit, an overvoltage discharge path and a control voltage production circuit, and two working states, namely a normal working state and an overvoltage working state. In the normal working state, the gate voltage of the device M5 of the overvoltage discharge path generates a gate voltage derived from M1 of the same type. By selecting a suitable M1 input reference current size, a resistor R1 / R2 ratio n and a M3 and M2 size ratio m, the gate voltage of M5 can be adjusted, so that M5 has a relatively small leakage current in the normal working state; at the same time, because the process parameters of M5 and M1 are consistent, the range of variation of the M5 leakage current with the process foot can be well controlled. In the case of overvoltage, the overvoltage part can be quickly discharged through M5, thereby protecting the load circuit from long-term overvoltage and solving the reliability problem caused by overvoltage.

[0023] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. An overvoltage protection circuit for LDO output voltage, characterized in that: include: A first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a first resistor, a second resistor, a first bias current, and a second bias current; The first MOS tube and the fifth MOS tube are NMOS tubes, and the second MOS tube, the third MOS tube, and the fourth MOS tube are PMOS tubes; The positive end of the first bias current is connected to the power supply voltage, the negative end is connected to the drain end of the first MOS tube, the gate end of the first MOS tube is connected to the first end of the first resistor, and the source end of the first MOS tube is grounded; The source terminal of the second MOS tube is connected to the power supply voltage, the gate terminal is connected to its own drain terminal and the gate terminal of the third MOS tube at the same time, the drain terminal of the second MOS tube is connected to the gate terminal of the first MOS tube and the first terminal of the second resistor at the same time, and the second terminal of the second resistor is grounded; The source terminal of the third MOS tube is connected to the power supply voltage, the drain terminal is connected to the first end of the second resistor, and the second end of the second resistor is grounded; The source terminal of the fourth MOS tube is connected to the output voltage VOUT of the LDO, the gate terminal is connected to the current mirror bias voltage VB, the drain terminal is connected to the first terminal of the second resistor and the positive terminal of the second bias current at the same time, and the negative terminal of the second bias current is grounded; The drain terminal of the fifth MOS tube is connected to the output voltage VOUT of the LDO, the gate terminal is connected to the drain terminal of the fourth MOS tube, and the source terminal is grounded.

2. The overvoltage protection circuit for LDO output voltage according to claim 1, characterized in that: The second MOS tube and the first resistor provide a gate bias voltage for the first MOS tube, so that the first MOS tube always operates in a saturation region when the first bias current is input. The gate voltage of the first MOS tube is determined by the first bias current flowing through the first MOS tube and the width-to-length ratio W / L of the first MOS tube: ， The current flowing through the second MOS tube ; Through the mirror relationship between the second MOS tube and the third MOS tube, the current of the second MOS tube is mirrored to the third MOS tube: , the gate control voltage of the fifth MOS tube is provided by the voltage VR across the second resistor, that is: .

3. The overvoltage protection circuit for LDO output voltage according to claim 1, characterized in that: The second bias current is used to absorb the current flowing through the fourth MOS tube, so that the current of the third MOS tube flows entirely through the second resistor; the fourth MOS tube is used for overvoltage detection, and the fifth MOS tube is a current discharge path when overvoltage occurs.

4. The overvoltage protection circuit for LDO output voltage according to claim 1, characterized in that: The process parameters of the fifth MOS transistor and the first MOS transistor are consistent.

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