Integrated high power device and power switch including the same

Abstract

The invention discloses an integrated high-voltage power device and a power switch including the same. The high-voltage power device comprises a plurality of first transistors; the drain electrodes of the plurality of first transistors are electrically connected with the drain electrodes of the one or more second transistors, the grid electrodes of the plurality of first transistors are electrically connected, the grid electrodes of the one or more second transistors are electrically connected, and the drain electrodes of the plurality of first transistors are electrically connected with the drain electrodes of the one or more second transistors. The one or more second transistors are distributed at one or more locations of the high voltage power device and are configured to detect temperatures at the one or more locations.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices and circuits, and in particular to an integrated high-power device and a power switch comprising the high-power device. Background Art

[0002] Intelligent power switch is a hybrid integrated circuit of high-voltage devices and low-voltage logic, which is widely used in industrial automation, automotive electronics and other fields. Intelligent power switch refers to the integration of high-voltage power devices with high withstand voltage and large current, and low-voltage control logic with control and protection functions. It can provide intelligent control of power devices and provide load drive and protection functions to the outside.

[0003] refer to Figure 1 The system-level package (SIP) solution of the related intelligent power switch is to attach a thermistor R ntc The temperature is monitored by current sampling resistor R sampl The current sampling and overcurrent protection are carried out in series. The disadvantages of this solution are that the off-chip thermistor and the current sampling resistor are used separately, which makes the system integration low; in addition, the off-chip current sensing resistor should be a high-power, high-precision, low-resistance device to avoid the power current in the current sampling resistor R sampl It brings large power loss and voltage drop, and the small voltage of millivolt (mv) level across the current sensing resistor makes it difficult to detect the voltage at the subsequent stage. Summary of the invention

[0004] In view of the above technical problems, the present application proposes an integrated high-power device and a power switch including the integrated high-power device to solve the problems of low integration, high power loss and difficulty in voltage detection of related power switches.

[0005] In a first aspect, the present application provides an integrated high-voltage power device, comprising: a plurality of first transistors; and one or more second transistors integrated with the plurality of first transistors, wherein the drains of the plurality of first transistors are electrically connected to the drains of the one or more second transistors, the gates of the plurality of first transistors are electrically connected, the gates of the one or more second transistors are electrically connected, and the one or more second transistors are distributed at one or more positions of the high-voltage power device and are configured to detect the temperature of the one or more positions.

[0006] Optionally, the multiple first transistors include: a main power transistor configured to allow external current to flow through the high-voltage power device; a current detection transistor configured to detect current flowing through the high-voltage power device; and an overcurrent protection transistor configured to protect the main power transistor from overcurrent.

[0007] Optionally, the ratio between the area of ​​the active area of ​​the main power transistor and the active area of ​​the current detection transistor is K:1; the ratio between the active area of ​​the main power transistor and the active area of ​​the overcurrent protection transistor is N:1, where K and N are both greater than 1.

[0008] Optionally, the main power transistor and the overcurrent detection transistor share a first chip substrate; the main power transistor and the current detection transistor share a second chip substrate.

[0009] Optionally, the first chip substrate and the second chip substrate are the same chip substrate.

[0010] In a second aspect, the present application provides a power switch. The power switch includes: a high-voltage power device according to the first aspect above and a driver chip. The driver chip includes: a gate drive circuit electrically connected to the multiple first transistors and configured to provide a gate drive voltage to the gates of the multiple first transistors; a current detection circuit electrically connected to the current detection transistor and configured to detect the current flowing through the main power transistor; an overcurrent protection circuit electrically connected to the overcurrent protection transistor and the gate drive circuit, and configured to stop the gate drive circuit from providing a drive voltage to the multiple first transistors when the current in the main power transistor exceeds a current threshold, thereby achieving overcurrent protection; and one or more overtemperature protection circuits electrically connected to the gate drive circuit and the one or more second transistors, wherein each of the one or more overtemperature protection circuits is configured to stop the gate drive circuit from providing a drive voltage to the multiple first transistors when the temperature of any one of the one or more positions exceeds a temperature threshold, thereby achieving overtemperature protection.

[0011] Optionally, the gate drive circuit includes: a level conversion circuit, configured to receive an input control signal and generate a first control signal based on the input control signal; a protection logic, an input end of the protection logic is electrically connected to the overcurrent protection circuit and the one or more over-temperature protection circuits, and is configured to receive an overcurrent protection signal from the overcurrent protection circuit, receive an overtemperature protection signal from the one or more over-temperature protection circuits, and generate a protection signal based on the overcurrent protection signal and the over-temperature protection signal; a driver, electrically connected to the level conversion circuit and the protection logic, and configured to turn on or off the multiple first transistors based on the protection signal and the first control signal; a charge pump, electrically connected to the driver and the level conversion circuit, and configured to supply power to the driver and the level conversion circuit.

[0012] Optionally, the current detection circuit includes: a first operational amplifier, wherein the two input terminals of the first operational amplifier are electrically connected to the source of the main power transistor and the source of the current detection transistor, respectively; a first current mirror, wherein the input terminal of the first current mirror is electrically connected to the source of the current detection transistor and the output terminal of the first operational amplifier; a second current mirror, wherein the input terminal of the second current mirror is electrically connected to the output terminal of the first current mirror; a first switch array, which is electrically connected to the output terminal of the second current mirror and includes a plurality of first switches, wherein one or more of the plurality of first switches are selectively turned on or off; and a first detector, which is electrically connected to the first switch array and detects the current flowing through the main power transistor.

[0013] Optionally, the overcurrent protection circuit includes: a second operational amplifier, wherein the two input terminals of the second operational amplifier are electrically connected to the source of the main power transistor and the source of the overcurrent protection transistor, respectively; a third current mirror, wherein the input terminal of the third current mirror is electrically connected to the source of the overcurrent protection transistor and the output terminal of the second operational amplifier; a fourth current mirror, wherein the input terminal of the fourth current mirror is electrically connected to the output terminal of the third current mirror; a second switch array, electrically connected to the output terminal of the fourth current mirror and including a plurality of second switches, wherein one or more of the plurality of second switches are selectively turned on or off; a first comparator, electrically connected to one terminal of the second switch array, and compares the voltage of the one terminal of the second switch array with a reference voltage to obtain a comparison result; an overcurrent protection logic, electrically connected to the output terminal of the first comparator, and causes the gate drive circuit to stop providing a drive voltage to the plurality of first transistors when the comparison result exceeds the current threshold.

[0014] Optionally, each of the one or more over-temperature protection circuits includes: a current source configured to generate a current that is independent of temperature changes; a fifth current mirror, wherein the input end of the fifth current mirror is electrically connected to the current source; a third switch array, including a plurality of third switches, each of the plurality of third switches being electrically connected to a corresponding one of the plurality of output ends of the fifth current mirror; a first resistor, wherein the first end of the first resistor is electrically connected to the source of a corresponding one of the one or more over-temperature protection transistors; a second comparator, electrically connected to the second end of the first resistor, and configured to compare the voltage of the second end with a reference voltage to obtain a comparison result; and over-temperature protection logic, electrically connected to the output end of the second comparator, and configured to cause the gate drive circuit to stop providing a drive voltage to the plurality of first transistors when the comparison result exceeds a specific threshold.

[0015] The integrated high-power device and the power switch including the high-power device provided by the present invention have the following beneficial effects:

[0016] Based on the shielded gate trench SGT / Trench process, metal-oxide semiconductor field effect transistors MOS of different sizes are designed, and the current detection device is integrated into the vertical double diffused metal oxide semiconductor device VDMOS transistor, which makes the current detection more accurate on the one hand. On the other hand, the system integration is improved. Based on the SGT / Trench process, multiple MOS of different sizes are designed, and the temperature sensing device is integrated into the VDMOS transistor. On the one hand, the temperature monitoring is more accurate, and on the other hand, the error caused by the position deviation or thermal conduction delay of the external temperature sensor can be avoided by arranging the temperature sensing MOS at different positions of the power tube, and the system integration is improved. In addition, the driver chip in the power switch of the present application controls the temperature protection, overcurrent protection, and current detection ratio in a programmable manner, which increases the flexibility of system application and the actual scope of use. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 is a schematic diagram of the structure of the relevant power switch;

[0019] Figure 2A is a circuit diagram of an integrated high-power device of the present application;

[0020] Figure 2B is a schematic cross-sectional structure diagram of a transistor of an integrated high-power device of the present application;

[0021] Figure 2C is a simplified circuit diagram of an integrated high-power device of the present application;

[0022] Figure 3A It is a structural schematic diagram of the intelligent power switch of the present application;

[0023] Figure 3B is an external schematic diagram of the SIP package of the intelligent power switch of the present application;

[0024] Figure 4 is a schematic diagram of the structure of the gate drive circuit in the intelligent power switch of the present application;

[0025] Figure 5A It is a schematic diagram of the structure of a charge pump in a gate drive circuit in an intelligent power switch of the present application;

[0026] Figure 5B It is a schematic diagram of the structure of a driver in a gate drive circuit in an intelligent power switch of the present application;

[0027] Figure 6 is a schematic diagram of a programmable current detection circuit in the intelligent power switch of the present application;

[0028] Figure 7 is a schematic diagram of a programmable overcurrent protection circuit in the intelligent power switch of the present application; and

[0029] Figure 8 It is a schematic diagram of a programmable over-temperature protection circuit in the intelligent power switch of the present application. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0031] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings, and "multiple" generally includes at least two.

[0032] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0033] The purpose of this application is to propose a new power device based on high-voltage technology, which is an integrated chip. The integrated chip includes a temperature sensing transistor, a current detection transistor and an overcurrent protection transistor. At the same time, current detection, temperature detection, over-temperature protection and overcurrent protection are performed in the driving chip part to solve the problems existing in the related technology.

[0034] refer to Figure 2A-2C , Figure 2A The circuit diagram of the on-chip integrated high-voltage power device 1 provided by the present application is shown. Figure 2B shows a cross-sectional schematic diagram of an on-chip integrated high-voltage power device 1 of the present application, Figure 2CFIG. 1 shows a simplified circuit diagram of the high-voltage power device 1. The high-voltage power device 1 includes a plurality of first transistors and one or more second transistors integrated with one or more first transistors. In an embodiment of the present application, the plurality of first transistors and the one or more second transistors may use the same substrate, such as Figure 2B For example, in Figure 2A 3 shows three first transistors M1-M3 and three second transistors M4-M6. It should be understood that although Figure 2A and Figure 2B Three second transistors M4-M6 are shown in the figure, but the number of one or more second transistors can be manufactured as needed, for example, P second transistors, where P is a positive integer greater than 3. The high-voltage power device 1 is manufactured using a vertical double-diffused metal-oxide semiconductor field effect transistor VDMOS (Vertical Double-diffused Metal-Oxide-Semiconductor) manufacturing technology, and a trench process or a shielded gate trench SGT (Shielded Gate Trench) process is used to manufacture multiple first transistors and one or more second transistors. Specifically, the multiple second transistors M4-M6 are located at the same layer as the first transistors M1-M3, and use the same substrate 101 and are integrated on the same chip. As shown Figure 2B As shown, the second transistors M4-M6 are used for temperature detection and are arranged according to the requirements of the temperature detection position, for example, arranged in the center of the chip or arranged at the edge of the chip. VDMOS technology and SGT and Trench technology are known to those skilled in the art and are not described in detail in this application.

[0035] In some embodiments, each of the plurality of first transistors M1-M3 is a metal oxide semiconductor (MOS) tube, the drains D of the plurality of first transistors M1-M3 use a common substrate 101, and the gates G1 are electrically connected to the same potential. Each of the one or more second transistors M4-M6 is a MOS tube, the drains D of the plurality of second transistors M4-M6 use a common substrate 101, and the gates G are electrically connected to the same potential. The one or more second transistors M4-M6 are distributed at one or more locations of the high-voltage power device 1, and are configured to detect the temperature of the one or more locations.

[0036] In some embodiments, the plurality of first transistors M1-M3 include a main power transistor M1 configured to allow an external current to flow through the high-voltage power device 1; a current detection transistor M2 for detecting an external current flowing through the high-voltage power device 1; and an overcurrent protection transistor M3 for performing overcurrent protection on the main power transistor M1.

[0037] In some embodiments, the ratio of the area of ​​the active region of the main power transistor M1 to the area of ​​the active region of the current detection transistor M2 is K:1, that is, the ratio of the number of cells of M1 to the number of cells of M2 is K:1. K is greater than 1, such as Figure 6 shown.

[0038] In some embodiments, the ratio of the area of ​​the active region of the main power transistor M1 to the area of ​​the active region of the overcurrent protection transistor M3 is N:1, that is, the ratio of the number of cells of M1 to the number of cells of M3 is N:1. N is greater than 1, such as Figure 7 shown.

[0039] In the technical solution of the present application, transistors M1-M6 of different sizes are designed on the high-voltage power device based on the SGT / Trench process, and the current detection transistor M2 and the main power transistor M1 are integrated in the form of VDMOS, which makes the current detection more accurate on the one hand and improves the system integration on the other hand. The high-voltage power device 1 of the present application is suitable for high voltage ranges, such as 30V-100V, 20V-200V, 15V-250V, etc. In addition, the temperature detection transistors M4-M6 are integrated with the main power transistor M1 in the form of VDMOS. Since the temperature detection is not performed by external pasting, on the one hand, the temperature monitoring is more accurate, and on the other hand, the temperature sensing transistors M4-M6 can be arranged at different positions of the high-voltage power tube M1 to avoid the error caused by the position deviation or thermal conduction delay of the external temperature sensor, and improve the system integration.

[0040] The following is a schematic diagram of the structure of the intelligent power switch of the present application. The intelligent power switch adopts the high-voltage power device described in the above embodiment of the present application.

[0041] refer to Figure 3A , Figure 3A The schematic diagram of the structure of the intelligent power switch of the present application is shown. The intelligent power switch of the present application includes the above Figure 2A-2CThe high-voltage power device 1 and the driver chip 2 shown. The driver chip 2 includes: a gate drive circuit 21, which is electrically connected to the gates of the plurality of first transistors M1-M3 and configured to provide a gate drive voltage to the gates of the plurality of first transistors M1-M3; a current detection circuit 22, which is electrically connected to the current detection transistor M2 and configured to detect the current flowing through the main power transistor M1; an overcurrent protection circuit 23, which is electrically connected to the overcurrent protection transistor M3 and the gate drive circuit 21 and configured to stop the gate drive circuit 21 from providing a drive voltage to the plurality of first transistors M1-M3 when the current of the main power transistor M1 exceeds the current threshold TH1, thereby generating overcurrent protection for the main power transistor M1; and an overtemperature protection circuit 24, which is electrically connected to the gate drive circuit 21 and one or more second transistors M4-M6 and configured to stop the gate drive circuit 21 from providing a drive voltage to the plurality of first transistors M1-M3 when the temperature of any one of the one or more positions where the one or more second transistors M4-M6 are located exceeds the temperature threshold TH1, thereby forming overtemperature protection for the main power transistor M1.

[0042] In the embodiment of the present application, the driver chip 2 and the high-voltage power device 1 are packaged together through a system-in-package (SIP). The external structure of the SIP package is as follows: Figure 3B As shown,

[0043] The driver chip 2 is implemented by BCD (Bipolar-CMOS-DMOS) high-voltage process design and tape-out, and the high-voltage power device 1 is implemented by SGT or Trench process design and tape-out. Finally, the two are integrated by SIP. Figure 3B The figure shows a SIP integration method of a high-voltage power device 1 and a driver chip 2. The back of the high-voltage power device 1 is the drain (D) terminal. Figure 3B Terminals S1-S6 in are Figure 2A Terminals S1-S6, G1 are Figure 2A The gate terminals G1 and G2 are Figure 2A The gate terminal G2 in the circuit can be connected to the D terminal by bonding G2 (the gate of the MOS transistors M4-M6 for temperature detection) to the base island. The other ports are connected to the PAD corresponding to the driver chip 2 through the electrode pad PAD to achieve circuit connection.

[0044] Optionally, in a specific application, the S1 terminal of the main power transistor M1 of the intelligent power switch is also connected in series with an external inductor L load and the external resistor R load Inductance L load and resistor R loadThe setting method and parameters are similar to those of related intelligent power switches. load and resistor R load , the voltage and inductance on the intelligent power switch can be adjusted, which is not described in detail in this application.

[0045] The gate drive circuit 21 of the intelligent power switch of the present application is introduced below. Figure 4 , Figure 4 2 is a schematic diagram of the structure of the gate drive circuit of the intelligent power switch of the present application. The gate drive circuit 21 includes an input control logic 211, a level conversion circuit 212 and a driver 215, and the input control logic 211 is configured to receive an input control signal IN and output the input control signal IN to the level conversion circuit 212 when the input control signal IN of the input control logic 211 is at a first level.

[0046] The level conversion circuit 212 is configured to receive an input control signal IN from the input control logic 211, and generate a first control signal Dp according to the input control signal IN, wherein the first control signal Dp is used to enable the driver 215 to turn on or off multiple first transistors M1-M3. Vs is the system power supply, which is generally 4 to 28V, and its typical application value is 13.5V. Specifically, the input control logic 211 receives the input control signal IN from the outside, and the input control signal IN is a signal with a first level in the low voltage domain, such as a signal of 0 to 5V. The level conversion circuit 212 receives the input control signal IN from the input control logic 211, and converts the input control signal IN into a level signal Dp in the high voltage domain (the level signal Dp in the high voltage domain can be a level signal between Out and Vboot). The level signal Dp in the high voltage domain can control the driver 215 to turn on or off, and the driver 215 drives the gate capacitance of the MOS tubes M1-M3 to charge or discharge. When the driver 215 is turned on, the driver 215 outputs a high level, and the charging current charges the gate capacitance of the MOS tubes M1-M3, and the S G Pull it up to Vboot to turn on the power MOS tubes M1-M3. The driver 215 is turned off, that is, the driver 215 outputs a low level, and the discharge current discharges the gate capacitance of the MOS tubes M1-M3, turning on the S G Pull it down to Out to turn off the power MOS tubes M1-M3.

[0047] Optionally, the gate drive circuit 21 further includes a protection logic 213 and a charge pump 214. The protection logic 213 is electrically connected to an input terminal of the driver 215 and is configured to receive an overcurrent protection signal Sc_p from the overcurrent protection circuit 23, receive an overtemperature protection signal St_p from the overtemperature protection circuit 24, and generate a protection signal Sp according to the overcurrent protection signal Sc_p and the overtemperature protection signal St_p. The protection signal Sp can cause the driver 215 to discharge the gate capacitance of the main power tube M1, pull down the gate-source voltage Vgs of the main power tube M1 to 0, thereby turning off the power MOS tubes M1-M3, thereby achieving the purpose of protecting the power MOS tubes M1-M3.

[0048] Optionally, the gate drive circuit further includes a charge pump 214, the charge pump 214 includes an input end and an output end, the input end of the charge pump 214 is connected to the power supply Vs, and the output end of the charge pump 214 is connected to the driver 215 and the level conversion circuit 212. Figure 5A As shown. The charge pump 214 includes MOS transistors NM1 and NM2, MOS transistors PM1 and PM2, capacitor C1, capacitor C2 and Cout. The gate and drain of MOS transistor NM1 and MOS transistor NM2 are cross-connected, and the gate and drain of MOS transistor PM1 of the charge pump 214 are cross-connected with MOS transistor PM2. One end of capacitor C1 is electrically connected to the gate of MOS transistor PM2, and one end of capacitor C2 is electrically connected to the gate of MOS transistor PM1. The other end of capacitor C1 is connected to the first pulse signal input terminal clk1, and the other end of capacitor C2 is connected to the second pulse signal input terminal clk2. The charge pump 214 receives level pulse signals clk1 and clk2 from the outside through capacitors C1 and C2. The frequencies of level pulse signals clk1 and clk2 are the same and the phases are opposite. The voltage domain of clk1 and clk2 is Vs~Vs-5V. Using the characteristics of capacitance, capacitors C1 and C2 are charged through power supply Vs, so that the storage voltage on C1 and C2 is 5V. When the circuit charges the load capacitor Cout, the capacitors C1 and C2 discharge Cout alternately, raising the voltage on Cout from Vs to Vboot=Vs+5V. The charge pump 214 circuit adopts a cross-coupled charge pump structure, which alternately controls the charging and discharging of the capacitors C1 and C2 by switching the periodic level pulse signals clk1 and clk2, and uses the high-frequency clock signals clk1 and clk2 and the capacitor characteristics to generate a voltage Vboot higher than Vs, which supplies power to the driver 215 and the level conversion circuit 212.

[0049] refer to Figure 5B , Figure 5B2 is a schematic diagram of the structure of the gate driver 215. The driver 215 includes an AND gate and a cascade of multiple drivers with gradually increasing driving capabilities. When a driving signal is received (Dp is logic high) and the circuit is not protected (Sp is logic low), the driver outputs a high level to charge the gate capacitance of the power tubes M1-M3 and S G The output voltage is pulled up to Vboot, and the power MOS tubes M1-M3 are turned on. OUT is used to provide a "floating ground" for the driver.

[0050] The current detection function, overcurrent protection function and overtemperature protection function of the intelligent power switch of the present application are introduced below respectively.

[0051] Figure 6 2 is a schematic diagram of the structure of the current detection circuit 22 of the driver chip of the present application. Figure 6 As shown, the current detection circuit 22 of the driver chip 2 includes: a first operational amplifier 221, two input terminals of the first operational amplifier 221 are respectively connected to the source S terminal of the main power transistor M1 and the source S terminal of the current detection transistor M2, and are configured to clamp the source S terminal of the main power transistor M1 and the source S terminal of the current detection transistor M2 at the same voltage; a first current mirror 222, an input terminal of the first current mirror 222 is electrically connected to the source of the current detection transistor M2 and the output terminal of the first operational amplifier 221, and is configured to clamp the current I flowing through the current detection transistor M2 sense-load1 mirrored to the output end; a second current mirror 225, the input end of the second current mirror 225 is electrically connected to the output end of the first current mirror 222 and the current of the input end is mirrored to the output end; a first switch array 223, configured as the second current mirror 225 is electrically connected and controls the output current I of the current detection circuit 22 sense ; A first detector 224, configured to detect the output current I of the current detection circuit 22 sense , obtain the current I flowing through the main power transistor load .

[0052] Specifically, refer to Figure 6 The gate drive circuit 21 provides a gate drive voltage to the main power transistor M1 and the current detection transistor M2, thereby controlling the on and off of the main power transistor M1 and the current detection transistor M2. The positive input terminal In+ and the negative input terminal In- of the first operational amplifier 221 are connected to the source S terminal of the main power transistor M2 and the source S terminal of the current detection transistor M1, respectively. Figure 6In the embodiment, the positive input terminal In+ is connected to the S terminal of the current detection transistor M2, and the negative input terminal In- is connected to the S terminal of the main power transistor M1. However, it can be understood that the positive input terminal In+ of the first operational amplifier 211 of the present application can also be connected to the S terminal of the main power transistor M1, and the negative input terminal In- is connected to the S terminal of the current detection transistor M2. The present application will not be described in detail here.

[0053] The output terminal of the first operational amplifier 221 is connected to the control terminal of the first current mirror 222. The first operational amplifier 221 can play the role of opening and closing the first current mirror 222. The input terminal of the first current mirror 222 is connected to the S terminal of the current detection transistor M2, and is configured to convert the current I flowing through the current detection transistor M2 sense_load1 Mirrored to the output.

[0054] The input end of the second current mirror 225 is connected to the output end of the first current mirror 222. Specifically, the drain of the MOS transistor at the input end of the second current mirror 225 is connected to the source of the MOS transistor at the output end of the first current mirror 222, such as Figure 6 As shown, in this case, the current at the output end of the first current mirror 222 is the same as the current at the input end of the second current mirror 225. Specifically, the second current mirror 225 is a binary current mirror array, which includes multiple MOS tubes. The current in the NMOS tube M2 in the high-voltage domain of the input end is first mirrored to the current in the PMOS tube in the low-voltage domain of the output end through a 1:1 current mirror. The multiple PMOS tubes of the second current mirror 225 in the low-voltage domain adopt a binary ratio (1:2:4:8) of channel width-to-length ratio W / L, thereby realizing a binary ratio of mirror current (1:2:4:8). The working principle of the binary current mirror is the current replication mechanism. The drain-source current formula of the MOS tube is:

[0055]

[0056] Among them, V GS is the gate-source voltage; V TH is the threshold voltage of the MOS tube; μ n is the electron mobility in the conductive channel; C ox is the gate oxide potential area capacitance, which is a process-related parameter; W and L are the width and length of the MOS. The five PMOS tubes in the binary current mirror circuit have the same gate-source voltage V GS , using the same device in the same process, so V TH The same is true, so the drain-source current I in these PMOS can be obtained. D The ratio of is the ratio of its width to length ratio. Thus, by setting, a binary ratio (1:2:4:8) of the channel width to length ratio W / L is obtained, and a binary ratio of the mirror current (1:2:4:8) is obtained.

[0057] The binary current mirror array 225 is connected to the first switch array 223. The first switch array 223 includes a plurality of switches SW0-SW3 and SWn0-SWn3. The current sensing circuit 22 specifically includes a current sensing switch selector 224 configured to control the on or off of the switches SW0-SW3 and SWn0-SWn3, thereby generating a voltage V on the off-chip resistor Rsense. sense By detecting the off-chip resistor R sense The voltage V sense , the current I on the main power transistor M1 can be monitored in real time load In addition, the output current Isense of the current detection circuit 22 can be controlled by the current sensing switch selector 224, so that the output current of the current sensing circuit can be programmed.

[0058] In the embodiment of the present application, since the drain D end of the current detection transistor M2 and the main power transistor M1 use a common chip substrate, the gate G end is connected to the same potential, and the source S end is clamped at the same voltage through the first operational amplifier 221 in the driver chip 2. Since the active area of ​​the main power transistor M1 and the current detection transistor M2 is set to K:1, that is, the ratio of the number of cells of the main power transistor M1 and M2 is K:1, where K is greater than 1. When the current I load When , since the voltages at the D, G, and S terminals of the current detection transistor M2 are the same as the voltages at the D, G, and S terminals of the main power transistor M1, and the ratio of the number of cells is 1 / K, the current passing through the current detection transistor M2 is I sense_load1 =I load / k. In the driver chip 2, the current I is generated by the current mirror method. sense_load1 The current is mirrored to the second current mirror 225 and controlled by the current switches SW0-SW3 or SWn0-SWn3. sense The voltage V sense .

[0059] V sense =R sense I load / k(1*SW0+2*SW1+4*SW2+8*SW3)

[0060] The current detection circuit 22 further includes a first detector 226 configured to detect the current of the off-chip resistor R sense The voltage V sense , can monitor the current flowing through the main power transistor M1 (i.e. the current flowing through the load R load ) current I load Optionally, an off-chip resistor R senseThe current passing through is controlled by current switches SW0-SW3 or SWn0-SWn3, thereby realizing a programmable control function.

[0061] Figure 7 2 is a schematic diagram of the structure of the overcurrent protection circuit 23 of the driver chip of the present application. Figure 7 As shown, the overcurrent protection circuit 23 of the driver chip 2 includes: a second operational amplifier 231, two input terminals of the second operational amplifier 231 are respectively connected to the source S terminal of the main power transistor M1 and the source S terminal of the overcurrent protection transistor M3, and are configured to clamp the source S terminal of the main power transistor M1 and the source S terminal of the overcurrent protection transistor M3 at the same voltage; a third current mirror 232, which is electrically connected to the source of the overcurrent protection transistor M3 and the output terminal of the second operational amplifier 231 and is configured to clamp the current I in the overcurrent protection transistor M3 sense-load2 A fourth current mirror 236, the input end of the fourth current mirror 236 is connected to the output end of the third current mirror 232 and is configured to flow through the overcurrent protection transistor M3 of the current I sense-load2 The second switch array 233 is configured to be electrically connected to the output end of the fourth current mirror 236 and to control the output current I of the overcurrent protection circuit 23 oc ; The first comparator 234 is configured to compare the voltage on the off-chip resistor Roc with the first reference voltage and output the comparison result; the overcurrent protection logic 235 is configured to be connected to the output end of the first comparator 234, and when the comparison result exceeds the temperature threshold TH2, the gate drive circuit 21 outputs a signal to turn off the first transistor M1, thereby generating overcurrent protection for the main power transistor M1.

[0062] Specifically, refer to Figure 7 The gate drive circuit 21 provides a gate drive voltage to the main power transistor M1 and the overcurrent protection transistor M3, thereby controlling the on and off of the main power transistor M1 and the overcurrent protection transistor M3. The negative input terminal In- and the positive input terminal In+ of the second operational amplifier 231 are connected to the source S terminal of the main power transistor M1 and the source S terminal of the overcurrent protection transistor M3, respectively. Figure 7 In the embodiment, the positive input terminal In+ is connected to the S terminal of the overcurrent protection transistor M3, and the negative input terminal In- is connected to the S terminal of the main power transistor M1. However, it can be understood that the positive input terminal In+ of the second operational amplifier 231 of the present application can also be connected to the S terminal of the main power transistor M1, and the negative input terminal In- is connected to the S terminal of the overcurrent protection transistor M3. The present application is not described in detail here. The output terminal of the second operational amplifier 231 is connected to the input terminal of the third current mirror 232. The input terminal of the third current mirror 232 is connected to the S terminal of the overcurrent protection transistor M3, and is configured to convert the current I flowing through the overcurrent protection transistor M3 sense_load2 Mirrored to the output.

[0063] Specifically, the input end of the fourth current mirror 236 is connected to the output end of the third current mirror 232. The drain of the MOS transistor at the input end of the fourth current mirror 236 is connected to the source of the MOS transistor at the output end of the third current mirror 232, such as Figure 7 As shown, in this case, the current at the output end of the third current mirror 232 is the same as the current at the input end of the fourth current mirror 236. Specifically, the fourth current mirror 236 is a binary current mirror array, which includes multiple MOS tubes. The current in the PMOS tube in the high-voltage domain of the input end is first mirrored to the current in the PMOS tube in the low-voltage domain of the output end through a 1:1 current mirror. The multiple PMOS tubes in the low-voltage domain adopt a binary ratio (1:2:4:8) of channel width-to-length ratio W / L, thereby realizing a binary ratio mirror current (1:2:4:8). The working principle of the binary current mirror is the current replication mechanism. The drain-source current formula of the MOS tube is:

[0064]

[0065] Among them, V GS is the gate-source voltage; V TH is the threshold voltage of the MOS tube; μ n is the electron mobility in the conductive channel; C ox is the gate oxide potential area capacitance, which is a process-related parameter; W and L are the width and length of the MOS. The five PMOS tubes in the binary current mirror circuit have the same gate-source voltage V GS , using the same device in the same process, so V TH The same is true, so the drain-source current I in these PMOS can be obtained. D The ratio of is the ratio of its width to length ratio. Thus, by setting, a binary ratio (1:2:4:8) of the channel width to length ratio W / L is obtained, and a binary ratio of the mirror current (1:2:4:8) is obtained.

[0066] The binary current mirror array 236 is connected to the second switch array 233. The second switch array 233 includes a plurality of switches SW0-SW3 and SWn0-SWn3. The overcurrent protection circuit 23 specifically includes an overcurrent protection switch selector 234, which is configured to control the on or off of the switches SW0-SW3 and SWn0-SWn3, thereby controlling the magnitude of the current Ioc flowing through the off-chip resistor Roc in a programmable manner, so that a voltage V is generated on the off-chip resistor Roc. oc The first comparator 234 compares the voltage Voc on the off-chip resistor Roc with the first reference voltage V refThe overcurrent protection logic 235 obtains the comparison result from the second comparator 234; when the comparison result exceeds the current threshold TH2, the gate drive circuit 21 outputs a signal to turn off the main power transistor M1, thereby generating overcurrent protection for the main power transistor M1.

[0067] In some embodiments, the overcurrent protection switch selector 234 can select the on or off of the switches SW0 - SW3 or the on or off of the switches SWn0 - SWn3 , thereby adjusting the output current of the overcurrent protection circuit.

[0068] In the embodiment of the present application, since the drain D end of the overcurrent protection transistor M3 and the main power transistor M1 use a common chip substrate, the gate G end is connected to the same potential, and the source S end is clamped at the same voltage through the second operational amplifier 231 in the driver chip 2. Since the active area of ​​the main power transistor M1 and the overcurrent protection transistor M3 is set to N:1, that is, the ratio of the number of cells of the main power transistor M1 and M3 is N:1, where N is greater than 1. When the current I load When , since the voltages at the D, G, and S terminals of the overcurrent protection transistor M3 are the same as the voltages at the D, G, and S terminals of the main power transistor M1, and the ratio of the number of cells is 1 / N, the current passing through the overcurrent protection transistor M3 is I sense_load2 =I load / N. In the driver chip 2, the current I is generated by the current mirror method. sense_load2 The current is mirrored to the binary current mirror array 232 and controlled by the current switches SW0-SW3 or SWn0-SWn3. oc The voltage V oc .

[0069] V oc =R oc I load / N(1*SW0+2*SW1+4*SW2+8*SW3)

[0070] The second comparator 234 converts the voltage V oc With reference voltage V ref A comparison is performed and the comparison result is output to the overcurrent protection logic 235. When the voltage exceeds the current threshold TH2, the overcurrent protection logic 235 controls the gate drive circuit 21 to turn off the main power transistor M1, thereby generating overcurrent protection for the main power transistor M1.

[0071] Figure 8 Schematic diagram of the over-temperature protection circuit of the present application. Figure 8As shown, the driver chip 2 includes one or more over-temperature protection circuits 24. The number of the one or more over-temperature protection circuits 24 is the same as the number of the one or more second transistors, and the one or more over-temperature protection circuits 24 correspond to the one or more second transistors one by one. Each over-temperature protection circuit 24 includes: a current source 241, configured to generate a current I ref , the current I ref It can be microampere uA level (1uA~10uA); the fifth current mirror 242 is configured to convert the current I ref The output terminal Iout includes one or more third transistors. Figure 8 In the embodiment, the input end of the fifth current mirror 242 includes a transistor M7, and the output end includes three transistors M8-M10. The ratio of the channel lengths of the three transistors M8-M10 is 1:1:1, so that the same current (1:1:1) is obtained. The ratio of the channel length of the first transistor M7 to the channel length of the three transistors M8-M10 is 1:1:1:1, so that the current I ref Mirrored to transistors M8-M10.

[0072] In some embodiments, the over-temperature protection circuit 24 further includes a third switch array 243, and the third switch array 243 includes one or more switches. Figure 8 2 and 3. It is shown that the third switch array 243 includes three switches S8-S10, which are connected to transistors M8-M10 respectively.

[0073] In some embodiments, the over-temperature protection circuit 24 further includes a load 244, a first end of the load 244 is connected to the source S end of the over-temperature protection transistor M4, and a second end of the load 244 is connected to the source end of the third transistor M8-M10. By controlling the switches S8-S10, a load current I sense_temp The over-temperature protection transistor M4 is connected in a diode manner, that is, the drain and the gate are connected to a common electrode, so that the over-temperature protection transistor M4 operates in a saturation region, and a voltage V is generated across the drain and source of the over-temperature protection transistor M4. DS ,

[0074]

[0075] Among them, V GS is the gate-source voltage; I sense_temp is the drain-source current in M4; μ n is the electron mobility in the conductive channel; C ox is the gate oxide layer potential area capacitance, which is a process-related parameter; W and L are the width and length of the MOS; V TH is the threshold voltage of the MOS tube M4.TH Has a negative temperature coefficient. When the temperature rises, V TH Reduce, V DS decreases, thereby increasing the voltage at the second end of the load 244,

[0076] In some embodiments, the over-temperature protection circuit 24 further includes: a second comparator 245 configured to compare a reference voltage V generated by the bandgap and having no relation to temperature with a reference voltage V ref2 A comparison is performed and a comparison result is generated; the over-temperature protection logic 246 is configured to obtain a comparison result from the second comparator 245, and when the temperature exceeds the temperature threshold TH2, the over-temperature protection logic 246 causes the gate drive circuit 21 to stop providing a drive voltage to the main power transistor M1, thereby generating over-temperature protection for the main power transistor M1.

[0077] Based on the shielded gate trench SGT / Trench process, metal-oxide semiconductor field effect transistors MOS of different sizes are designed, and the current detection device is integrated into the vertical double diffused metal oxide semiconductor device VDMOS transistor, which makes the current detection more accurate on the one hand. On the other hand, the system integration is improved. Based on the SGT / Trench process, multiple MOS of different sizes are designed, and the temperature sensing device is integrated into the VDMOS transistor. On the one hand, the temperature monitoring is more accurate, and on the other hand, the error caused by the position deviation or thermal conduction delay of the external temperature sensor can be avoided by arranging the temperature sensing MOS at different positions of the power tube, and the system integration is improved. In addition, the driver chip in the power switch of the present application controls the temperature protection, overcurrent protection, and current detection ratio in a programmable manner, which increases the flexibility of system application and the actual scope of use.

[0078] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An integrated high-voltage power device, comprising: a plurality of first transistors; as well as one or more second transistors integrated with the plurality of first transistors, wherein the drains of the plurality of first transistors are electrically connected to the drains of the one or more second transistors, the gates of the plurality of first transistors are electrically connected, and the gates of the one or more second transistors are electrically connected, The one or more second transistors are distributed at one or more locations of the high-voltage power device and are configured to detect temperatures of the one or more locations.

2. The high voltage power device according to claim 1, wherein: The plurality of first transistors include: a main power transistor configured to allow external current to flow through the high voltage power device; a current detection transistor configured to detect a current flowing through the high voltage power device; and An overcurrent protection transistor is configured to perform overcurrent protection on the main power transistor.

3. The high voltage power device according to claim 2, wherein: The ratio between the areas of the active area of ​​the main power transistor and the active area of ​​the current detection transistor is K:1; A ratio between the active area of ​​the main power transistor and the active area of ​​the overcurrent protection transistor is N:1, where both K and N are greater than 1.

4. The high voltage power device according to claim 2, wherein: The main power transistor and the overcurrent detection transistor share a first chip substrate; The main power transistor and the current detection transistor share a second chip substrate.

5. The high voltage power device according to claim 4, wherein: The first chip substrate and the second chip substrate are the same chip substrate.

6. A power switch, comprising: The high voltage power device according to claim 2; as well as Driver chip, including: a gate driving circuit electrically connected to the plurality of first transistors and configured to provide a gate driving voltage to the gates of the plurality of first transistors; a current detection circuit, electrically connected to the current detection transistor and configured to detect a current flowing through the main power transistor; an overcurrent protection circuit, electrically connected to the overcurrent protection transistor and the gate drive circuit, and configured to cause the gate to be switched off when the current in the main power transistor exceeds a current threshold. The driving circuit stops providing the driving voltage to the plurality of first transistors, thereby achieving over-current protection; and One or more over-temperature protection circuits are electrically connected to the gate drive circuit and the one or more second transistors, wherein each of the one or more over-temperature protection circuits is configured to cause the gate drive circuit to stop providing a drive voltage to the multiple first transistors when the temperature at any one of the one or more positions exceeds a temperature threshold, thereby achieving over-temperature protection.

7. The power switch according to claim 6, wherein: The gate drive circuit comprises: a level conversion circuit configured to receive an input control signal and generate a first control signal according to the input control signal; a protection logic, wherein an input end of the protection logic is electrically connected to the overcurrent protection circuit and the one or more overtemperature protection circuits, and is configured to receive an overcurrent protection signal from the overcurrent protection circuit, receive an overtemperature protection signal from the one or more overtemperature protection circuits, and generate a protection signal according to the overcurrent protection signal and the overtemperature protection signal; a driver, electrically connected to the level conversion circuit and the protection logic, and configured to turn on or off the plurality of first transistors according to the protection signal and the first control signal; A charge pump is electrically connected to the driver and the level conversion circuit and is configured to supply power to the driver and the level conversion circuit.

8. The power switch according to claim 6, wherein: The current detection circuit comprises: A first operational amplifier, wherein two input terminals of the first operational amplifier are electrically connected to the source of the main power transistor and the source of the current detection transistor respectively; a first current mirror, wherein an input terminal of the first current mirror is electrically connected to a source of the current detection transistor and an output terminal of the first operational amplifier; a second current mirror, wherein an input terminal of the second current mirror is electrically connected to an output terminal of the first current mirror; a first switch array electrically connected to the output terminal of the second current mirror and comprising a plurality of first switches, wherein one or more of the plurality of first switches are selectively turned on or off; The first detector is electrically connected to the first switch array and detects a current flowing through the main power transistor.

9. The power switch according to claim 6, wherein: The overcurrent protection circuit comprises: A second operational amplifier, wherein two input terminals of the second operational amplifier are electrically connected to the source of the main power transistor and the source of the overcurrent protection transistor respectively; a third current mirror, wherein an input terminal of the third current mirror is electrically connected to a source of the overcurrent protection transistor and an output terminal of the second operational amplifier; a fourth current mirror, wherein an input terminal of the fourth current mirror is electrically connected to an output terminal of the third current mirror; a second switch array electrically connected to the output terminal of the fourth current mirror and comprising a plurality of second switches, wherein one or more of the plurality of second switches are selectively turned on or off; a first comparator, electrically connected to one end of the second switch array, and comparing a voltage at the one end of the second switch array with a reference voltage to obtain a comparison result; The overcurrent protection logic is electrically connected to the output terminal of the first comparator, and enables the gate driving circuit to stop providing the driving voltage to the plurality of first transistors when the comparison result exceeds the current threshold.

10. The power switch according to claim 6, wherein: Each of the one or more over-temperature protection circuits comprises: a current source configured to generate a current that is independent of temperature changes; a fifth current mirror, wherein an input terminal of the fifth current mirror is electrically connected to the current source; A third switch array, comprising a plurality of third switches, each of the plurality of third switches being electrically connected to a corresponding one of the plurality of output terminals of the fifth current mirror; a first resistor, wherein a first end of the first resistor is electrically connected to a source of a corresponding one of the one or more over-temperature protection transistors; a second comparator, electrically connected to the second end of the first resistor and configured to compare the voltage of the second end with a reference voltage to obtain a comparison result; and The over-temperature protection logic is electrically connected to the output terminal of the second comparator and is configured to enable the gate driving circuit to stop providing the driving voltage to the plurality of first transistors when the comparison result exceeds a specific threshold.

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