Manufacturing method of one-step adjustable bidirectional large-through-flow TVS (Transient Voltage Suppressor) device

Abstract

The invention belongs to the field of design and manufacturing of semiconductors / integrated circuits, and particularly relates to a manufacturing method of a one-step adjustable bidirectional large-through-flow TVS (Transient Voltage Suppressor) device. A doped silicon substrate with specific crystal orientation and resistivity is selected, an epitaxial layer is generated, then an oxide layer is formed through thermal oxidation or chemical vapor deposition, a groove is formed through photoetching and etching, and doped polycrystalline silicon is filled and sealed. And then etching to remove surface doped silicon, performing high-temperature diffusion and junction pushing, depositing an oxide layer, forming a through hole, filling conductive metal, depositing metal, etching to form an electrode, and performing related operation of a back electrode on a specific TVS (Transient Voltage Suppressor). The required groove type device structure is formed in one step, the chip area can be reduced by more than 30% compared with a plane structure, meanwhile, the PN junction structure formed in one step can meet the requirement for consistent symmetry of breakdown voltage, the clamping voltage Vc can be accurately controlled, and meanwhile the surge current absorption capacity of the TVS can be improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor / integrated circuit design and manufacturing, and specifically is a one-step adjustable bidirectional large through-current TVS device manufacturing method. Background Art

[0002] TVS, also known as transient voltage suppression diode, is a high-efficiency protection device in the form of a diode, used in parallel with the protected circuit. When subjected to transient high-energy impact, TVS can instantly change from high resistance to low resistance, absorb up to several kilowatts of surge power, and clamp the voltage between the two poles to a predetermined value, effectively protecting the precision components in the electronic circuit from damage by various surge pulses. The current conventional bidirectional TVS device is a typical planar structure, as shown in the figure below. The process requires multiple lithography, ion implantation and diffusion processes. The two PN junctions cannot be formed at one time and each heat treatment has a greater impact on the breakdown voltage. The difference in the doping concentration distribution of the PN junction will also cause the clamping voltage Vc to be inconsistent in two directions, affecting the device parameters. Summary of the invention

[0003] In view of the shortcomings of the prior art, the present invention proposes a one-step adjustable bidirectional large through-current TVS device manufacturing method. This method forms the required trench device structure in one step by changing the mask pattern, and the chip area can be reduced by more than 30% compared with the planar structure. At the same time, the one-time formed PN junction structure can meet the requirements of consistent symmetry of the breakdown voltage, can accurately control the clamping voltage Vc, and can increase the surge current absorption capacity of the TVS.

[0004] The technical solution of the present invention is as follows:

[0005] A one-step method for manufacturing a bidirectional large through-current TVS device that can be controlled, comprising:

[0006] Selecting a doped silicon substrate and determining the resistivity of the doped silicon substrate, and generating an epitaxial layer on the doped silicon substrate that is inverse to the substrate;

[0007] forming an oxide layer on the surface of the epitaxial layer by thermal oxidation or chemical vapor deposition process;

[0008] Through photolithography and etching processes, grooves of specific shape and depth are formed on the epitaxial layer;

[0009] Through a deposition process, doped polysilicon that is inversely proportional to the epitaxial layer is filled into the trench and sealed;

[0010] The surface doped silicon is removed by etching process until the surface of the epitaxial layer is reached, and then the junction is pushed by high-temperature diffusion;

[0011] Through a deposition process, an oxide layer is deposited on the epitaxial layer as a through-hole dielectric layer, through holes are opened at each groove position through photolithography and etching processes, and conductive metal is filled in the through holes;

[0012] Through the deposition process, metal is deposited on the through-hole dielectric layer, and the metal between the through-holes is etched away through the photolithography and etching processes. After the final passivation treatment, the electrode is led out from the front to form a bidirectional TVS device.

[0013] Furthermore, the doped silicon substrate is selected <100> or <111> The silicon material has a crystal orientation, the resistivity of the doped silicon substrate is selected within the range of 0.001 to 0.006 Ω.cm, and the thickness of the epitaxial layer is 2 to 20 um.

[0014] Furthermore, the oxide layer is 100-10000A.

[0015] Furthermore, the groove is in a rectangular, square, circular, elliptical or polygonal shape.

[0016] Furthermore, the grooves are divided into equal depth grooves and unequal depth grooves;

[0017] Among them, for equal-depth grooves, equal-width layouts are designed and etched according to the etching process;

[0018] Among them, for grooves of unequal depth, that is, deep grooves go deep into the substrate and shallow grooves go deep into the epitaxial layer, the etching time required to make the grooves deep into the substrate is first calculated based on the etching rate, and the width of the shallow trench layout is reversed under the condition of the required shallow trench depth. The unequal width layout is designed. When etching, the deep groove is first etched to the substrate, and then the etching is adjusted according to the requirements of the unequal depth grooves.

[0019] Furthermore, during the sealing process, doped polysilicon is continuously deposited to form a flat surface above the trench, thereby completely sealing the trench.

[0020] Furthermore, the high temperature diffusion temperature is 900-1200°C, and the diffusion time is 10-90min;

[0021] The high temperature diffusion push-in junction causes two adjacent doped silicons and the formed doped region and the intermediate epitaxial region to undergo a diffusion reaction at high temperature, and the diffusion reaction standard is:

[0022] Ensure that the distance between the two trenches does not hold hands in the diffusion area formed after high-temperature diffusion, and there is still an epitaxial area with a certain gap in the middle to form a bidirectional TVS device unit.

[0023] Furthermore, the thickness of the through-hole dielectric layer is 2-3 um, and metal W or Mo is selected to fill the through-hole.

[0024] Furthermore, for the deep trenches that penetrate deep into the substrate, through holes are opened at the shallow trenches in the deep trenches and filled with metal.

[0025] Furthermore, the metal deposited on the through-hole dielectric layer includes AlCu or AlSiCu; the deposition thickness is 3-5 um;

[0026] For the deep grooves in the grooves that penetrate into the substrate, the back side of the substrate is ground and thinned, and then multiple layers of metal TiNiAg or TiNiSnCuAg are deposited to form a back electrode with a thickness of 2-10 um.

[0027] The beneficial effects of the present invention are as follows: 1. The present invention only requires one photomask in the front-end process, which greatly reduces the number of photomasks and avoids inaccurate electrical properties of the device caused by photolithography alignment deviation.

[0028] 2. The present invention can form grooves of different sizes and depths by simply changing the mask pattern in one step to meet various electrical requirements such as breakdown voltage and clamping voltage, and has one-step controllability.

[0029] 3. In the present invention, the PN junction formed by the trench filling with doped polysilicon has a uniform doping concentration distribution and a highly symmetrical and consistent junction voltage.

[0030] 4. The chip area of ​​the trench longitudinal PN junction structure of the present invention can be reduced by more than 30% compared with the planar PN junction structure.

[0031] 5. The present invention can increase the trench PN junction area by increasing the thickness of the epitaxial layer, thereby further improving the surge current absorption capacity of the device without increasing the chip area.

[0032] 6. In the present invention, the device with deep and shallow grooves has two current discharge channels, a channel T1 between the surfaces of two adjacent PN junction grooves, and a channel T2 from the surface of the PN junction groove through the substrate to the adjacent PN junction. The two discharge channels can also increase the current discharge capacity and efficiency.

[0033] 7. Two lead methods can provide two packaging methods, and the packaging is optional. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is the overall flow chart of the present invention;

[0035] Figure 2 It is a schematic diagram of the structure of doped silicon substrate and epitaxial layer;

[0036] Figure 3 Schematic diagram of the process of forming an oxide layer by thermal oxidation or chemical vapor deposition;

[0037] Figure 4Schematic diagram of the oxide layer and epitaxial layer structure before photolithography and trench etching;

[0038] Figure 5 It is a schematic diagram of photoresist coating and trench pattern exposure;

[0039] Figure 6 is a schematic diagram of the trench structure formed on the oxide layer and the epitaxial layer;

[0040] Figure 7 Schematic diagram of the trench structure after being filled with doped polysilicon;

[0041] Figure 8 Schematic diagram of removing surface doped silicon and high temperature diffusion junction pushing;

[0042] Fig. 9 Schematic diagram of the structure after depositing an oxide layer and opening through holes to fill them with conductive metal. DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0044] See also Figure 1 , which shows a one-step adjustable bidirectional large through-current TVS device manufacturing method provided by an embodiment of the present invention, comprising:

[0045] S100: selecting a doped silicon substrate and determining the resistivity of the doped silicon substrate, and generating an epitaxial layer on the doped silicon substrate that is inverse to the substrate.

[0046] S200: forming an oxide layer on the surface of the epitaxial layer by thermal oxidation or chemical vapor deposition process.

[0047] S300: A groove of a specific shape and depth is formed on the epitaxial layer through photolithography and etching processes.

[0048] S400: Through a deposition process, doped polysilicon having an inverse type to the epitaxial layer is filled into the trench and sealed.

[0049] S500: The surface doped silicon is removed by etching process, and the surface of the epitaxial layer is etched, and then the junction is pushed to meet the required junction voltage performance by high-temperature diffusion. Two adjacent doped silicons and the formed doped regions and the epitaxial region between the doped regions constitute a bidirectional TVS device unit.

[0050] S600: depositing an oxide layer as a through-hole dielectric layer on the epitaxial layer through a deposition process, opening through holes at each groove position through photolithography and etching processes, and filling the through holes with conductive metal.

[0051] S700: Through a deposition process, metal AlCu or AlSiCu is deposited on the through-hole dielectric layer, and the metal between the through-holes is etched away through a photolithography and etching process. After a final passivation treatment, the electrode is led out from the front to form a bidirectional TVS device.

[0052] S100 involves selecting a doped silicon substrate with a specific crystal orientation and resistivity, and then generating an epitaxial layer on the substrate that is inverse to the substrate. Selecting a silicon substrate with a specific crystal orientation ensures good electrical and mechanical properties, and the appropriate resistivity range can prevent the device from powering too much and preventing the breakdown voltage from being too low. By selecting an epitaxial layer material that is inverse to the substrate and a suitable thickness, and controlling the doping concentration of the epitaxial layer to be lower than the doping concentration of the substrate, it is possible to ensure that the epitaxial layer has a suitable resistivity and breakdown voltage, laying the foundation for the subsequent manufacture of high-performance, one-step adjustable, bidirectional, large-current TVS devices.

[0053] S100 specifically includes the following steps:

[0054] S110: Select the material and resistivity of the silicon substrate.

[0055] <100> or <111> The silicon material with good electrical and mechanical properties is selected <100> or <111> crystal orientation of a doped silicon substrate.

[0056] A resistivity that is too low will result in excessive power consumption of the device, and a resistivity that is too high will result in a too low breakdown voltage of the device. Therefore, a doped silicon substrate with a resistivity in the range of 0.001 to 0.006 Ω.cm is selected.

[0057] At the same time, the surface of the doped silicon substrate is ensured to be flat and smooth, without scratches, impurities and other defects, so as to ensure the growth quality of the epitaxial layer and the performance of the device.

[0058] S120: Generate an epitaxial layer on the doped silicon substrate that is inverse to the substrate, such as Figure 2 shown.

[0059] In one possible implementation, the epitaxial layer is grown using chemical vapor deposition or molecular beam epitaxy.

[0060] The epitaxial layer material is selected to be doped silicon with an inverse type to the substrate. Exemplarily, a p-type epitaxial layer is grown on an n-type doped silicon substrate, and vice versa.

[0061] The thickness of the epitaxial layer is determined according to the device design requirements, such as breakdown voltage, current density, etc. Specifically, the thickness of the epitaxial layer is 2 to 20 um.

[0062] To ensure that the epitaxial layer has a suitable resistivity and breakdown voltage, the doping concentration of the epitaxial layer is lower than the doping concentration of the substrate.

[0063] S130: Substrate and epitaxial layer cleaning and inspection

[0064] Use chemical cleaning fluid to remove impurities and organic matter on the surface of the doped silicon substrate and epitaxial layer, such as oxide layer, hydrocarbons, etc., and then use deionized water to rinse to remove the chemical cleaning fluid residue to ensure the surface is clean.

[0065] Detect the resistivity, cleanliness, lattice structure and orientation of the doped silicon substrate and epitaxial layer to ensure that they meet the design requirements. For example, the resistivity of the substrate and epitaxial layer is measured using a four-probe method. Use a microscope to observe the surface of the substrate and epitaxial layer to ensure that there are no defects such as scratches and impurities. Use X-ray diffraction technology to detect the lattice structure and orientation of the epitaxial layer to ensure that it matches the substrate lattice.

[0066] S200 is to form an oxide layer on the surface of the epitaxial layer, and the oxide layer is used as an oxide mask film and is required for trench etching.

[0067] S200 specifically includes the following steps:

[0068] S210: According to actual needs and process conditions, a thermal oxidation or chemical vapor deposition process is selected to form an oxide layer.

[0069] The thermal oxidation process can use oxygen or water vapor to react with the silicon substrate at high temperature to form an oxide layer, which has the advantages of high quality of the oxide layer and close bonding with the substrate. The specific operation is: put the cleaned substrate and epitaxial layer into a high-temperature furnace, pass oxygen or water vapor for oxidation, and form Figure 3 The SiO2 layer shown.

[0070] Chemical vapor deposition is the process of forming an oxide layer by chemically reacting gaseous reactants on the substrate surface. It can be carried out at a relatively low temperature and can precisely control the thickness and composition of the oxide layer. The substrate and epitaxial layer are placed in a chemical vapor deposition device, and reaction gases such as SiH4 and O2 are introduced to form an oxide layer at a relatively low temperature. Figure 3 The SiO2 layer shown.

[0071] S220: Determine the thickness of the oxide layer.

[0072] The oxide layer acts as an oxide mask, forming an oxide layer of 100-10000A on the surface of the epitaxial layer.

[0073] S300 forms grooves of specific shape and depth on the epitaxial layer through photolithography and etching processes to realize the internal structure of the device. This structure can achieve bidirectional conduction and has the characteristics of low on-resistance and low leakage current. At the same time, the performance of the device can be controlled by adjusting the shape and size of the groove.

[0074] S300 specifically includes the following steps:

[0075] S310: Select the shape and size of the groove according to design requirements.

[0076] The shape of the groove can be rectangular, square, circular, elliptical, or polygonal. The size of the groove includes the width of the groove, the spacing between the grooves, and the depth of the groove. Figure 4 As shown, the groove is a rectangular groove.

[0077] In one possible implementation, for equal-depth grooves, equal-width layouts are designed; for unequal-depth grooves, i.e., deep grooves go deep into the substrate and shallow grooves go deep into the epitaxial layer, the etching time required to meet the requirements of deep-depth grooves in the substrate is first calculated based on the etching rate, and the width of the shallow groove layout is reversed under the required shallow groove depth to design unequal-width layouts. Then, the photoresist is exposed through a mask with a designed pattern using a photolithography process. During the exposure process, the exposure dose and focus depth are precisely controlled to ensure that the photoresist can form a clear and accurate potential groove pattern after exposure. The exposed photoresist is developed to remove the unexposed or underexposed photoresist portion, thereby showing the groove pattern on the photoresist layer.

[0078] Exemplarily, an electronic design automation (EDA) tool is used to draw a layout of the trench pattern and convert the layout into a photoresist plate.

[0079] S320: according to the groove pattern on the photoresist, use an etching process to etch a groove on the epitaxial layer.

[0080] In one possible implementation, for equal-depth grooves, etching is performed according to a conventional etching process, and the etching rate and time are controlled to achieve the desired groove depth. For unequal-depth grooves, etching is performed according to the designed unequal-width layout and the calculated etching time, first etching the deep groove to the substrate, and then adjusting the etching according to the requirements of the shallow groove.

[0081] In some possible implementations, the etching process is selected as dry etching or wet etching, and the etchant is selected as CF4 or HBr.

[0082] After etching is completed, use a microscope or scanning electron microscope to check the shape, size and depth of the trench to ensure that it meets the design requirements.

[0083] S330: After the trench etching is completed, the oxide layer is removed.

[0084] Use chemical solutions or dry etching processes to remove the oxide layer while ensuring that the trench and epitaxial layer are not damaged. After removing the oxide layer, the trench is cleaned and dried.

[0085] S400 uses chemical vapor deposition, physical vapor deposition or plasma enhanced chemical vapor deposition to fill the trench with doped polysilicon that is inversely proportional to the epitaxial layer and seal it. Sealing helps improve the performance and reliability of bidirectional large-through-current TVS devices, meet different design requirements, and improve the overall manufacturing quality and electrical performance of the device.

[0086] S400 specifically includes the following steps:

[0087] S410: According to the process requirements, select a doped polysilicon material that is inversely related to the epitaxial layer.

[0088] Exemplarily, if the epitaxial layer is n-type, the doped polysilicon should be p-type; conversely, if the epitaxial layer is p-type, the doped polysilicon should be n-type.

[0089] S420: Select a deposition process and equipment required for the corresponding deposition process, set deposition parameters according to the characteristics of the doped polysilicon and the required deposition effect, and perform trench filling deposition.

[0090] In one possible implementation, chemical vapor deposition, physical vapor deposition or plasma enhanced chemical vapor deposition is selected.

[0091] Suitable deposition parameters include deposition temperature, pressure, reaction gas type and flow rate to control the deposition rate, doping concentration and grain size of polysilicon.

[0092] The prepared epitaxial layer and the structure with the groove are placed in a deposition device, and the deposition process is started to fill the doped polysilicon into the groove. During the deposition process, it is ensured that the doped polysilicon can be evenly filled into all parts of the groove to avoid voids, gaps or uneven filling. Exemplarily, uniform filling is achieved by adjusting the nozzle position, gas distribution, etc. of the deposition device.

[0093] S430: After the groove is filled, a sealing process is performed.

[0094] During the sealing process, the thickness and quality of the deposition must be controlled to ensure that the surface after sealing is flat and smooth, integrated with the surrounding epitaxial layer surface, and will not have an adverse effect on subsequent process steps.

[0095] In a possible implementation, doped polysilicon is continuously deposited to form a flat surface above the trench, thereby completely sealing the trench. Figure 5 shown.

[0096] S500 uses an etching process to remove the doped silicon on the surface of the epitaxial layer to the surface of the epitaxial layer, with an epitaxial region in the middle to form a bidirectional TVS device unit. This step can effectively adjust the junction voltage performance by precisely controlling the etching depth and high-temperature diffusion conditions, ensuring the formation of a bidirectional TVS device unit that meets the requirements, laying the foundation for the subsequent manufacture of high-quality bidirectional large-current TVS devices, and improving the electrical performance and stability of the device.

[0097] S500 specifically includes the following steps:

[0098] S510: using an etching process to remove the doped silicon on the surface of the epitaxial layer, etching to the surface of the epitaxial layer.

[0099] During the etching process, the etching depth must be closely monitored to ensure that it is etched just to the surface of the epitaxial layer and to avoid over-etching into the interior of the epitaxial layer.

[0100] S520: After the surface doped silicon etching is completed, prepare the high temperature diffusion process, the diffusion temperature is 900-1200°C, and the diffusion time is 10-90 minutes. Start the high temperature diffusion process to make the two adjacent doped silicon and the formed doped area and the middle epitaxial area diffuse at high temperature to meet the required junction voltage performance.

[0101] At the same time, it is necessary to ensure that the spacing between the two trenches does not hold hands in the diffusion area formed after high-temperature diffusion, and there is still an epitaxial area with a certain gap in the middle to form a bidirectional TVS device unit. If it is found that the diffusion area has a tendency to hold hands, the diffusion temperature or time can be appropriately adjusted, or the spacing design of the trenches can be improved to form a bidirectional TVS device unit. Figure 6 The structure shown.

[0102] S530: After the high-temperature diffusion is completed, the sample is tested to check whether the diffusion area meets the design requirements, including the shape, size and junction voltage performance of the diffusion area.

[0103] S600 deposits an oxide layer as a through-hole dielectric layer on the surface of the sample through a deposition process, and then forms through-holes at each groove position through steps such as photoresist coating, through-hole pattern design and photolithography exposure, development, and oxide layer etching. Finally, a suitable conductive metal is selected and filled into the through-hole through corresponding equipment and processes. This step can accurately control the deposition thickness of the oxide layer and the formation process of the through-hole, ensuring that the through-hole position is accurate, the size is appropriate, and the filling is uniform, laying the foundation for subsequent electrode extraction and optimization of the electrical performance of the device, improving the stability and reliability of the device, and at the same time, each step is closely connected to ensure the efficiency and controllability of the process.

[0104] S600 specifically includes the following steps:

[0105] S610: Place the sample into a deposition device and start the deposition process. During the deposition process, the reaction gas undergoes a chemical reaction on the sample surface, and an oxide layer is gradually formed on the epitaxial layer.

[0106] According to the relationship between deposition time and deposition rate, the process parameters should be adjusted in time to ensure that the thickness of the final deposited oxide layer meets the requirement of 2-3um.

[0107] S620: According to the design requirements of each groove position, the layout of the through hole pattern is designed, and then the photolithography process is used to expose the photoresist through a mask with the designed pattern. The exposed photoresist is developed to show the through hole pattern on the photoresist layer.

[0108] Wherein, the through hole is located at each groove position.

[0109] S630: Select a conductive metal, place the sample into a filling process device, and start the filling process.

[0110] In a possible implementation, metal W or Mo is selected to fill the through hole. During the filling process, the deposition temperature, pressure, reaction gas type and flow rate and other parameters are controlled to ensure the filling effect and density of the metal. The conductive metal is gradually filled into the through hole to form a conductive path.

[0111] Among them, for TVS devices with deep trenches deep into the substrate and shallow trenches deep into the epitaxial layer, only the through holes in the shallow trenches are opened and filled with metal. This is different from the through hole processing in the manufacturing process of general TVS devices. This selective through hole processing is to meet the electrical performance requirements of this specific structure TVS.

[0112] S700 deposits metal on the dielectric layer through a deposition process, and then forms an electrode pattern through steps such as photoresist coating, electrode pattern design and photolithography exposure, development, and metal etching, and then undergoes a final passivation treatment to allow the electrode to be led out from the front to form a bidirectional TVS device. This step can accurately control the metal deposition thickness and the formation process of the electrode pattern, ensuring that the electrode position is accurate, the size is appropriate, and the performance is stable. The passivation treatment improves the electrode's anti-oxidation and corrosion capabilities. The resulting bidirectional TVS device has good electrical performance and reliability, and can effectively protect the circuit under forward and reverse voltages.

[0113] S700 specifically includes the following steps:

[0114] S710: Select a suitable metal material for deposition on the through-hole dielectric layer, place the sample into a deposition device, and start the deposition process.

[0115] For example, a metal material AlCu or AlSiCu is selected and deposited on the through-hole dielectric layer. During the deposition process, metal atoms are gradually deposited on the surface of the dielectric layer to form a metal layer with a thickness of 3-5 um.

[0116] S720: Photoresist is uniformly coated on the surface of the sample on which the metal layer is deposited. The layout of the electrode pattern is designed according to the design requirements of the electrode. Then, the photoresist is exposed through a mask with the designed pattern using a photolithography process. The exposed photoresist is developed to reveal the electrode pattern on the photoresist layer.

[0117] S730: etching the metal layer according to the developed pattern.

[0118] The etchant reacts chemically with the metal to etch away the exposed metal between the two through holes. At the same time, it is important to control the lateral etching during the etching process to avoid excessive impact on the size and shape of the electrode pattern.

[0119] S740: Perform final passivation treatment on the etched sample.

[0120] In one possible implementation, the passivation treatment uses a chemical passivation or physical passivation method, such as forming a passivation film on the sample surface to protect the metal electrode from oxidation and corrosion. The process parameters of the passivation treatment should be determined according to the selected passivation method and the properties of the sample to ensure a good passivation effect and protect the performance and stability of the metal electrode.

[0121] S750: The metal part corresponding to the electrode pattern is led out from the front as an electrode, such as Figure 8 As shown, a bidirectional TVS device is formed.

[0122] Bidirectional TVS devices have the characteristic of protecting circuits under both forward and reverse voltages. Under forward voltage, when the voltage exceeds a certain threshold, certain areas in the device begin to conduct, shunting excess current and protecting subsequent circuit components. Under reverse voltage, when the voltage exceeds a certain threshold, the device can also conduct and shunt current. This bidirectional conduction characteristic is achieved through the internal structural design and manufacturing process of the device. By precisely controlling each manufacturing process step and parameter, it is ensured that the electrical performance of the device meets the requirements of bidirectional TVS devices and can effectively protect circuits under different voltage polarities.

[0123] Among them, for TVS with deep trenches deep into the substrate and shallow trenches deep into the epitaxial layer, such as Fig. 9As shown, metal AlCu or AlSiCu is deposited with a thickness of 3-5um to form a front electrode, and the back side of the substrate is ground and thinned, and then multiple layers of metal TiNiAg or TiNiSnCuAg are deposited to form a back side electrode with a thickness of 2-10um, thereby forming a bidirectional TVS device.

[0124] The basic principles of the present application are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present application are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present application. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, not for limitation, and the above details do not limit the present application to being implemented by adopting the above specific details.

[0125] The block diagrams of the devices, apparatuses, equipment, and systems involved in this application are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagram. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including", "comprising", "having", etc. are open words, referring to "including but not limited to", and can be used interchangeably with them. The words "or" and "and" used here refer to the words "and / or" and can be used interchangeably with them, unless the context clearly indicates otherwise. The words "such as" used here refer to the phrase "such as but not limited to", and can be used interchangeably with them.

[0126] It should also be noted that in the apparatus, device and method of the present application, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present application.

[0127] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present application. Therefore, the present application is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features of the present invention.

[0128] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A one-step adjustable bidirectional large through-current TVS device manufacturing method, characterized in that: include: Selecting a doped silicon substrate and determining the resistivity of the doped silicon substrate, and generating an epitaxial layer on the doped silicon substrate that is inverse to the substrate; forming an oxide layer on the surface of the epitaxial layer by thermal oxidation or chemical vapor deposition process; Through photolithography and etching processes, grooves of specific shape and depth are formed on the epitaxial layer; Through a deposition process, doped polysilicon that is inversely proportional to the epitaxial layer is filled into the trench and sealed; The surface doped silicon is removed by etching process until the surface of the epitaxial layer is reached, and then the junction is pushed by high-temperature diffusion; Through a deposition process, an oxide layer is deposited on the epitaxial layer as a through-hole dielectric layer, through holes are opened at each groove position through photolithography and etching processes, and conductive metal is filled in the through holes; Through the deposition process, metal is deposited on the through-hole dielectric layer, and the metal between the through-holes is etched away through the photolithography and etching processes. After the final passivation treatment, the electrode is led out from the front to form a bidirectional TVS device.

2. The method for manufacturing a one-step controllable bidirectional large through-current TVS device according to claim 1, characterized in that: The doped silicon substrate is selected <100> or <111> The silicon material has a crystal orientation, the resistivity of the doped silicon substrate is selected within the range of 0.001 to 0.006 Ω.cm, and the thickness of the epitaxial layer is 2 to 20 um.

3. The method for manufacturing a one-step controllable bidirectional large through-current TVS device according to claim 1, characterized in that: The oxide layer is 100-10000A.

4. The method for manufacturing a one-step controllable bidirectional large through-current TVS device according to claim 1, characterized in that: The groove is in the shape of a rectangle, a square, a circle, an ellipse or a polygon.

5. The method for manufacturing a one-step controllable bidirectional large through-current TVS device according to claim 4, characterized in that: The grooves are divided into equal depth grooves and unequal depth grooves; Among them, for equal-depth grooves, equal-width layouts are designed and etched according to the etching process; Among them, for grooves of unequal depth, that is, deep grooves go deep into the substrate and shallow grooves go deep into the epitaxial layer, the etching time required to make the grooves deep into the substrate is first calculated based on the etching rate, and the width of the shallow trench layout is reversed under the condition of the required shallow trench depth. The unequal width layout is designed. When etching, the deep groove is first etched to the substrate, and then the etching is adjusted according to the requirements of the unequal depth grooves.

6. The method for manufacturing a one-step controllable bidirectional large through-current TVS device according to claim 1, characterized in that: During the sealing process, doped polysilicon is continuously deposited to form a flat surface above the trench, thereby completely sealing the trench.

7. The method for manufacturing a one-step controllable bidirectional large through-current TVS device according to claim 1, characterized in that: The high temperature diffusion temperature is 900-1200°C and the diffusion time is 10-90min; The high temperature diffusion push-in junction causes two adjacent doped silicons and the formed doped region and the intermediate epitaxial region to undergo a diffusion reaction at high temperature, and the diffusion reaction standard is: Ensure that the distance between the two trenches does not hold hands in the diffusion area formed after high-temperature diffusion, and there is still an epitaxial area with a certain gap in the middle to form a bidirectional TVS device unit.

8. The method for manufacturing a one-step controllable bidirectional large through-current TVS device according to claim 1, characterized in that: The thickness of the through-hole dielectric layer is 2-3 um, and metal W or Mo is selected to fill the through-hole.

9. The method for manufacturing a one-step controllable bidirectional large through-current TVS device according to claim 1, characterized in that: For the deep trenches in the trenches that extend deep into the substrate, through holes are opened at shallow trenches in the deep trenches and filled with metal.

10. The method for manufacturing a one-step controllable bidirectional large through-current TVS device according to claim 1, characterized in that: The metal deposited on the through-hole dielectric layer includes AlCu or AlSiCu; the deposition thickness is 3-5um; For the deep grooves in the grooves that penetrate into the substrate, the back side of the substrate is ground and thinned, and then multiple layers of metal TiNiAg or TiNiSnCuAg are deposited to form a back electrode with a thickness of 2-10 um.

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