Bilinear interpolation operation device and method, electronic equipment and storage medium

Abstract

The invention relates to a bilinear interpolation operation device and method, electronic equipment and a storage medium, and the device comprises a linear interpolation module which comprises a plurality of selectors and a summator; the primary linear interpolation module performs primary linear interpolation on the first to-be-interpolated data and the second to-be-interpolated data according to the first interpolation weight by using a plurality of selectors and a summator to obtain a first intermediate interpolation result; the primary linear interpolation module performs primary linear interpolation on the third to-be-interpolated data and the fourth to-be-interpolated data according to the first interpolation weight by using a plurality of selectors and a summator to obtain a second intermediate interpolation result; and the primary linear interpolation module performs primary linear interpolation on the first intermediate interpolation result and the second intermediate interpolation result according to the second interpolation weight by using a plurality of selectors and a summator to obtain a target bilinear interpolation result. According to the embodiment of the invention, the overall circuit area of the device can be effectively reduced, and hardware resource consumption is saved.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a bilinear interpolation operation device and method, an electronic device and a storage medium. Background Art

[0002] Bilinear interpolation is a method of interpolation in two-dimensional space that estimates the value of an unknown point by performing two linear interpolations of its four nearest neighboring points. This technique is very common in image processing, computer graphics, and various engineering applications, especially in texture mapping and image scaling. Summary of the invention

[0003] The present disclosure proposes a technical solution of a bilinear interpolation operation device and method, an electronic device and a storage medium.

[0004] According to one aspect of the present disclosure, a bilinear interpolation operation device is provided, including: a linear interpolation module, the linear interpolation module including multiple selectors and an adder; the linear interpolation module is used to use the multiple selectors and the adder to perform linear interpolation on first data to be interpolated and second data to be interpolated according to a first interpolation weight to obtain a first intermediate interpolation result; the linear interpolation module is used to use the multiple selectors and the adder to perform linear interpolation on third data to be interpolated and fourth data to be interpolated according to the first interpolation weight to obtain a second intermediate interpolation result; the linear interpolation module is used to use the multiple selectors and the adder to perform linear interpolation on the first intermediate interpolation result and the second intermediate interpolation result according to a second interpolation weight to obtain a target bilinear interpolation result.

[0005] In a possible implementation, the first interpolation weight and the second interpolation weight are m bits, where m is the number of bits of the binary numbers corresponding to the first interpolation weight and the second interpolation weight; and the first-order linear interpolation module includes: m selectors.

[0006] In one possible implementation, the input of the i-th selector is the first target data, the second target data, and the value of the i-th bit of the target interpolation weight, where i is a positive integer greater than or equal to 0 and less than or equal to m-1; when the first target data is the first data to be interpolated, the second target data is the second data to be interpolated, and the target interpolation weight is the first interpolation weight; when the first target data is the third data to be interpolated, the second target data is the fourth data to be interpolated, and the target interpolation weight is the first interpolation weight; when the first target data is the first interpolation result, the second target data is the second interpolation result, and the target interpolation weight is the second interpolation weight.

[0007] In a possible implementation, the input of the adder is the first target data and the selection result output by each selector.

[0008] In one possible implementation, the i-th selector is used to select between the first target data and the second target data according to the value of the i-th bit of the target interpolation weight, and determine the selection result of the i-th selector; the adder is used to sum the first target data and the selection results of each selector to obtain a summed result; wherein, when the first target data is the first data to be interpolated, the summed result is the first intermediate interpolation result; when the first target data is the third data to be interpolated, the summed result is the second intermediate interpolation result; when the first target data is the first interpolation result, the summed result is the target bilinear interpolation result.

[0009] In a possible implementation, the i-th selector is specifically used to: when the value of the i-th bit of the target interpolation weight is 0, the first target data is shifted left by i bits and determined as the selection result of the i-th selector; when the value of the i-th bit of the target interpolation weight is 1, the second target data is shifted left by i bits and determined as the selection result of the i-th selector.

[0010] In a possible implementation, the first data to be interpolated, the second data to be interpolated, the third data to be interpolated, and the fourth data to be interpolated are four pixel data of a 2×2 structure in a target image that need to be subjected to bilinear interpolation processing.

[0011] In a possible implementation, when the bilinear interpolation operation device is applied to a texture unit of a graphics processing unit (GPU), decimal values ​​of the first interpolation weight and the second interpolation weight are greater than or equal to 0 and less than 1.

[0012] According to one aspect of the present disclosure, a bilinear interpolation operation device is provided, including: three linear interpolation modules, each of which includes multiple selectors and an adder; a first linear interpolation module, used to use multiple selectors and an adder to perform linear interpolation on first data to be interpolated and second data to be interpolated according to a first interpolation weight to obtain a first intermediate interpolation result; a second linear interpolation module, used to use multiple selectors and an adder to perform linear interpolation on third data to be interpolated and fourth data to be interpolated according to the first interpolation weight to obtain a second intermediate interpolation result; a third linear interpolation module, used to use multiple selectors and an adder to perform linear interpolation on the first intermediate interpolation result and the second intermediate interpolation result according to a second interpolation weight to obtain a target bilinear interpolation result.

[0013] According to one aspect of the present disclosure, a bilinear interpolation operation method is provided, the method is applied to a bilinear interpolation operation device, the bilinear interpolation operation device includes a linear interpolation module, the linear interpolation module includes multiple selectors and an adder; the method includes: using the multiple selectors and the adder in the linear interpolation module, according to a first interpolation weight, performing a linear interpolation on a first to-be-interpolated data and a second to-be-interpolated data to obtain a first intermediate interpolation result; using the multiple selectors and the adder in the linear interpolation module, according to the first interpolation weight, performing a linear interpolation on a third to-be-interpolated data and a fourth to-be-interpolated data to obtain a second intermediate interpolation result; using the multiple selectors and the adder in the linear interpolation module, according to a second interpolation weight, performing a linear interpolation on the first intermediate interpolation result and the second intermediate interpolation result to obtain a target bilinear interpolation result.

[0014] According to one aspect of the present disclosure, a bilinear interpolation operation method is provided, the method is applied to a bilinear interpolation operation device, the bilinear interpolation operation device includes three linear interpolation modules, each linear interpolation module includes multiple selectors and an adder; the method includes: using multiple selectors and an adder in a first linear interpolation module, according to a first interpolation weight, performing linear interpolation on first data to be interpolated and second data to be interpolated, to obtain a first intermediate interpolation result; using multiple selectors and an adder in a second linear interpolation module, according to the first interpolation weight, performing linear interpolation on third data to be interpolated and fourth data to be interpolated, to obtain a second intermediate interpolation result; using multiple selectors and an adder in a third linear interpolation module, according to a second interpolation weight, performing linear interpolation on the first intermediate interpolation result and the second intermediate interpolation result, to obtain a target bilinear interpolation result.

[0015] According to one aspect of the present disclosure, an electronic device is provided, including: the above-mentioned bilinear interpolation operation device.

[0016] According to one aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to call the instructions stored in the memory to execute the above method.

[0017] According to one aspect of the present disclosure, a computer-readable storage medium is provided, on which computer program instructions are stored, and the computer program instructions implement the above method when executed by a processor.

[0018] In an embodiment of the present disclosure, a bilinear interpolation operation device includes: a linear interpolation module, the linear interpolation module includes a plurality of selectors and an adder; the linear interpolation module is used to use a plurality of selectors and adders to perform a linear interpolation on a first data to be interpolated and a second data to be interpolated according to a first interpolation weight to obtain a first intermediate interpolation result; the linear interpolation module is used to use a plurality of selectors and adders to perform a linear interpolation on a third data to be interpolated and a fourth data to be interpolated according to a first interpolation weight to obtain a second intermediate interpolation result; the linear interpolation module is used to use a plurality of selectors and adders to perform a linear interpolation on the first intermediate interpolation result and the second intermediate interpolation result according to a second interpolation weight to obtain a target bilinear interpolation result. Compared with a high-complexity multiplier, the bilinear interpolation operation device of the embodiment of the present disclosure can realize bilinear interpolation by using only a plurality of selectors and adders in a linear interpolation module, thereby effectively reducing the overall circuit area of ​​the device and saving hardware resource consumption.

[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only and do not limit the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.

[0021] Figure 1 A schematic diagram showing bilinear interpolation of a 2X2 dot matrix in the related art is shown.

[0022] Figure 2 A schematic diagram of a bilinear interpolation operation device according to an embodiment of the present disclosure is shown.

[0023] Figure 3 A schematic diagram of a linear interpolation module according to an embodiment of the present disclosure is shown.

[0024] Figure 4 A schematic diagram of the operation of a linear interpolation module according to an embodiment of the present disclosure is shown.

[0025] Figure 5 A schematic diagram of the operation of a linear interpolation module according to an embodiment of the present disclosure is shown.

[0026] Figure 6 A schematic diagram of the operation of a linear interpolation module according to an embodiment of the present disclosure is shown.

[0027] Figure 7 A schematic diagram of a bilinear interpolation operation device according to an embodiment of the present disclosure is shown.

[0028] Figure 8 A flow chart of a bilinear interpolation operation method according to an embodiment of the present disclosure is shown.

[0029] Fig. 9 A flow chart of a bilinear interpolation operation method according to an embodiment of the present disclosure is shown.

[0030] Fig.10 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0031] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0032] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0033] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

[0034] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0035] Bilinear interpolation is a method of interpolation in two-dimensional space that estimates the value of an unknown point by performing two linear interpolations of its four nearest neighboring points. This technique is very common in image processing, computer graphics, and various engineering applications, especially in texture mapping and image scaling.

[0036] In the texture unit of a graphics processing unit (GPU), there is often a filtering method called bilinear interpolation, whose physical meaning is to perform linear interpolation on a 2X2 dot matrix in the horizontal and vertical directions respectively, and obtain the interpolation result as the final output. Figure 1 FIG. 2 is a schematic diagram showing bilinear interpolation of a 2X2 dot matrix in the related art. Figure 1 As shown, a linear interpolation is performed on the four points A, B, C, and D of the 2X2 dot matrix in the U and V directions respectively.

[0037] One expression of bilinear interpolation can be the following formulas (1) to (3):

[0038] result_ab=a×(1-u)+b×u (1),

[0039] result_cd=c×(1-u)+d×u (2),

[0040] result_abcd=result_ab×(1-v)+result_cd×u (3).

[0041] Among them, a, b, c, d are the four interpolation data that need to be bilinearly interpolated, that is, the data corresponding to the four points A, B, C, and D; u is the interpolation weight in the U direction; v is the interpolation weight in the V direction; result_ab is the interpolation result obtained after a and b are linearly interpolated in the U direction; result_cd is the interpolation result obtained after c and d are linearly interpolated in the U direction; result_abcd is the interpolation result obtained after result_ab and result_cd are linearly interpolated in the V direction, that is, the bilinear interpolation results corresponding to a, b, c, and d.

[0042] A bilinear interpolation implementation method in the related art, according to the above formulas (1) and (2), a linear interpolation is performed in the U direction respectively to obtain the interpolation results result_ab and result_cd, and then according to the above formula (3), a linear interpolation is performed in the V direction to determine the bilinear interpolation result result_abcd.

[0043] Another bilinear interpolation implementation method in the related art is to express the bilinear interpolation result result_abcd by the following formula (4) according to the above formulas (1), (2) and (3):

[0044] result_abcd=a×(1-u)×(1-v)+b×u×(1-v)+c×(1-u)×v+d×u×v (4).

[0045] According to the above formula (4), the bilinear interpolation result result_abcd can be directly determined.

[0046] However, the above two bilinear interpolation implementation methods require at least 6 multipliers. Assuming that the binary number corresponding to the interpolation weights u and v is m bits, if the accuracy is high enough, that is, when m is very large, the hardware resources consumed will also be large. In order to solve the above technical problems, the embodiment of the present disclosure provides a bilinear interpolation operation device, which can avoid the use of multipliers and save hardware resource consumption. The bilinear interpolation operation device provided by the embodiment of the present disclosure is described in detail below.

[0047] Figure 2 FIG. 1 is a schematic diagram showing a bilinear interpolation operation device according to an embodiment of the present disclosure. Figure 2 As shown, the bilinear interpolation operation device includes a linear interpolation module, which includes multiple selectors and an adder; the linear interpolation module is used to use multiple selectors and adders to perform linear interpolation on the first data to be interpolated and the second data to be interpolated according to the first interpolation weight to obtain a first intermediate interpolation result; the linear interpolation module is used to use multiple selectors and adders to perform linear interpolation on the third data to be interpolated and the fourth data to be interpolated according to the first interpolation weight to obtain a second intermediate interpolation result; the linear interpolation module is used to use multiple selectors and adders to perform linear interpolation on the first intermediate interpolation result and the second intermediate interpolation result according to the second interpolation weight to obtain a target bilinear interpolation result.

[0048] Compared with high-complexity multipliers, the bilinear interpolation operation device of the embodiment of the present disclosure can realize bilinear interpolation by utilizing multiple selectors and adders in a linear interpolation module, thereby effectively reducing the overall circuit area of ​​the device and saving hardware resource consumption.

[0049] In a possible implementation, the first data to be interpolated, the second data to be interpolated, the third data to be interpolated, and the fourth data to be interpolated are four pixel data of a 2×2 structure in a target image that need to be subjected to bilinear interpolation processing.

[0050] By performing bilinear interpolation on the four pixel data of the 2x2 structure in the target image, the pixel data of a certain pixel point located at the center of the four pixel points can be effectively determined. In image scaling or texture mapping, based on this bilinear interpolation process, smooth transition of pixel colors can be achieved, reducing aliasing and aliasing.

[0051] With the above Figure 2 For example, the first data to be interpolated a, the second data to be interpolated b, the third data to be interpolated c, and the fourth data to be interpolated d are pixel data corresponding to pixel points A, B, C, and D.

[0052] In a possible implementation, when the bilinear interpolation operation device is applied to a GPU texture unit, the decimal values ​​of the first interpolation weight and the second interpolation weight are greater than or equal to 0 and less than 1.

[0053] There is a concept of "top left" in the GPU texture unit, that is, the point in the upper left corner is generally used as the reference point. Therefore, after bilinear interpolation is performed on the four pixel data of the 2x2 structure in the target image, the bilinear interpolation result cannot obtain any value of the second interpolation data b, the third interpolation data c, and the fourth interpolation data d. Therefore, it is necessary to ensure that the decimal values ​​of the first interpolation weight u in the U direction and the second interpolation weight v in the V direction are greater than or equal to 0 and less than 1, that is, the decimal value range of the first interpolation weight u and the second interpolation weight v is [0, 1).

[0054] If the bilinear interpolation result needs to be able to obtain the second data to be interpolated b, the third data to be interpolated c, and the fourth data to be interpolated d, the pixels B, C, and D need to be the pixels located at the upper left corner of the four pixels in the 2x2 structure.

[0055] In GPU or other graphics hardware, interpolation operations are usually performed in the integer domain to simplify hardware design and improve efficiency. Therefore, by optimizing the bilinear interpolation processing of integer data, the bilinear interpolation operation device proposed in this application is obtained.

[0056] In the hardware design circuit, the numbers are all expressed in binary form. The first data to be interpolated a, the second data to be interpolated b, the third data to be interpolated c, and the fourth data to be interpolated d are n-bit integer data, and the first interpolation weight u and the second interpolation weight v are m-bit integer data. Among them, the value of n reflects the accuracy of the data to be interpolated, and the value of m reflects the accuracy of the interpolation process. The specific values ​​of n and m can be flexibly set according to actual conditions, and the present disclosure does not make specific restrictions on this.

[0057] The process of performing a linear interpolation on the first data to be interpolated a and the second data to be interpolated b in the U direction based on the first interpolation weight u as shown in the above formula (1) is taken as an example for description.

[0058] In order to use the same hardware circuit to process addition and subtraction operations, 1-u is transformed based on the two's complement in digital circuits, 1-u = ~u + LSB, where ~u is the inversion of each bit of u, LSB is the least significant bit of u, that is, the rightmost 1, so 1-u = ~u + 1. For example, if u is 1011, then ~u is 0100, 1-u = ~u + 1 = 0101.

[0059] After transforming 1-u, a×(1-u)+b×u=a×(~u)+b×u+a. Furthermore, a×(~u)+b×u=u? b:a, where ? is a ternary operator, that is, a and b are selected according to the value of u. At this time, a selector can be used to select a and b to implement the multiplication operation a×(~u)+b×u.

[0060] Specifically for each bit, sum[i]=u[i]? b shifts left by i bits: a shifts left by i bits, where sum[i] is the selection result based on the i-th bit of u. At this time, the above formula (1) can be expressed by the following formula (5):

[0061]

[0062] Furthermore, the above formula (5) can be intuitively represented by the following Table 1.

[0063] 0 …… 0 0 0 sum[0] 0 …… 0 0 sum[1] 0 0 …… 0 sum[2] 0 0 0 …… …… 0 0 0 sum[n-1] …… …… 0 0 0 0 0 0 0 0 a

[0064] The above table includes m+1 rows and n columns, wherein the first m rows are used to indicate the selection result of sum[i], the m+1th row is used to indicate +a, and the jth column from right to left is used to indicate a left shift of j bits, where j is greater than or equal to 0 and less than or equal to n-1.

[0065] After the above analysis, the linear interpolation of the first data a to be interpolated and the second data b to be interpolated in the U direction based on the first interpolation weight u as shown in the above formula (1) can be realized only by using the selector and the adder.

[0066] Similarly, for the linear interpolation of the third data c to be interpolated and the fourth data d to be interpolated in the U direction based on the first interpolation weight u as shown in the above formula (2), and the linear interpolation of result_ab and result_cd in the V direction based on the second interpolation weight v as shown in formula (3), the selectors and adders can be used in the above manner, which will not be elaborated here.

[0067] In a possible implementation, the first interpolation weight and the second interpolation weight are m bits, where m is the number of bits of the binary numbers corresponding to the first interpolation weight and the second interpolation weight; and the linear interpolation module includes: m selectors.

[0068] According to the above formula (5), when the first interpolation weight u and the second interpolation weight v are m bits, the linear interpolation module may include m selectors.

[0069] Figure 3 FIG. 2 is a schematic diagram showing a linear interpolation module according to an embodiment of the present disclosure. Figure 3 As shown, the linear interpolation module includes m selectors: selectors 0 to m-1, and an adder.

[0070] In one possible implementation, the input of the i-th selector is the first target data, the second target data, and the value of the i-th bit of the target interpolation weight, where i is a positive integer greater than or equal to 0 and less than or equal to m-1; when the first target data is the first data to be interpolated, the second target data is the second data to be interpolated, and the target interpolation weight is the first interpolation weight; when the first target data is the third data to be interpolated, the second target data is the fourth data to be interpolated, and the target interpolation weight is the first interpolation weight; when the first target data is the first interpolation result, the second target data is the second interpolation result, and the target interpolation weight is the second interpolation weight.

[0071] When a linear interpolation module is used to perform a linear interpolation on the first data to be interpolated a and the second data to be interpolated b in the U direction based on the first interpolation weight u, the input of each selector includes: the first target data (the first data to be interpolated a), the second target data (the second data to be interpolated b), and the input of the i-th selector also includes: the value of the i-th bit of the target interpolation weight (the first interpolation weight u). Figure 4 FIG. 2 shows a schematic diagram of the operation of a linear interpolation module according to an embodiment of the present disclosure. Figure 4As shown, the input of each selector includes: the first data to be interpolated a, the second data to be interpolated b, the input of the 0th selector (selector 0) also includes the value u[0] of the 0th bit of the first interpolation weight u, the input of the 1st selector (selector 1) also includes the value u[1] of the 1st bit of the first interpolation weight u, and so on, until the input of the m-1th selector (selector m-1) also includes the value u[m-1] of the m-1th bit of the first interpolation weight u.

[0072] When a linear interpolation module is used to perform a linear interpolation on the third data to be interpolated c and the fourth data to be interpolated d in the U direction based on the first interpolation weight u, the input of each selector includes: the first target data (the third data to be interpolated c), the second target data (the fourth interpolation data d), and the input of the i-th selector also includes: the value of the i-th bit of the target interpolation weight (the first interpolation weight u). Figure 5 FIG. 2 shows a schematic diagram of the operation of a linear interpolation module according to an embodiment of the present disclosure. Figure 5 As shown, the input of each selector includes: the third data to be interpolated c, the fourth data to be interpolated d, the input of the 0th selector (selector 0) also includes the value u[0] of the 0th bit of the first interpolation weight u, the input of the 1st selector (selector 1) also includes the value u[1] of the 1st bit of the first interpolation weight u, and so on, until the input of the m-1th selector (selector m-1) also includes the value u[m-1] of the m-1th bit of the first interpolation weight u.

[0073] When a linear interpolation module is used to perform a linear interpolation on the first intermediate interpolation result result_ab and the second intermediate interpolation result result_cd in the V direction based on the second interpolation weight v, the input of each selector includes: the first target data (first intermediate interpolation result result_ab), the second target data (second intermediate interpolation result result_cd), and the input of the i-th selector also includes: the value of the i-th bit of the target interpolation weight (second interpolation weight v). Figure 6 FIG. 2 shows a schematic diagram of the operation of a linear interpolation module according to an embodiment of the present disclosure. Figure 6 As shown, the input of each selector includes: a first intermediate interpolation result result_ab, a second intermediate interpolation result result_cd, the input of the 0th selector (selector 0) also includes the value v[0] of the 0th bit of the second interpolation weight v, the input of the 1st selector (selector 1) also includes the value v[1] of the 1st bit of the second interpolation weight v, and so on, until the input of the m-1th selector (selector m-1) also includes the value v[m-1] of the m-1th bit of the second interpolation weight v.

[0074] In one possible implementation, the i-th selector is specifically used to: when the value of the i-th bit of the target interpolation weight is 0, the first target data is shifted left by i bits and determined as the selection result of the i-th selector; when the value of the i-th bit of the target interpolation weight is 1, the second target data is shifted left by i bits and determined as the selection result of the i-th selector.

[0075] According to the above formula (5), the i-th selector is the selection process of sum[i] above.

[0076] In the case where a linear interpolation module is used to perform a linear interpolation on the first data to be interpolated a and the second data to be interpolated b in the U direction based on the first interpolation weight u, Figure 4 In the linear interpolation module shown, the i-th selector is specifically used for: when the value of the i-th bit u[i] of the first interpolation weight u is 0, the first data to be interpolated a is shifted left by i bits and determined as the selection result of the i-th selector; when the value of the i-th bit u[i] of the first interpolation weight u is 1, the second data to be interpolated b is shifted left by i bits and determined as the selection result of the i-th selector.

[0077] When a linear interpolation module is used to perform a linear interpolation on the third data to be interpolated c and the fourth data to be interpolated d in the U direction based on the first interpolation weight u, Figure 5 In the linear interpolation module shown, the i-th selector is specifically used for: when the value of the i-th bit u[i] of the first interpolation weight u is 0, the third data to be interpolated c is shifted left by i bits and determined as the selection result of the i-th selector; when the value of the i-th bit u[i] of the first interpolation weight u is 1, the fourth data to be interpolated d is shifted left by i bits and determined as the selection result of the i-th selector.

[0078] In the case where a linear interpolation module is used to perform a linear interpolation on the first intermediate interpolation result result_ab and the second intermediate interpolation result result_cd in the V direction based on the second interpolation weight v, Figure 6 In the linear interpolation module shown, the i-th selector is specifically used to: when the value of the i-th bit v[i] of the second interpolation weight v is 0, the first intermediate interpolation result result_ab is shifted left by i bits and determined as the selection result of the i-th selector; when the value of the i-th bit v[i] of the second interpolation weight v is 1, the second intermediate interpolation result result_cd is shifted left by i bits and determined as the selection result of the i-th selector.

[0079] In a possible implementation, the input of the adder is the first target data and the selection result output by each selector.

[0080] According to the above formula (5), an adder is used to implement the summation processing of the output sum[i] of each selector and the first target data.

[0081] In one possible implementation, the i-th selector is used to select between the first target data and the second target data according to the value of the i-th bit of the target interpolation weight, and determine the selection result of the i-th selector; the adder is used to sum the first target data and the selection results of each selector to obtain a summed result; wherein, when the first target data is the first data to be interpolated, the summed result is the first intermediate interpolation result; when the first target data is the third data to be interpolated, the summed result is the second intermediate interpolation result; when the first target data is the first interpolation result, the summed result is the target bilinear interpolation result.

[0082] In the case where a linear interpolation module is used to perform a linear interpolation on the first data to be interpolated a and the second data to be interpolated b in the U direction based on the first interpolation weight u, as follows: Figure 4 As shown, the outputs of the m selectors and the first data to be interpolated a are input into the adder for summing, and a summing result is obtained: the first intermediate interpolation result result_ab.

[0083] In the case where a linear interpolation module is used to perform a linear interpolation on the third data to be interpolated c and the fourth data to be interpolated d in the U direction based on the first interpolation weight u, as follows: Figure 5 As shown, the outputs of the m selectors and the third data to be interpolated c are input into the adder for summing, and the summing result is obtained: the second intermediate interpolation result result_cd.

[0084] In the case where a linear interpolation module is used to perform a linear interpolation on the first intermediate interpolation result result_ab and the second intermediate interpolation result result_cd in the V direction based on the second interpolation weight v, as follows Figure 6 As shown, the outputs of the m selectors and the first intermediate interpolation result result_ab are input into the adder for summing, and the summation result is obtained: the target bilinear interpolation result result_abcd.

[0085] Compared with high-complexity multipliers, the bilinear interpolation operation device of the embodiment of the present disclosure can realize bilinear interpolation by utilizing multiple selectors and adders in a linear interpolation module, thereby effectively reducing the overall circuit area of ​​the device and saving hardware resource consumption.

[0086] In order to further improve the efficiency of bilinear interpolation operation, the embodiment of the present disclosure further provides another bilinear interpolation operation device.

[0087] Figure 7 FIG. 1 is a schematic diagram showing a bilinear interpolation operation device according to an embodiment of the present disclosure. Figure 7 As shown, the bilinear interpolation operation device includes three linear interpolation modules: a first linear interpolation module, a second linear interpolation module, and a third linear interpolation module, each of which includes a plurality of selectors and an adder. The first linear interpolation module is used to use a plurality of selectors and an adder to perform linear interpolation on the first data to be interpolated and the second data to be interpolated according to the first interpolation weight to obtain a first intermediate interpolation result; the second linear interpolation module is used to use a plurality of selectors and an adder to perform linear interpolation on the third data to be interpolated and the fourth data to be interpolated according to the first interpolation weight to obtain a second intermediate interpolation result; the third linear interpolation module is used to use a plurality of selectors and an adder to perform linear interpolation on the first intermediate interpolation result and the second intermediate interpolation result according to the second interpolation weight to obtain a target bilinear interpolation result.

[0088] Figure 7 The first linear interpolation module shown is used to perform a linear interpolation on the first to-be-interpolated data a and the second to-be-interpolated data b in the U direction based on the first interpolation weight u. The specific operation can refer to the above Figure 4 The above-mentioned related descriptions will not be repeated here.

[0089] Figure 7 The second linear interpolation module shown is used to perform a linear interpolation on the third to-be-interpolated data c and the fourth to-be-interpolated data d in the U direction based on the first interpolation weight u. The specific operation can refer to the above Figure 5 The above-mentioned related descriptions will not be repeated here.

[0090] Figure 7 The third linear interpolation module shown is used to perform a linear interpolation on the first intermediate interpolation result result_ab and the second intermediate interpolation result result_cd in the V direction based on the second interpolation weight v. The specific operation can refer to the above Figure 6 The above-mentioned related descriptions will not be repeated here.

[0091] Figure 8 A flow chart of a bilinear difference operation method according to an embodiment of the present disclosure is shown. The method can be applied to Figure 2 The bilinear difference operation device shown in the figure includes a linear interpolation module, which includes a plurality of selectors and an adder. Figure 8 As shown, the method includes:

[0092] In step S81, a plurality of selectors and an adder in a linear interpolation module are used to perform a linear interpolation on the first data to be interpolated and the second data to be interpolated according to a first interpolation weight to obtain a first intermediate interpolation result.

[0093] In step S82, a plurality of selectors and an adder in the linear interpolation module are used to perform linear interpolation on the third data to be interpolated and the fourth data to be interpolated according to the first interpolation weight to obtain a second intermediate interpolation result.

[0094] In step S83, a plurality of selectors and an adder in the linear interpolation module are used to perform linear interpolation on the first intermediate interpolation result and the second intermediate interpolation result according to the second interpolation weight to obtain a target bilinear interpolation result.

[0095] application Figure 2 The bilinear difference operation device shown performs Figure 8 For the specific process of the bilinear difference calculation method shown in FIG. Figures 2 to 6 The relevant embodiments are not described in detail here.

[0096] Fig. 9 A flow chart of a bilinear difference operation method according to an embodiment of the present disclosure is shown. The method can be applied to Figure 7 The bilinear difference operation device shown in the figure comprises three linear interpolation modules, each of which comprises a plurality of selectors and an adder. Fig. 9 As shown, the method includes:

[0097] In step S91, a plurality of selectors and an adder in the first linear interpolation module are used to perform linear interpolation on the first data to be interpolated and the second data to be interpolated according to the first interpolation weight to obtain a first intermediate interpolation result.

[0098] In step S92, a plurality of selectors and an adder in the second linear interpolation module are used to perform linear interpolation on the third data to be interpolated and the fourth data to be interpolated according to the first interpolation weight to obtain a second intermediate interpolation result.

[0099] In step S93, a plurality of selectors and an adder in the third linear interpolation module are used to perform linear interpolation on the first intermediate interpolation result and the second intermediate interpolation result according to the second interpolation weight to obtain a target bilinear interpolation result.

[0100] application Figure 7 The bilinear difference operation device shown performs Fig. 9 For the specific process of the bilinear difference calculation method shown in FIG. Figures 4 to 7 The relevant embodiments are not described in detail here.

[0101] It can be understood that the above-mentioned embodiments mentioned in the present disclosure can be combined with each other to form a combined embodiment without violating the principle logic. Due to space limitations, the present disclosure will not repeat them. It can be understood by those skilled in the art that in the above-mentioned method of the specific implementation method, the specific execution order of each step should be determined according to its function and possible internal logic.

[0102] This method has a specific technical connection with the internal structure of the computer system, and can solve the technical problem of how to improve the hardware computing efficiency or execution effect (including reducing the amount of data storage, reducing the amount of data transmission, increasing the hardware processing speed, etc.), thereby obtaining the technical effect of improving the internal performance of the computer system in accordance with the laws of nature.

[0103] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0104] The embodiment of the present disclosure also provides a computer-readable storage medium on which computer program instructions are stored, and the computer program instructions implement the above method when executed by a processor. The computer-readable storage medium can be a volatile or non-volatile computer-readable storage medium.

[0105] The disclosed embodiment further provides an electronic device, comprising: the above-mentioned bilinear difference operation device.

[0106] An embodiment of the present disclosure further proposes an electronic device, comprising: a processor; and a memory for storing instructions executable by the processor; wherein the processor is configured to call the instructions stored in the memory to execute the above method.

[0107] The embodiments of the present disclosure also provide a computer program product, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.

[0108] The electronic device may be provided as a terminal, a server, or a device in other forms.

[0109] Fig.10 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. Fig.10 , the electronic device 1900 can be provided as a server or a terminal device. Fig.10 , the electronic device 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions executable by the processing component 1922, such as an application. The application stored in the memory 1932 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute instructions to perform the above method.

[0110] The electronic device 1900 may also include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output interface 1958. The electronic device 1900 may operate based on an operating system stored in the memory 1932, such as a Microsoft Server operating system (Windows Server 2003). TM ), a graphical user interface operating system launched by Apple (Mac OS X TM ), a multi-user, multi-process computer operating system (Unix TM ), a free and open source Unix-like operating system (Linux TM ), an open source Unix-like operating system (FreeBSD TM ) or similar.

[0111] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions, which can be executed by the processing component 1922 of the electronic device 1900 to perform the above method.

[0112] The present disclosure may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0113] Computer readable storage medium can be a tangible device that can hold and store instructions used by an instruction execution device. Computer readable storage medium can be, for example, (but not limited to) an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (non-exhaustive list) of computer readable storage medium include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, for example, a punch card or a convex structure in a groove on which instructions are stored, and any suitable combination thereof. The computer readable storage medium used here is not interpreted as a transient signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated by a waveguide or other transmission medium (for example, a light pulse by an optical fiber cable), or an electrical signal transmitted by a wire.

[0114] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0115] The computer program instructions for performing the operation of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. Computer-readable program instructions may be executed completely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or completely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be customized by utilizing the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0116] Various aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0117] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0118] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0119] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0120] The computer program product may be implemented in hardware, software or a combination thereof. In one optional embodiment, the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (SDK) and the like.

[0121] The above description of various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced to each other, and for the sake of brevity, they will not be repeated herein.

[0122] Those skilled in the art will appreciate that, in the above method of specific implementation, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of the steps should be determined by their functions and possible internal logic.

[0123] If the technical solution of this application involves personal information, the product using the technical solution of this application has clearly informed the personal information processing rules and obtained the individual's voluntary consent before processing the personal information. If the technical solution of this application involves sensitive personal information, the product using the technical solution of this application has obtained the individual's separate consent before processing the sensitive personal information, and at the same time meets the "explicit consent" requirement. For example, on personal information collection devices such as cameras, clear and prominent signs are set to inform that the personal information collection scope has been entered and personal information will be collected. If the individual voluntarily enters the collection scope, it is deemed that he or she agrees to the collection of his or her personal information; or on the device that processes personal information, the personal information processing rules are notified by obvious signs / information, and the individual's authorization is obtained through pop-up information or by asking the individual to upload his or her personal information; among them, the personal information processing rules may include information such as the personal information processor, the purpose of personal information processing, the processing method, and the type of personal information processed.

[0124] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A bilinear interpolation operation device, characterized in that: include: A linear interpolation module, wherein the linear interpolation module comprises a plurality of selectors and an adder; The linear interpolation module is used to use the multiple selectors and the adder to perform linear interpolation on the first data to be interpolated and the second data to be interpolated according to the first interpolation weight to obtain a first intermediate interpolation result; The linear interpolation module is used to use the multiple selectors and the adder to perform linear interpolation on the third data to be interpolated and the fourth data to be interpolated according to the first interpolation weight to obtain a second intermediate interpolation result; The linear interpolation module is used to use the multiple selectors and the adder to perform linear interpolation on the first intermediate interpolation result and the second intermediate interpolation result according to the second interpolation weight to obtain a target bilinear interpolation result.

2. The device according to claim 1, characterized in that The first interpolation weight and the second interpolation weight are m bits, where m is the number of bits of the binary numbers corresponding to the first interpolation weight and the second interpolation weight; The first-order linear interpolation module includes: m selectors.

3. The device according to claim 2, characterized in that The input of the i-th selector is the first target data, the second target data, and the value of the i-th bit of the target interpolation weight, where i is a positive integer greater than or equal to 0 and less than or equal to m-1; When the first target data is the first data to be interpolated, the second target data is the second data to be interpolated, and the target interpolation weight is the first interpolation weight; when the first target data is the third data to be interpolated, the second target data is the fourth data to be interpolated, and the target interpolation weight is the first interpolation weight; when the first target data is the first interpolation result, the second target data is the second interpolation result, and the target interpolation weight is the second interpolation weight.

4. The device according to claim 3, characterized in that The input of the adder is the first target data and the selection result output by each selector.

5. The device according to claim 4, characterized in that The i-th selector is used to select between the first target data and the second target data according to the value of the i-th bit of the target interpolation weight, and determine the selection result of the i-th selector; The adder is used to sum the first target data and the selection result of each selector to obtain a sum result; Among them, when the first target data is the first data to be interpolated, the summation result is the first intermediate interpolation result; when the first target data is the third data to be interpolated, the summation result is the second intermediate interpolation result; when the first target data is the first interpolation result, the summation result is the target bilinear interpolation result.

6. The device according to claim 5, characterized in that The i-th selector is specifically used for: When the value of the i-th bit of the target interpolation weight is 0, the first target data is shifted left by i bits and determined as the selection result of the i-th selector; When the value of the i-th bit of the target interpolation weight is 1, the second target data is shifted left by i bits and determined as the selection result of the i-th selector.

7. The device according to any one of claims 1 to 6, characterized in that The first data to be interpolated, the second data to be interpolated, the third data to be interpolated, and the fourth data to be interpolated are four pixel data of a 2×2 structure in a target image that need to be subjected to bilinear interpolation processing.

8. The device according to claim 7, characterized in that When the bilinear interpolation operation device is applied to a texture unit of a graphics processing unit (GPU), the decimal values ​​of the first interpolation weight and the second interpolation weight are greater than or equal to 0 and less than 1.

9. A bilinear interpolation operation device, characterized in that: include: Three linear interpolation modules, each of which includes a plurality of selectors and an adder; A first linear interpolation module, configured to use a plurality of selectors and an adder to perform a linear interpolation on the first data to be interpolated and the second data to be interpolated according to a first interpolation weight, so as to obtain a first intermediate interpolation result; A second linear interpolation module is used to use a plurality of selectors and an adder to perform a linear interpolation on the third data to be interpolated and the fourth data to be interpolated according to the first interpolation weight to obtain a second intermediate interpolation result; The third linear interpolation module is used to use multiple selectors and an adder to perform linear interpolation on the first intermediate interpolation result and the second intermediate interpolation result according to the second interpolation weight to obtain a target bilinear interpolation result.

10. A bilinear interpolation method, characterized in that: The method is applied to a bilinear interpolation operation device, the bilinear interpolation operation device includes a linear interpolation module, the linear interpolation module includes a plurality of selectors and an adder; the method includes: Using the multiple selectors and the adder in the linear interpolation module, according to the first interpolation weight, a linear interpolation is performed on the first data to be interpolated and the second data to be interpolated to obtain a first intermediate interpolation result; Using the multiple selectors and the adder in the linear interpolation module, and according to the first interpolation weight, performing a linear interpolation on the third data to be interpolated and the fourth data to be interpolated to obtain a second intermediate interpolation result; Using the multiple selectors and the adder in the linear interpolation module, a linear interpolation is performed on the first intermediate interpolation result and the second intermediate interpolation result according to a second interpolation weight to obtain a target bilinear interpolation result.

11. A bilinear interpolation method, characterized in that: The method is applied to a bilinear interpolation operation device, the bilinear interpolation operation device includes three linear interpolation modules, each of which includes a plurality of selectors and an adder; the method includes: Using a plurality of selectors and an adder in the first linear interpolation module, according to the first interpolation weight, a linear interpolation is performed on the first data to be interpolated and the second data to be interpolated to obtain a first intermediate interpolation result; Using a plurality of selectors and an adder in the second linear interpolation module, according to the first interpolation weight, a linear interpolation is performed on the third data to be interpolated and the fourth data to be interpolated to obtain a second intermediate interpolation result; Using multiple selectors and an adder in the third linear interpolation module, a linear interpolation is performed on the first intermediate interpolation result and the second intermediate interpolation result according to a second interpolation weight to obtain a target bilinear interpolation result.

12. An electronic device, characterized in that: include: The bilinear interpolation operation device according to any one of claims 1 to 8, or the bilinear interpolation operation device according to claim 9.

13. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; The processor is configured to call the instructions stored in the memory to execute the method of claim 10 or 11.

14. A computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to claim 10 or 11 is implemented.

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