DSP (Digital Signal Processor) and master-slave core using method thereof, storage medium and program product

Abstract

The invention discloses a DSP (Digital Signal Processor) and a master-slave core using method thereof, a storage medium and a program product, the method is applied to a master core, and comprises the following steps: receiving a command sent by a console, and determining a target slave core to be controlled from a plurality of slave cores according to the command; according to a loading program preset by a DSP program tool, a slave core program corresponding to the target slave core is loaded to a memory area corresponding to the target slave core from a corresponding position in a network or flash; wherein a slave core program corresponding to each slave core is an independent program file, the plurality of program files are written into a flash through a DSP program tool in advance, and the master core and the plurality of slave cores run in different memory spaces; controlling the target slave core through a driver in the master core; according to the method, each algorithm is taken as an independent program file, and the master core performs offline and loading switching on the slave core algorithm program according to a command received from a console, so that the slave core runs different algorithm programs, and the software redefinition equipment is completed.

Description

Technical Field

[0001] The present invention relates to the technical field of master-slave core use of DSP, and in particular to a DSP and a master-slave core use method thereof, a storage medium and a program product. Background Art

[0002] The foundation of informatization and intelligence is digitization, and one of the core technologies of digitization is digital signal processing, which needs to be completed by DSP (Digital Signal Processor) devices to a large extent. In particular, high-performance multi-core DSP has a very wide range of applications: communication, such as modems, data encryption, data compression, spread spectrum communication, error correction coding, videophone, etc.; speech, such as speech coding, speech recognition, speech synthesis, etc.; graphics and images, such as three-dimensional image processing, image compression and transmission, animation, robot vision, etc.; automatic control, such as engine control, voice control, disk control, etc.; household appliances, automotive electronic systems and other application fields.

[0003] The operating mode of a multi-core DSP is usually that multiple cores run different tasks relatively independently. Each core is isolated from each other and can run different operating systems or bare metal programs. It usually adopts the Master / Slaver operating mode, with core 0 as the master core and the other cores as slave cores.

[0004] The AMP system of multi-core DSP often adopts the Master / Slaver mode: 0 core is the master core, accepting external commands, and other cores are slave cores, running algorithms. In order to save costs, software defines the device, and each slave core runs different algorithms to give the device different functions. The traditional approach is to integrate the algorithms used in the slave core program together, and then the master core controls the slave cores to run different algorithms through inter-core communication. However, this will make the algorithm program huge and difficult to maintain. It is even often encountered that different algorithms are developed by different developers or different companies. This involves the confidentiality of technology by different companies, as well as the communication and problem location between the integrator and the developers of each slave core module. This makes the later integration of the project very time-consuming and laborious. Summary of the invention

[0005] The purpose of the present invention is to provide a DSP and its master-slave core usage method, storage medium and program product, so that each algorithm can be used as an independent program file. The master core can take the slave core algorithm program offline and load and switch it according to the command received from the console, so that the slave core can run different algorithm programs to complete the software redefinition of the device.

[0006] A first aspect of an embodiment of the present invention provides a method for using a master and slave core of a DSP, the method being applied to a master core and comprising:

[0007] receiving a command sent by the control console, and determining a target slave core to be controlled from a plurality of slave cores according to the command;

[0008] According to the loading program pre-set by the DSP program tool, the slave core program corresponding to the target slave core is loaded from the network or the corresponding position in the flash into the memory area corresponding to the target slave core; wherein the slave core program corresponding to each of the slave cores is an independent program file, and a plurality of the program files are pre-written into the flash by the DSP program tool, and the master core and the plurality of slave cores run in different memory spaces;

[0009] The target slave core is controlled by the driver in the master core so that the target slave core runs the corresponding slave core program.

[0010] Furthermore, before the slave core program corresponding to the target slave core is loaded into the memory area corresponding to the target slave core from the corresponding position in the slave network or flash, the method includes:

[0011] resetting the target slave core;

[0012] The controlling the target slave core through the driver in the master core includes:

[0013] The target slave core is enabled.

[0014] Furthermore, the slave core program is converted from ELF to .bin by a tool chain and then stored in the flash, wherein the tool chain is obtained by organizing the DSP program tool.

[0015] Furthermore, the slave core program is developed based on a program open template, and the program open template integrates a memory allocation link script and the tool chain.

[0016] Furthermore, the master core resets the target slave core through the PSC_MDCTL register, and the master core enables the target slave core through the PSC_PTCMD register.

[0017] A second aspect of the present disclosure provides a DSP, the DSP comprising:

[0018] A master core and multiple slave cores;

[0019] The main core is used to execute any one of the methods described in the first aspect.

[0020] In a third aspect, the present disclosure provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor unit as a main core in a DSP, the steps of any method described in the first aspect are implemented. The computer-readable storage medium may be, for example, a non-temporary computer-readable storage medium.

[0021] A fourth aspect of the embodiments of the present disclosure provides a computer program product, including a computer program, which implements the steps of any one of the methods described in the first aspect when executed by a processor unit serving as a main core in a DSP.

[0022] The present invention has at least the following beneficial effects:

[0023] In this solution, the core developers develop the core algorithm programs, and after completion, they only need to burn each core algorithm program to a specific location in the flash. The main core takes the core algorithm program offline and loads and switches it according to the console command received, so that the core runs different algorithm programs, thereby completing the software redefinition of the device and saving costs. The algorithm program in this solution is different from the traditional approach. The traditional approach is that the core program integrates all the algorithms used together. The core algorithm programs in this solution are independent program files, that is, each algorithm is an independent program file. Therefore, the capacity of each program file is smaller than the program file that integrates multiple core algorithms in the prior art, thereby reducing the capacity of the algorithm program, reducing the difficulty of maintenance, and shortening the communication and problem location time between the integrator and the developers of each core module.

[0024] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 The present invention provides a flow chart of a method for using the master and slave cores of a DSP. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0027] In the description of the present invention, it is necessary to understand that the terms "upper", "lower", "front", "back", "left", "right", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0028] Example 1: Combination Figure 1 This embodiment is described.

[0029] This embodiment is a method for using a master and slave core of a DSP. The method is applied to the master core, such as Figure 1 As shown, the method comprises the following steps:

[0030] S101, receiving a command sent by a control console, and determining a target slave core to be controlled from a plurality of slave cores according to the command.

[0031] For example, if the console command carries a unique identifier of a slave core, the master core may determine a target slave core from multiple slave cores based on the unique identifier.

[0032] S102. According to the loader pre-set by the DSP program tool, the slave core program corresponding to the target slave core is loaded from the network or the corresponding position in the flash into the memory area corresponding to the target slave core; wherein each slave core program corresponding to the slave core is an independent program file, and a plurality of the program files are pre-written into the flash by the DSP program tool, and the master core and the plurality of slave cores run in different memory spaces.

[0033] S103: Control the target slave core through the driver in the master core, so that the target slave core runs a corresponding slave core program.

[0034] Since multiple slave cores run in different memory spaces, the slave core programs of different slave cores can be stored in independent storage spaces, which facilitates the master core to manage different slave cores, especially the management of slave core switching and loading, without considering the complexity of switching between slave cores caused by multiple slave cores sharing memory space.

[0035] In this solution, the slave core developers develop the slave core algorithm program, and after completion, they only need to burn each slave core algorithm program to a specific location in the flash. The main core takes the slave core algorithm program offline and loads and switches it according to the console command received, so that the slave core runs a different algorithm program, thereby completing the software redefinition of the device and saving costs. The algorithm program in this solution is different from the traditional approach. The traditional approach is that the slave core program integrates all the algorithms used, and the main core controls the slave core to run different algorithms through inter-core communication. In this solution, the main core controls the slave core to run different algorithms through inter-core communication, and the slave core algorithm program is an independent program file, that is, each algorithm is an independent program file, so the capacity of each program file is smaller than the program file that integrates multiple slave core algorithms in the prior art, thereby reducing the capacity of the algorithm program, reducing the difficulty of maintenance, and shortening the communication and problem location time between the integrator and the developers of each slave core sub-module.

[0036] Before the slave core program corresponding to the target slave core is loaded into the memory area corresponding to the target slave core at the corresponding position in the slave network or flash, the method includes:

[0037] resetting the target slave core;

[0038] The controlling the target slave core through the driver in the master core includes:

[0039] The target slave core is enabled.

[0040] The slave core program is converted from ELF to .bin by a tool chain and then stored in flash. The tool chain is obtained by organizing DSP program tools.

[0041] The tool chain is sorted out and each slave core program is converted from ELF file to .bin file, so that various DSP slave core algorithm programs can be stored in the limited flash space.

[0042] The slave core program is developed based on a program open template, and the program open template integrates a memory allocation link script and the tool chain.

[0043] Based on the program development template, algorithm developers develop their own core algorithm programs. They do not need to integrate the algorithms into one program as in the traditional way, but develop them as independent program files, thus saving costs.

[0044] The master core resets the target slave core through the PSC_MDCTL register, and the master core enables the target slave core through the PSC_PTCMD register.

[0045] The register stores a mark for each slave core. When the mark is 1, the master core resets the target slave core through the PSC_MDCTL register. When the mark is 0, the master core enables the target slave core through the PSC_PTCMD register.

[0046] Based on the same concept, an embodiment of the present disclosure further provides a DSP, which includes a master core and multiple slave cores, wherein the master core is used to execute the method described in Embodiment 1.

[0047] Based on the same concept, an embodiment of the present disclosure further provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor unit serving as a main core in a DSP, the method described in Embodiment 1 is implemented.

[0048] Based on the same concept, an embodiment of the present disclosure further provides a computer program product, including a computer program, which implements the method described in Embodiment 1 when executed by a processor unit serving as a main core in a DSP.

[0049] It should also be noted that the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of further restrictions, the elements defined by the sentence "includes one..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements. The words "first", "second" and the like are used to indicate names, but do not indicate any specific order. The above schematically describes the invention and its implementation methods, which is not restrictive. The invention can be implemented in other specific forms without departing from the spirit or basic features of the invention. What is shown in the accompanying drawings is only one of the implementation methods of the invention, and the actual structure is not limited thereto. Any figure mark in the claims should not limit the claims involved. Therefore, if a person of ordinary skill in the art is inspired by it, and does not deviate from the purpose of the invention, and designs a structural mode and an embodiment similar to the technical solution without creativity, they should all belong to the scope of protection of this patent.

Claims

1. A method for using a master-slave core of a DSP, characterized in that: The method is applied to the main core and includes: receiving a command sent by the control console, and determining a target slave core to be controlled from a plurality of slave cores according to the command; According to the loading program pre-set by the DSP program tool, the slave core program corresponding to the target slave core is loaded from the network or the corresponding position in the flash into the memory area corresponding to the target slave core; wherein the slave core program corresponding to each of the slave cores is an independent program file, and a plurality of the program files are pre-written into the flash by the DSP program tool, and the master core and the plurality of slave cores run in different memory spaces; The target slave core is controlled by the driver in the master core so that the target slave core runs the corresponding slave core program.

2. The method for using the master-slave core of a DSP according to claim 1, characterized in that: Before the slave core program corresponding to the target slave core is loaded into the memory area corresponding to the target slave core at the corresponding position in the slave network or flash, the method includes: resetting the target slave core; The controlling the target slave core through the driver in the master core includes: The target slave core is enabled.

3. The method for using the master-slave core of a DSP according to claim 1, characterized in that: The slave core program is converted from ELF to .bin by a tool chain and then stored in flash. The tool chain is obtained by organizing DSP program tools.

4. The method for using the master-slave core of a DSP according to claim 3, characterized in that: The slave core program is developed based on a program open template, and the program open template integrates a memory allocation link script and the tool chain.

5. The method for using the master-slave core of a DSP according to claim 2, characterized in that: The master core resets the target slave core through the PSC_MDCTL register, and the master core enables the target slave core through the PSC_PTCMD register.

6. A DSP, characterized in that: include: A master core and multiple slave cores; The main core is used to execute the method according to any one of claims 1 to 5.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor unit serving as a main core in a DSP, the steps of the method described in any one of claims 1 to 5 are implemented.

8. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor unit serving as a main core in a DSP, the computer program implements the steps of the method according to any one of claims 1 to 5.

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