Dual-output basic logic unit and FPGA logic packaging method

Abstract

The invention provides a dual-output basic logic unit, which relates to the technical field of field programmable gate array (FPGA) design, and is mainly structurally characterized in that a first output end of a dual-output lookup table is connected with an input end of a first trigger and one input end of a first multiplexer, and an output end of the first trigger is connected with the other input end of the first multiplexer; the output end of the first multiplexer is used as a first total output end of the dual-output basic logic unit; the second output end of the dual-output lookup table is connected with the input end of the second trigger and one input end of the second multiplexer, the output end of the second trigger is connected with the other input end of the second multiplexer, and the output end of the second multiplexer serves as the second total output end of the dual-output basic logic unit. The invention further provides an FPGA logic packaging method based on the dual-output basic logic unit. The method can cover the configurable unit structure of the current mainstream FGPA, can improve the resource utilization rate to a greater extent, and has better adaptability.

Description

Technical Field

[0001] The present invention relates to the field of FPGA design technology, and in particular to a dual-output basic logic unit and an FPGA logic packaging method. Background Art

[0002] At present, the field of FPGA chips is developing rapidly, and related chips are widely used in various industries. At the same time, EDA development tools for FPGA chips are also widely used, and as the scale of chip design grows, higher performance requirements are placed on related tools. As a key stage in the design process, the packaging stage directly affects the difficulty of back-end layout and routing, as well as the delay and area of ​​the final generated circuit. Therefore, improving the performance of the packaging method is of great significance to the entire EDA tool chain.

[0003] Field Programmable Gate Array (FPGA) is a programmable logic device. Its basic architecture includes input and output modules (IOBs), configurable logic blocks (CLBs), and routing resources. These resources can be programmed into various logic functions. Classical packing algorithms are all based on logic clusters with unit block structures, such as VPack and TVPack. The input of VPack is a netlist containing LUT (Look Up Table) and registers, and the output is a netlist of logic clusters. In the first stage of the algorithm, a simple and efficient pattern matching algorithm is used to greedily pack a register and a LUT into a basic logic unit (BLE). In the second stage, these BLEs are packed into logic clusters. In order to reduce the number of CLBs, each logic cluster should be able to reach the CLB capacity as much as possible. Secondly, the input of each cluster should be as small as possible. The absorption priority is evaluated by the number of collinear networks of the basic logic unit and the currently formed CLB. However, the algorithm greedily considers area optimization during the packing process, and does not consider the timing effect after packing. The TVPack algorithm is based on the VPack algorithm. In addition to considering the packing capacity, it also considers the number of cluster connections on the critical path. The local interconnection within the cluster is faster than the interconnection between logic clusters. Circuit delay can be effectively reduced by reducing the number of connections between logic clusters on the critical path. However, the algorithm does not provide an effective delay model when calculating the critical path, resulting in a large difference between the critical path calculation and the actual circuit. The classic algorithms VPack and TVPack have specific limitations for BLE and only support a mode where one LUT drives a single register. In reality, the BLE units in the CLB architecture provided by different manufacturers are different. The single structure leads to a reduction in the final device utilization and an increase in the final area.

[0004] Some existing patents, such as Chinese patent CN02824998 "Field Programmable Gate Array Core Unit with Efficient Logic Packing", CN200910130548 "A FPGA Logic Unit Model and Its General Packing Algorithm", and CN201110028805 "FPGA Programmable Logic Block General Packing Method", all involve structures of single-output LUT and single-output BLE. The traditional single-output LUT and single-output BLE structures are as follows: Figure 1 shown.

[0005] Based on the timing model calculation ambiguity and single BLE structure problems existing in the current classic packaging algorithm, building a more adaptable BLE and a more accurate timing model is the key to ensuring that the final circuit has high device utilization and timing. Summary of the invention

[0006] Based on the above problems, the purpose of the present invention is to provide a dual-output basic logic unit and FPGA logic packaging method, which can cover the configurable unit structure of the current mainstream FGPA, can improve resource utilization to a greater extent, and has better adaptability.

[0007] The technical solution adopted by the present invention to achieve its invention object is a dual-output basic logic unit, including a dual-output lookup table, a first trigger, a second trigger, a first multiplexer, and a second multiplexer;

[0008] The specific structure of the dual-output lookup table is:

[0009] The output end of the first lookup table is connected to an input end of the third multiplexer, the output end of the second lookup table is connected to another input end of the third multiplexer, the output end of the third multiplexer serves as the first output end of the dual-output lookup table, and the output end of the second lookup table serves as the second output end of the dual-output lookup table; the first lookup table and the second lookup table share an input signal;

[0010] The first output terminal of the dual-output lookup table is connected to the input terminal of the first trigger and one input terminal of the first multiplexer, and the output terminal of the first trigger is connected to the other input terminal of the first multiplexer; the output terminal of the first multiplexer serves as the first total output terminal of the dual-output basic logic unit;

[0011] The second output end of the dual-output lookup table is connected to the input end of the second trigger and one input end of the second multiplexer, and the output end of the second trigger is connected to another input end of the second multiplexer; the output end of the second multiplexer serves as the second total output end of the dual-output basic logic unit.

[0012] Further, the control end of the third multiplexer is connected to another input signal as a control signal, and a single LUT function is realized at this time. The search results of all inputs are realized by the control of the control signal, and are output through the first output end of the dual-output lookup table. At this time, the second output end of the dual-output lookup table is not used.

[0013] Further, the control terminal of the third multiplexer is connected to the constant VCC, and the dual-output lookup table is used as two LUTs, wherein the first lookup table is fixedly output to the first output terminal of the dual-output lookup table through the third multiplexer, and the second lookup table is directly output through the second output terminal of the dual-output lookup table.

[0014] The present invention also provides an FPGA logic packaging method based on the above dual-output basic logic unit, comprising the following steps:

[0015] S1. Logic synthesis generates a netlist with lookup tables and flip-flops as basic units;

[0016] S2, packing two lookup tables satisfying the requirement that the number of input signal paths does not exceed 5 into a dual-output lookup table mode;

[0017] S3, searching for the trigger behind the dual-output lookup table, if there are triggers in both output channels, packaging the dual-output lookup table, the trigger and the multiplexer into a dual-output basic logic unit;

[0018] S4. Pack the dual-output basic logic units obtained in the previous step into the configurable logic block until all the basic logic units are packed.

[0019] In specific implementation, if there is only one trigger in the two output channels in step S3, they are packaged as a traditional single-output basic logic unit for use.

[0020] In order to be closer to the actual chip delay, the present invention also provides another FPGA logic packaging method based on the above dual-output basic logic unit, introducing a line load model in the timing estimation, specifically including the following steps:

[0021] S1. Logic synthesis generates a netlist with lookup tables and flip-flops as basic units;

[0022] S2, packing two lookup tables satisfying the requirement that the number of input signal paths does not exceed 5 into a dual-output lookup table mode;

[0023] S3, searching for the trigger behind the dual-output lookup table, if there are triggers in both output channels, packaging the dual-output lookup table, the trigger and the multiplexer into a dual-output basic logic unit;

[0024] S4, loading a line load model database, wherein the line load model is defined in a cell library;

[0025] S5. Constructing a timing model between dual-output basic logic units according to the line load model;

[0026] S6. Calculate the critical path of the netlist according to the timing data, and then calculate the criticality of each dual-output basic logic unit;

[0027] S7. Prioritize packing dual-output basic logic units with high criticality into configurable logic blocks until all basic logic units are packed.

[0028] The beneficial effects of the present invention are:

[0029] (I) In the construction of the basic logic unit BLE, the traditional algorithm only considers a single group of LUT and FF. The present invention expands on the basis of BLE supported by the traditional algorithm, merges the LUTs that meet the common input of no more than 5 into a LUT_O2 mode, expands the output of the LUT lookup table to two outputs and drives multiple triggers, and then constructs a dual-output basic logic unit with two outputs. It is compatible with the traditional BLE structure and can cover the current mainstream FGPA configurable unit structure, which can improve the utilization of hardware resources to a greater extent and has better adaptability.

[0030] (ii) Although the delay cannot be accurately evaluated before the circuit is laid out and wired, the delay model at this stage has a great impact on the final generated circuit. When performing static timing analysis in the RTL code synthesis stage, each manufacturer provides the delay and power consumption information of the standard unit, but the interconnection line still has no physical information. In order to more accurately reflect the delay of the actual chip, the present invention introduces the wire load model of the prior art when evaluating the delay. Before layout and wiring, the wire load model can be used to estimate the capacitance, resistance and area overhead caused by the interconnection line. The wire load model depends on the area of ​​the design module, that is, different load models can be selected for modules of different areas. Introducing the wire load model in the timing estimation is closer to the actual chip delay, so that the generated circuit timing is easier to converge. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of the structure of the traditional basic logic unit BLE;

[0032] Figure 2 Schematic diagram of the structure of a dual-output basic logic unit (BLE_O2) according to Embodiment 1 of the present invention;

[0033] Figure 3 Schematic diagram of the structure of a dual-output lookup table (LUT_O2) according to Embodiment 1 of the present invention;

[0034] Figure 4 This is a complete FPGA tool chain flow chart;

[0035] Figure 5 This is a flow chart of a logic packaging method according to Embodiment 2 of the present invention;

[0036] Figure 6 This is a flow chart of the logic packaging method according to Embodiment 3 of the present invention. DETAILED DESCRIPTION

[0037] In order to more clearly understand the above-mentioned objects, features and advantages of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] Example 1

[0039] Figures 2-3 A specific implementation of the dual-output basic logic unit of the present invention is shown, including a dual-output lookup table LUT_O2, a first flip-flop FF1, a second flip-flop FF2, a first multiplexer MUX1, and a second multiplexer MUX1;

[0040] The specific structure of the dual-output lookup table is:

[0041] The output LUT_O2 of the first lookup table LUT1 is connected to an input end of the third multiplexer MUX3, the output end of the second lookup table LUT2 is connected to another input end of the third multiplexer MUX3, the output end of the third multiplexer MUX3 serves as the first output end O1 of the dual-output lookup table LUT_O2, and the output end of the second lookup table LUT2 serves as the second output end O2 of the dual-output lookup table LUT_O2; the first lookup table LUT1 and the second lookup table LUT2 of this embodiment are both 5-input lookup tables, and the first lookup table LUT1 and the second lookup table LUT2 share 5 input signals I1-I5;

[0042] The control terminal of the third multiplexer MUX3 is connected to the sixth input signal I6 as a control signal, and a single 6-input LUT function is implemented at this time. The search results of the 6-input signals are realized by the control of I6, and are output through the first output terminal O1 of the dual-output lookup table LUT_O2. At this time, the second output terminal O2 of the dual-output lookup table LUT_O2 is not used; or, the control terminal of the third multiplexer MUX3 is connected to the constant VCC. At this time, the specific structure of the dual-output lookup table is used as 2 LUTs, wherein the first lookup table LUT1 is fixedly output through the third multiplexer MUX3 to the first output terminal O1 of the dual-output lookup table LUT_O2, and the second lookup table LUT2 is directly output through the second output terminal O2 of the dual-output lookup table LUT_O2.

[0043] The first output terminal O1 of the dual-output lookup table LUT_O2 is connected to the input terminal of the first trigger FF1 and one input terminal of the first multiplexer MUX1, and the output terminal of the first trigger FF1 is connected to the other input terminal of the first multiplexer MUX1; the output terminal of the first multiplexer MUX1 serves as the first total output terminal OUT1 of the dual-output basic logic unit BLE_O2;

[0044] The second output terminal O2 of the dual-output lookup table LUT_O2 is connected to the input terminal of the second trigger FF2 and one input terminal of the second multiplexer MUX2, and the output terminal of the second trigger FF2 is connected to another input terminal of the second multiplexer MUX2; the output terminal of the second multiplexer MUX2 serves as the second total output terminal OUT2 of the dual-output basic logic unit BLE_O2.

[0045] Example 2

[0046] A complete FPGA tool chain process is as follows: Figure 4 As shown, with respect to the step of "packaging and generating a logic cluster-level netlist on the FPGA structure", the main improvement of this embodiment is to construct a more adaptable dual-output basic logic unit BLE_O2.

[0047] Figure 5 A specific implementation of the FPGA logic packaging method of the present invention is shown. This method is based on the dual-output basic logic unit constructed in Example 1 and specifically includes the following steps:

[0048] S1. Logic synthesis generates a netlist with lookup tables and flip-flops as basic units;

[0049] S2, packing two lookup tables satisfying the requirement that the number of input signal paths does not exceed 5 into a dual-output lookup table LUT_O2 mode;

[0050] S3, searching for the trigger behind the dual-output lookup table LUT_O2, if there are triggers in both output channels, packaging the dual-output lookup table LUT_O2, the trigger and the multiplexer into a dual-output basic logic unit BLE_O2;

[0051] S4. Pack the dual-output basic logic unit BLE_O2 obtained in the previous step into the configurable logic block until all the basic logic units are packed.

[0052] Example 3

[0053] Figure 6Another specific implementation of the FPGA logic packaging method of the present invention is shown. This method is also based on the dual-output basic logic unit constructed in Example 1. Compared with Example 2, in addition to constructing a more adaptable dual-output basic logic unit BLE_O2, a line load model is also introduced in the timing estimation, which specifically includes the following steps:

[0054] S1. Logic synthesis generates a netlist with lookup tables and flip-flops as basic units;

[0055] S2, packing two lookup tables satisfying the requirement that the number of input signal paths does not exceed 5 into a dual-output lookup table LUT_O2 mode;

[0056] S3, searching for the trigger behind the dual-output lookup table LUT_O2, if there are triggers in both output channels, packaging the dual-output lookup table LUT_O2, the trigger and the multiplexer into a dual-output basic logic unit BLE O2;

[0057] S4, loading a line load model database, wherein the line load model is defined in a cell library;

[0058] S5. Construct a timing model between dual-output basic logic units BLE_O2 according to the line load model;

[0059] S6. Calculate the critical path of the netlist according to the timing data, and then calculate the criticality of each dual-output basic logic unit BLE_O2;

[0060] S7. Prioritize packing the dual-output basic logic unit BLE_O2 with high criticality into the configurable logic block until all the basic logic units are packed.

Claims

1. A dual-output basic logic unit, characterized in that: It includes a dual-output lookup table (LUT_O2), a first flip-flop (FF1), a second flip-flop (FF2), a first multiplexer (MUX1), and a second multiplexer (MUX1); The specific structure of the dual-output lookup table (LUT_O2) is: The output end of the first lookup table (LUT1) is connected to an input end of the third multiplexer (MUX3), the output end of the second lookup table (LUT2) is connected to another input end of the third multiplexer (MUX3), the output end of the third multiplexer (MUX3) serves as the first output end (O1) of the dual-output lookup table (LUT_O2), and the output end of the second lookup table (LUT2) serves as the second output end (O2) of the dual-output lookup table (LUT_O2); the first lookup table (LUT1) and the second lookup table (LUT2) share an input signal; The first output end (O1) of the dual-output lookup table (LUT_O2) is connected to the input end of the first trigger (FF1) and one input end of the first multiplexer (MUX1), and the output end of the first trigger (FF1) is connected to the other input end of the first multiplexer (MUX1); the output end of the first multiplexer (MUX1) serves as the first total output end (OUT1) of the dual-output basic logic unit (BLE_O2); The second output end (O2) of the dual-output lookup table (LUT_O2) is connected to the input end of the second trigger (FF2) and one input end of the second multiplexer (MUX2), and the output end of the second trigger (FF2) is connected to the other input end of the second multiplexer (MUX2); the output end of the second multiplexer (MUX2) serves as the second total output end (OUT2) of the dual-output basic logic unit (BLE_O2).

2. A dual-output basic logic unit according to claim 1, characterized in that: The control terminal of the third multiplexer (MUX3) is connected to another input signal as a control signal.

3. A dual-output basic logic unit according to claim 1, characterized in that: A control terminal of the third multiplexer (MUX3) is connected to a constant VCC.

4. An FPGA logic packaging method based on the dual-output basic logic unit of claim 1, characterized in that: The steps include: S1. Logic synthesis generates a netlist with lookup tables and flip-flops as basic units; S2, packing two lookup tables satisfying that the number of input signal paths does not exceed 5 into a dual-output lookup table (LUT_O2) mode; S3, searching for the trigger behind the dual-output lookup table (LUT_O2), if there are triggers in both output channels, packaging the dual-output lookup table (LUT_O2), the trigger and the multiplexer into a dual-output basic logic unit (BLE_O2); S4. Pack the dual-output basic logic unit (BLE_O2) obtained in the previous step into the configurable logic block until all the basic logic units are packed.

5. The FPGA logic packaging method based on the dual-output basic logic unit of claim 1 is characterized in that: The steps include: S1. Logic synthesis generates a netlist with lookup tables and flip-flops as basic units; S2, packing two lookup tables satisfying that the number of input signal paths does not exceed 5 into a dual-output lookup table (LUT_O2) mode; S3, searching for the trigger behind the dual-output lookup table (LUT_O2), if there are triggers in both output channels, packaging the dual-output lookup table (LUT_O2), the trigger and the multiplexer into a dual-output basic logic unit (BLE_O2); S4, loading a line load model database, wherein the line load model is defined in a cell library; S5. Construct a timing model between dual-output basic logic units (BLE_O2) according to the line load model; S6. Calculate the critical path of the netlist based on the timing data, and then calculate the criticality of each dual-output basic logic unit (BLE_O2); S7. Prioritize packing the dual-output basic logic unit (BLE_O2) with high criticality into the configurable logic block until all the basic logic units are packed.

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