Intelligent station table generation system and method for SMT (Surface Mount Technology)

Abstract

The invention discloses an intelligent station table generation system and method for SMT, and relates to the technical field of SMT, and the system comprises a data processing module which is used for importing a BOM file and PCB design information, carrying out the data analysis, verification and arrangement of the BOM file and the PCB design information, and recording and processing an engineering change notice at the same time; the image recognition module is used for automatically recognizing and analyzing component layout and component types on the PCB, and comparing and verifying with an analysis result of the data processing module; the position layout module realizes optimization of component layout by comprehensively considering the layout density of components on a PCB (Printed Circuit Board) and the chip mounting efficiency of a chip mounter; and the station table optimization and output module receives the data from the data processing module and the image recognition module, adjusts and optimizes the station table according to the layout result of the layout density and efficiency optimization module, and outputs a final station table result.

Description

Technical Field

[0001] The present invention relates to the technical field of SMT patches, and in particular to an intelligent station table generation system and method for SMT patches. Background Art

[0002] In the production process of SMT (surface mount technology), the station table is an indispensable basic information to ensure the accurate loading and efficient operation of the placement machine. The traditional station table production process is highly dependent on manual operation, covering many tedious steps from manually organizing the BOM (bill of materials), checking material information one by one, to setting the station according to the specific needs of the placement machine. This manual-dependent method is not only time-consuming and labor-intensive, but also prone to errors. Especially in the face of complex product structures and a wide variety of materials, the error rate often increases significantly, which directly affects production efficiency and product quality.

[0003] With the continuous progress of information technology, some preliminary automation tools have been gradually introduced into the SMT production process to assist in the production of station tables. However, the functions of these tools are often relatively limited. They can only process BOM files or placement machine position information in a specific format, lacking sufficient flexibility and wide compatibility. In addition, they usually can only provide basic generation functions for station tables, but cannot automatically check and error prompt the generated station tables, which means that users still need to spend a lot of time and energy on manual inspection and correction, which undoubtedly increases production costs and reduces production efficiency. At the same time, with the vigorous rise of intelligent manufacturing technology, more and more companies have begun to actively explore the deep integration of intelligent technology into the SMT patch process. Although some progress has been made, the existing station table generation system still faces many challenges, such as slow data processing speed, image recognition accuracy needs to be improved, and the station layout is not reasonable. These problems seriously restrict the application effect of the station table generation system and hinder its wide promotion and in-depth application in SMT production. Summary of the invention

[0004] The object of the present invention is to provide a system and method for generating an intelligent station table for SMT patches, so as to solve the problems raised in the prior art.

[0005] To achieve the above-mentioned purpose, the present invention provides the following technical solutions: an intelligent station table generation system for SMT patches, the system comprising a data processing module, an image recognition module, a station layout module, and a station table optimization and output module;

[0006] The data processing module is used to import BOM files and PCB board design information and perform data analysis, verification and sorting on them, and record and process engineering change notifications;

[0007] The image recognition module is used to automatically identify and analyze the component layout and component type on the PCB board, and compare and verify with the analysis results of the data processing module;

[0008] The station layout module optimizes the component layout by comprehensively considering the layout density of the components on the PCB board and the placement efficiency of the placement machine;

[0009] The station table optimization and output module receives data from the data processing module and the image recognition module, adjusts and optimizes the station table according to the layout result of the layout density and efficiency optimization module, and outputs the final station table result.

[0010] Furthermore, the data processing module includes a data import and analysis unit, a data verification unit, a change management unit, and a data sorting unit;

[0011] The data import and analysis unit is used to import the BOM file and PCB design information and automatically analyze them, and at the same time back up the original BOM file and PCB board design information;

[0012] The data verification unit automatically checks the errors and omissions in the BOM file, including the completeness, accuracy, consistency and field missing of the data, and performs multi-faceted verification on the PCB design information. If an error is found, the user is shown a specific error message and prompted to make corrections; after the user corrects the error, the relevant information is re-verified until no problem is found and the next step is performed;

[0013] The change management unit is used to record the change notification of the BOM file or PCB design information and prompt the user to make corresponding changes to the BOM file or PCB design information. The user can choose whether to change the information according to the prompt.

[0014] The data sorting unit merges, splits, and sorts the BOM file or PCB design information according to user needs, and stores the sorted information in a database.

[0015] In the above technical scheme, through the data import and analysis unit, the system can automatically process a large amount of data, reduce the burden of manual operation, and back up the original data to prevent loss; the data verification unit can timely discover and correct errors and omissions in the data, and improve the reliability of the data; the change management unit can flexibly respond to engineering changes and ensure timely updating of information; the data sorting unit merges, splits and sorts the data according to user needs, making the data more orderly and easy to manage; the entire data processing module improves the efficiency and accuracy of data processing, and provides a solid foundation for the subsequent generation of intelligent station tables.

[0016] Furthermore, the image recognition module includes a component recognition unit, a layout analysis unit, and a verification and comparison unit;

[0017] The component recognition unit uses a convolutional neural network and a residual network to automatically extract various components on the PCB board and corresponding attribute information through multi-layer convolution and pooling operations;

[0018] The layout parsing unit uses the YOLO target detection algorithm to locate the position of the component in the image and uses the image segmentation technology to segment the components in the image and assign corresponding labels. At the same time, the context reasoning technology is used to analyze the relative position and relationship between the components and the layout of the components on the PCB board to infer the component information that is blocked or difficult to identify;

[0019] The verification and comparison unit is used to receive the parsed BOM file and PCB design information from the data processing module, compare them with the component identification results and layout information results, and compare them according to the set verification rules. If the verification passes, the correct information is output; if it fails, specific error information is output to display to the user to prompt for inspection and modification.

[0020] In the above technical solution, by automatically identifying and analyzing the layout and type of components on the PCB board, the image recognition module can adapt to PCB boards of different models and specifications, thereby improving the flexibility and adaptability of production; at the same time, the component layout is optimized according to the relative position and relationship between the components, thereby improving the recognition accuracy and layout rationality of the components by reducing the overlap and occlusion between the components.

[0021] Furthermore, the station layout module includes a layout density calculation unit, a patch efficiency calculation unit, and a comprehensive optimization target unit;

[0022] The layout density calculation unit calculates the area occupied by each component on the PCB board according to the package size and spacing of the component, according to the formula:

[0023] A i = l i *w i +ΔA i ;

[0024] Among them A i represents the area of ​​the ith element, l i represents the length of the i-th element, w i represents the width of the i-th element, ΔA i It indicates that the extra spacing area reserved for the i-th component in the PCB layout considering the safety distance between components, heat dissipation requirements and layout optimization;

[0025] Calculate the ratio of the area occupied by the laid-out components to the total area on the PCB according to the formula:

[0026]

[0027] Where D represents the component layout density, n represents the total number of components, and A PCB Indicates the total area of ​​the PCB board, A r Indicates the area on the PCB that is reserved and cannot be used for component layout;

[0028] The patch efficiency calculation unit calculates the moving path length of the patch machine during the patch process by calculating the sum of the distances from each component to its previous component or starting point, according to the formula:

[0029]

[0030] Where L p represents the length of the patch path, (x0, y0) represents the starting coordinates of the patch machine, (x1, y1) represents the coordinates of the first component, (x i ,y i ) represents the coordinates of the ith element, (x i+1 ,y i+1 ) represents the coordinates of the i+1th element;

[0031] The patch efficiency is calculated by combining the patch path length, the moving speed of the patch machine, and the patch time, according to the formula:

[0032]

[0033] Where E represents the placement efficiency, v represents the average moving speed of the placement machine, T i represents the patch time of the i-th component;

[0034] The comprehensive optimization target unit comprehensively considers the layout density and patch efficiency, and defines a comprehensive optimization target function F:

[0035]

[0036] Where w1 and w2 are the weight coefficients of component layout density and patch efficiency, respectively, which are used to balance the importance of layout density and patch efficiency in the optimization process and set a comprehensive optimization objective function threshold K.

[0037] In the above technical solution, by adjusting the component layout, the system can balance the layout density and patch efficiency, improve production efficiency and product quality, realize intelligent optimization of component layout, and improve the rationality and efficiency of the station table.

[0038] Furthermore, the station table optimization output module is used to provide a variety of different station table templates, from which the user selects a template, and the system reads the information of the selected station table from the database, and evaluates the performance of the current station table according to the value of the comprehensive optimization objective function F. If the F value is less than the set threshold K, the optimization is stopped and the current station table is output. If it is greater than the threshold K, a group of new station tables are generated as candidates according to the particle swarm algorithm, and each candidate station table is evaluated and compared, and the station table with the smallest F value is selected as the final station table result and output.

[0039] In the above technical solution, the automatic optimization and output of the station table is realized, the performance and adaptability of the station table are improved, and the cost and time of manual optimization are reduced; by providing a variety of templates and optimization algorithms, the system can meet the needs and scenarios of different users, and improve the flexibility and intelligence level of station table generation.

[0040] A method for generating an intelligent station table for SMT patches, the method comprising the following steps:

[0041] Step S100: Import BOM files and PCB board design information and perform data analysis, verification and sorting on them, and record and process engineering change notifications;

[0042] Step S200: automatically identifying and analyzing the component layout and component type on the PCB board, and performing a comparative analysis with the analysis results of the data processing module for comprehensive verification;

[0043] Step S300: optimizing the component layout by comprehensively considering the layout density of the components on the PCB board and the placement efficiency of the placement machine;

[0044] Step S400: receiving data from the data processing module and the image recognition module, adjusting and optimizing the station table according to the layout result of the layout density and efficiency optimization module, and outputting the final station table result;

[0045] The step S100 includes the following steps:

[0046] Step S101 is used to import the BOM file and PCB design information and automatically parse them, while backing up the original BOM file and PCB board design information;

[0047] Step S102 is used to automatically check the errors and omissions in the BOM file, including the completeness, accuracy, consistency and field missing of the data, and perform multi-faceted verification of the PCB design information. If an error is found, the user is shown a specific error message and prompted to make corrections; after the user corrects the error, the relevant information is re-verified until no problem is found, and then the next step is performed;

[0048] Step S103 is used to record the change notification of the BOM file or PCB design information and prompt to make corresponding changes to the BOM file or PCB design information. The user can choose whether to change the information according to the prompt.

[0049] Step S104 merges, splits, and organizes the BOM file or PCB design information according to user requirements, and stores the organized material information in a database.

[0050] The step S200 includes the following steps:

[0051] Step S201 uses a convolutional neural network and a residual network to automatically extract various components on the PCB board and corresponding attribute information through multi-layer convolution and pooling operations;

[0052] Step S202 uses the YOLO target detection algorithm to locate the position of the component in the image and uses image segmentation technology to segment the components in the image and assign corresponding labels. At the same time, the context reasoning technology is used to analyze the relative position and relationship between the components and the layout of the components on the PCB board to infer the information of the components that are blocked or difficult to identify;

[0053] Step S203 is used to receive the parsed BOM file and PCB design information from the data processing module, compare them with the component identification results and layout information results, and compare them according to the set verification rules. If the verification passes, the correct information is output. If it fails, a specific error message is output to display to the user to prompt for inspection and modification.

[0054] The step S300 includes the following steps:

[0055] Step S301 calculates the area occupied by each component on the PCB board by the package size and spacing of the component, according to the formula:

[0056] A i = l i *w i +ΔA i ;

[0057] Among them A i represents the area of ​​the ith element, l i represents the length of the i-th element, w i represents the width of the i-th element, ΔA i It indicates that the extra spacing area reserved for the i-th component in the PCB layout considering the safety distance between components, heat dissipation requirements and layout optimization;

[0058] Step S302 calculates the ratio of the area occupied by the laid-out components to the total area of ​​the PCB according to the formula:

[0059]

[0060] Where D represents the component layout density, n represents the total number of components, and A PCB Indicates the total area of ​​the PCB board, A r Indicates the area on the PCB that is reserved and cannot be used for component layout;

[0061] Step S303 calculates the moving path length of the placement machine during the placement process by calculating the sum of the distances from each component to its previous component or starting point, according to the formula:

[0062]

[0063] Where L p represents the length of the patch path, (x0, y0) represents the starting coordinates of the patch machine, (x1, y1) represents the coordinates of the first component, (x i ,y i ) represents the coordinates of the ith element, (x i+1 ,y i+1 ) represents the coordinates of the i+1th element;

[0064] Step S304 calculates the patch efficiency by combining the patch path length, the moving speed of the patch machine, and the patch time, according to the formula:

[0065]

[0066] Where E represents the placement efficiency, v represents the average moving speed of the placement machine, T i represents the patch time of the i-th component;

[0067] Step S305 comprehensively considers the layout density and patch efficiency and defines a comprehensive optimization objective function F:

[0068]

[0069] Where w1 and w2 are the weight coefficients of component layout density and patch efficiency, respectively, which are used to balance the importance of layout density and patch efficiency in the optimization process, set a comprehensive optimization objective function threshold K, and evaluate the performance of the station table.

[0070] In step S500, the system provides a variety of different station table templates, and the user selects a template from them. The system reads the information of the selected station table from the database, and evaluates the performance of the current station table according to the value of the comprehensive optimization objective function F. If the F value is less than the set threshold K, the optimization is stopped and the current station table is output. If it is greater than the threshold K, a group of new station tables are generated as candidates according to the particle swarm algorithm, and each candidate station table is evaluated and compared. The station table with the smallest F value is selected as the final station table result and output.

[0071] Compared with the prior art, the present invention has the following beneficial effects:

[0072] The present invention can greatly reduce the errors and omissions of manual operation through accurate analysis, verification and arrangement of BOM files and PCB board design information, as well as automatic identification and analysis of components, improve the accuracy and efficiency of station table generation, and optimize component layout by comprehensively considering component layout density and patch efficiency.

[0073] The present invention can process PCB boards of different models and specifications and adapt to the production needs of different customers. By optimizing the component layout, the system can reduce the overlap and occlusion between components, improve the recognition accuracy and layout rationality of the components, thereby further improving the production efficiency and product quality; at the same time, the system provides a variety of station table templates and optimization algorithms to meet the needs and scenarios of different users, and improve the flexibility and efficiency of station table generation. BRIEF DESCRIPTION OF THE DRAWINGS

[0074] Figure 1 A system module diagram of an intelligent station table generation system for SMT patches according to the present invention;

[0075] Figure 2 A method flow chart of a method for generating an intelligent station table for SMT patches according to the present invention; DETAILED DESCRIPTION

[0076] Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in the field without making any creative work shall fall within the scope of protection of the present invention.

[0077] Example: Figure 1-Figure 2 As shown, the present invention provides a technical solution, an intelligent station table generation system for SMT patches, the system comprising a data processing module, an image recognition module, a station layout module, and a station table optimization and output module;

[0078] The data processing module is used to import BOM files and PCB board design information and perform data analysis, verification and sorting on them, and record and process engineering change notifications;

[0079] The image recognition module is used to automatically identify and analyze the component layout and component type on the PCB board, and compare and verify with the analysis results of the data processing module;

[0080] The station layout module optimizes the component layout by comprehensively considering the layout density of the components on the PCB board and the placement efficiency of the placement machine;

[0081] The station table optimization and output module receives data from the data processing module and the image recognition module, adjusts and optimizes the station table according to the layout result of the layout density and efficiency optimization module, and outputs the final station table result.

[0082] The data processing module includes a data import and analysis unit, a data verification unit, a change management unit, and a data sorting unit;

[0083] The data import and analysis unit is used to import the BOM file and PCB design information and automatically analyze them, and at the same time back up the original BOM file and PCB board design information;

[0084] The data verification unit automatically checks the errors and omissions in the BOM file, including the completeness, accuracy, consistency and field missing of the data, and performs multi-faceted verification on the PCB design information. If an error is found, the user is shown a specific error message and prompted to make corrections; after the user corrects the error, the relevant information is re-verified until no problem is found and the next step is performed;

[0085] The change management unit is used to record the change notification of the BOM file or PCB design information and prompt the user to make corresponding changes to the BOM file or PCB design information. The user can choose whether to change the information according to the prompt.

[0086] The data sorting unit merges, splits, and sorts the BOM file or PCB design information according to user needs, and stores the sorted information in a database.

[0087] In the above technical scheme, through the data import and analysis unit, the system can automatically process a large amount of data, reduce the burden of manual operation, and back up the original data to prevent loss; the data verification unit can timely discover and correct errors and omissions in the data, and improve the reliability of the data; the change management unit can flexibly respond to engineering changes and ensure timely updating of information; the data sorting unit merges, splits and sorts the data according to user needs, making the data more orderly and easy to manage; the entire data processing module improves the efficiency and accuracy of data processing, and provides a solid foundation for the subsequent generation of intelligent station tables.

[0088] The image recognition module includes a component recognition unit, a layout analysis unit, and a verification and comparison unit;

[0089] The component recognition unit uses a convolutional neural network and a residual network to automatically extract various components on the PCB board and corresponding attribute information through multi-layer convolution and pooling operations;

[0090] The layout parsing unit uses the YOLO target detection algorithm to locate the position of the component in the image and uses the image segmentation technology to segment the components in the image and assign corresponding labels. At the same time, the context reasoning technology is used to analyze the relative position and relationship between the components and the layout of the components on the PCB board to infer the component information that is blocked or difficult to identify;

[0091] The verification and comparison unit is used to receive the parsed BOM file and PCB design information from the data processing module, compare them with the component identification results and layout information results, and compare them according to the set verification rules. If the verification passes, the correct information is output; if it fails, specific error information is output to display to the user to prompt for inspection and modification.

[0092] In the above technical solution, by automatically identifying and analyzing the layout and type of components on the PCB board, the image recognition module can adapt to PCB boards of different models and specifications, thereby improving the flexibility and adaptability of production; at the same time, the component layout is optimized according to the relative position and relationship between the components, thereby improving the recognition accuracy and layout rationality of the components by reducing the overlap and occlusion between the components.

[0093] The station layout module includes a layout density calculation unit, a patch efficiency calculation unit, and a comprehensive optimization target unit;

[0094] The layout density calculation unit calculates the area occupied by each component on the PCB board according to the package size and spacing of the component, according to the formula:

[0095] A i = l i *w i +ΔA i ;

[0096] Among them A i represents the area of ​​the ith element, l i represents the length of the i-th element, w i represents the width of the i-th element, ΔA i It indicates that the extra spacing area reserved for the i-th component in the PCB layout considering the safety distance between components, heat dissipation requirements and layout optimization;

[0097] Calculate the ratio of the area occupied by the laid-out components to the total area on the PCB according to the formula:

[0098]

[0099] Where D represents the component layout density, n represents the total number of components, and A PCB Indicates the total area of ​​the PCB board, A r Indicates the area on the PCB that is reserved and cannot be used for component layout;

[0100] The patch efficiency calculation unit calculates the moving path length of the patch machine during the patch process by calculating the sum of the distances from each component to its previous component or starting point, according to the formula:

[0101]

[0102] Where L p represents the length of the patch path, (x0, y0) represents the starting coordinates of the patch machine, (x1, y1) represents the coordinates of the first component, (x i ,y i ) represents the coordinates of the ith element, (x i+1 ,y i+1 ) represents the coordinates of the i+1th element;

[0103] The patch efficiency is calculated by combining the patch path length, the moving speed of the patch machine, and the patch time, according to the formula:

[0104]

[0105] Where E represents the placement efficiency, v represents the average moving speed of the placement machine, T i represents the patch time of the i-th component;

[0106] The comprehensive optimization target unit comprehensively considers the layout density and patch efficiency, and defines a comprehensive optimization target function F:

[0107]

[0108] Where w1 and w2 are the weight coefficients of component layout density and patch efficiency, respectively, which are used to balance the importance of layout density and patch efficiency in the optimization process and set a comprehensive optimization objective function threshold K.

[0109] In the above technical solution, by adjusting the component layout, the system can balance the layout density and patch efficiency, improve production efficiency and product quality, realize intelligent optimization of component layout, and improve the rationality and efficiency of the station table.

[0110] The station table optimization output module is used to provide a variety of different station table templates, from which the user selects a template. The system reads the information of the selected station table from the database, and evaluates the performance of the current station table according to the value of the comprehensive optimization objective function F. If the F value is less than the set threshold K, the optimization is stopped and the current station table is output. If it is greater than the threshold K, a group of new station tables are generated as candidates according to the particle swarm algorithm, and each candidate station table is evaluated and compared. The station table with the smallest F value is selected as the final station table result and output.

[0111] In the above technical solution, the automatic optimization and output of the station table is realized, the performance and adaptability of the station table are improved, and the cost and time of manual optimization are reduced; by providing a variety of templates and optimization algorithms, the system can meet the needs and scenarios of different users, and improve the flexibility and intelligence level of station table generation.

[0112] A method for generating an intelligent station table for SMT patches, the method comprising the following steps:

[0113] Step S100: Import BOM files and PCB board design information and perform data analysis, verification and sorting on them, and record and process engineering change notifications;

[0114] Step S200: automatically identifying and analyzing the component layout and component type on the PCB board, and performing a comparative analysis with the analysis results of the data processing module for comprehensive verification;

[0115] Step S300: optimizing the component layout by comprehensively considering the layout density of the components on the PCB board and the placement efficiency of the placement machine;

[0116] Step S400: receiving data from the data processing module and the image recognition module, adjusting and optimizing the station table according to the layout result of the layout density and efficiency optimization module, and outputting the final station table result;

[0117] The step S100 includes the following steps:

[0118] Step S101 is used to import the BOM file and PCB design information and automatically parse them, while backing up the original BOM file and PCB board design information;

[0119] Step S102 is used to automatically check the errors and omissions in the BOM file, including the completeness, accuracy, consistency and field missing of the data, and perform multi-faceted verification of the PCB design information. If an error is found, the user is shown a specific error message and prompted to make corrections; after the user corrects the error, the relevant information is re-verified until no problem is found, and then the next step is performed;

[0120] Step S103 is used to record the change notification of the BOM file or PCB design information and prompt to make corresponding changes to the BOM file or PCB design information. The user can choose whether to change the information according to the prompt.

[0121] Step S104 merges, splits, and organizes the BOM file or PCB design information according to user requirements, and stores the organized material information in a database.

[0122] The step S200 includes the following steps:

[0123] Step S201 uses a convolutional neural network and a residual network to automatically extract various components on the PCB board and corresponding attribute information through multi-layer convolution and pooling operations;

[0124] Step S202 uses the YOLO target detection algorithm to locate the position of the component in the image and uses image segmentation technology to segment the components in the image and assign corresponding labels. At the same time, the context reasoning technology is used to analyze the relative position and relationship between the components and the layout of the components on the PCB board to infer the information of the components that are blocked or difficult to identify;

[0125] Step S203 is used to receive the parsed BOM file and PCB design information from the data processing module, compare them with the component identification results and layout information results, and compare them according to the set verification rules. If the verification passes, the correct information is output. If it fails, a specific error message is output to display to the user to prompt for inspection and modification.

[0126] The step S300 includes the following steps:

[0127] Step S301 calculates the area occupied by each component on the PCB board by the package size and spacing of the component, according to the formula:

[0128] A i = l i *w i +ΔA i ;

[0129] Among them A i represents the area of ​​the ith element, l i represents the length of the i-th element, w i represents the width of the i-th element, ΔA i It indicates that the extra spacing area reserved for the i-th component in the PCB layout considering the safety distance between components, heat dissipation requirements and layout optimization;

[0130] Step S302 calculates the ratio of the area occupied by the laid-out components to the total area of ​​the PCB according to the formula:

[0131]

[0132] Where D represents the component layout density, n represents the total number of components, and A PCB Indicates the total area of ​​the PCB board, A r Indicates the area on the PCB that is reserved and cannot be used for component layout;

[0133] Step S303 calculates the moving path length of the placement machine during the placement process by calculating the sum of the distances from each component to its previous component or starting point, according to the formula:

[0134]

[0135] Where L p represents the length of the patch path, (x0, y0) represents the starting coordinates of the patch machine, (x1, y1) represents the coordinates of the first component, (x i ,y i ) represents the coordinates of the ith element, (x i+1 ,y i+1 ) represents the coordinates of the i+1th element;

[0136] Step S304 calculates the patch efficiency by combining the patch path length, the moving speed of the patch machine, and the patch time, according to the formula:

[0137]

[0138] Where E represents the placement efficiency, v represents the average moving speed of the placement machine, T i represents the patch time of the i-th component;

[0139] Step S305 comprehensively considers the layout density and patch efficiency and defines a comprehensive optimization objective function F:

[0140]

[0141] Where w1 and w2 are the weight coefficients of component layout density and patch efficiency, respectively, which are used to balance the importance of layout density and patch efficiency in the optimization process, set a comprehensive optimization objective function threshold K, and evaluate the performance of the station table.

[0142] In step S500, the system provides a variety of different station table templates, and the user selects a template from them. The system reads the information of the selected station table from the database, and evaluates the performance of the current station table according to the value of the comprehensive optimization objective function F. If the F value is less than the set threshold K, the optimization is stopped and the current station table is output. If it is greater than the threshold K, a group of new station tables are generated as candidates according to the particle swarm algorithm, and each candidate station table is evaluated and compared. The station table with the smallest F value is selected as the final station table result and output.

[0143] In this embodiment, the BOM file and PCB design information are first imported and automatically parsed. The BOM file contains the number, name, package and other information of the component, and the PCB design information contains the size of the PCB board, component layout, etc. At the same time, the original BOM file and PCB design information are backed up;

[0144] Automatically check the errors and omissions in the BOM file, the completeness, accuracy, consistency and field missing of the data, and perform multi-faceted verification of the PCB design information, such as whether the component spacing and component packaging meet the standards. If an error is found, the user will be prompted to make corrections. For example, if the number of a component in the BOM file is missing, the user will be prompted to add the number. After the user corrects the error, the relevant information will be re-verified until no problem is found.

[0145] Record the change notifications of BOM files or PCB design information, such as component replacement, component quantity change, etc., prompt the user to make corresponding changes to the BOM files or PCB design information, and the user can choose whether to change the information according to the prompt; merge, split, and organize the BOM files or PCB design information according to user needs, and store the organized information in the database;

[0146] Using convolutional neural networks and residual networks, through multi-layer convolution and pooling operations, various components on the PCB board and corresponding attribute information, such as component number, name, package, etc., are automatically extracted; the YOLO target detection algorithm is used to locate the position of the component in the image; the image segmentation technology is used to segment the components in the image and assign corresponding labels; the contextual reasoning technology is used to analyze the relative position and relationship between components, as well as the layout of components on the PCB board, and infer the information of components that are blocked or difficult to identify;

[0147] Receive the parsed BOM file and PCB design information from the data processing module, compare them with the component identification results and layout information results, and compare them according to the set verification rules, including component number and name verification, component package verification, component position verification, component quantity verification, component spacing verification, and component direction verification; for example, component number and name verification rules: check whether the component number and name in the BOM file are consistent with the number and name in the component identification result; in this embodiment, the number of a component in the BOM file is "C101" and the name is "capacitor", and the verification and comparison unit will check whether there is a component with the number "C101" and the name "capacitor" in the component identification result; if they are inconsistent, an error message is output to prompt the user to check the BOM file or component identification result; if the verification passes, the correct information is output;

[0148] In this embodiment, it is assumed that there is a component A1 on a PCB board, whose length is 10mm and width is 5mm, and the required additional spacing area is 2mm. 2 , then according to the formula, the area is A1 = 52mm 2 , the total area of ​​PCB board is 1000mm 2 , the area A that is not available for component layout r 50mm 2 , the total number of components is 10 and all components are of the same size and spacing, then the component layout density of the PCB board is calculated according to the formula D = 0.547;

[0149] Set the starting coordinates (x0, y0) of the placement machine to (0, 0), the average moving speed of the placement machine to 15 mm / s, the component placement time to 0.5 s, the coordinates of component A1 to (10, 10), the coordinates of component A2 to (20, 10), the coordinates of component A3 to (30, 10), ..., component A 10 The coordinates are (100,10), then the patch path length L is calculated according to the formula p =90mm, then calculate the patch efficiency E≈0.9; set the weight coefficients w1 and w2 of component layout density and patch efficiency to 0.6 and 0.4 respectively, and set the comprehensive optimization target threshold K to 0.6. According to the formula, F≈0.712 is calculated, which is greater than the set threshold K, so the station table needs to be optimized;

[0150] The particle swarm algorithm is used to optimize the station table. First, the number of particle swarms, that is, the number of candidate station tables, is set. An initial position is randomly generated for each particle, which represents an initial station table solution. The initial position can be generated by randomly selecting parameters such as the position and rotation angle of the component. An initial speed is set for each particle, which determines the direction and distance of movement of the particle in the search space. The initial speed can be set to zero or a small value can be randomly generated. A fitness function is defined to evaluate the quality of each station table. The fitness function is constructed based on factors such as the compactness of the station table layout, the spacing between components, and the length of the routing. The station table it represents is substituted into the fitness function to calculate the fitness value of each particle. The particle swarm algorithm is updated according to the speed. Formula, update the speed of each particle, and update the position of each particle according to the updated speed, that is, generate a new station table solution. For each particle, compare the fitness value of the current station table with the fitness value of the individual optimal position. If the fitness value of the current position is better, update the individual optimal position to this position, compare the fitness values ​​of the individual optimal positions among all particles, and find the global optimal position, that is, the optimal station table. Repeat the above steps, continuously iterate and update the speed and position of the particles, generate a new candidate station table, and evaluate its fitness value. As the iteration proceeds, the particle swarm will gradually converge to the vicinity of the optimal solution, that is, generate a high-quality station table; among all candidate station tables, select the station table with the smallest fitness value as the final station table result and output it.

[0151] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An intelligent station table generation system for SMT patches, characterized by: The system includes a data processing module, an image recognition module, a station layout module, and a station table optimization and output module; The data processing module is used to import BOM files and PCB board design information and perform data analysis, verification and sorting on them, and record and process engineering change notifications; The image recognition module is used to automatically identify and analyze the component layout and component type on the PCB board, and compare and verify with the analysis results of the data processing module; The station layout module optimizes the component layout by comprehensively considering the layout density of the components on the PCB board and the placement efficiency of the placement machine; The station table optimization and output module receives data from the data processing module and the image recognition module, adjusts and optimizes the station table according to the layout result of the layout density and efficiency optimization module, and outputs the final station table result.

2. According to claim 1, an intelligent station table generation system for SMT patches is characterized by: The data processing module includes a data import and analysis unit, a data verification unit, a change management unit, and a data sorting unit; The data import and analysis unit is used to import the BOM file and PCB design information and automatically analyze them, and at the same time back up the original BOM file and PCB board design information; The data verification unit automatically checks the errors and omissions in the BOM file, including the completeness, accuracy, consistency and field missing of the data, and performs multi-faceted verification on the PCB design information. If an error is found, the user is shown a specific error message and prompted to make corrections; after the user corrects the error, the relevant information is re-verified until no problem is found and the next step is performed; The change management unit is used to record the change notification of the BOM file or PCB design information and prompt the user to make corresponding changes to the BOM file or PCB design information. The user can choose whether to change the information according to the prompt. The data sorting unit merges, splits, and sorts the BOM file or PCB design information according to user needs, and stores the sorted information in a database.

3. According to claim 1, an intelligent station table generation system for SMT patches is characterized by: The image recognition module includes a component recognition unit, a layout analysis unit, and a verification and comparison unit; The component recognition unit uses a convolutional neural network and a residual network to automatically extract various components on the PCB board and corresponding attribute information through multi-layer convolution and pooling operations; The layout parsing unit uses the YOLO target detection algorithm to locate the position of the component in the image and uses the image segmentation technology to segment the components in the image and assign corresponding labels. At the same time, the context reasoning technology is used to analyze the relative position and relationship between the components and the layout of the components on the PCB board to infer the component information that is blocked or difficult to identify; The verification and comparison unit is used to receive the parsed BOM file and PCB design information from the data processing module, compare them with the component identification results and layout information results, and compare them according to the set verification rules. If the verification passes, the correct information is output; if it fails, specific error information is output to display to the user to prompt for inspection and modification.

4. The intelligent station table generation system for SMT patches according to claim 1, characterized in that: The station layout module includes a layout density calculation unit, a patch efficiency calculation unit, and a comprehensive optimization target unit; The layout density calculation unit calculates the area occupied by each component on the PCB board according to the package size and spacing of the component, according to the formula: A i =l i *w i +ΔA i ; Among them A i represents the area of ​​the ith element, l i represents the length of the i-th element, w i represents the width of the i-th element, ΔA i It indicates that the extra spacing area reserved for the i-th component in the PCB layout considering the safety distance between components, heat dissipation requirements and layout optimization; Calculate the ratio of the area occupied by the laid-out components to the total area on the PCB according to the formula: Where D represents the component layout density, n represents the total number of components, and A PCB Indicates the total area of ​​the PCB board, A r Indicates the area on the PCB that is reserved and cannot be used for component layout; The patch efficiency calculation unit calculates the moving path length of the patch machine during the patch process by calculating the sum of the distances from each component to its previous component or starting point, according to the formula: Where L p represents the length of the patch path, (x0, y0) represents the starting coordinates of the patch machine, (x1, y1) represents the coordinates of the first component, (x i ,y i ) represents the coordinates of the ith element, (x i+1 ,y i+1 ) represents the coordinates of the i+1th element; The patch efficiency is calculated by combining the patch path length, the moving speed of the patch machine, and the patch time, according to the formula: Where E represents the placement efficiency, v represents the average moving speed of the placement machine, T i represents the patch time of the i-th component; The comprehensive optimization target unit comprehensively considers the layout density and patch efficiency, and defines a comprehensive optimization target function F: Where w1 and w2 are the weight coefficients of component layout density and patch efficiency, respectively, which are used to balance the importance of layout density and patch efficiency in the optimization process and set a comprehensive optimization objective function threshold K.

5. The intelligent station table generation system for SMT patches according to claim 1, characterized in that: The station table optimization output module is used to provide a variety of different station table templates, from which the user selects a template. The system reads the information of the selected station table from the database, and evaluates the performance of the current station table according to the value of the comprehensive optimization objective function F. If the F value is less than the set threshold K, the optimization is stopped and the current station table is output. If it is greater than the threshold K, a group of new station tables are generated as candidates according to the particle swarm algorithm, and each candidate station table is evaluated and compared. The station table with the smallest F value is selected as the final station table result and output.

6. A method for generating an intelligent station table for SMT patches, characterized in that: The method comprises the following steps: Step S100: Import BOM files and PCB board design information and perform data analysis, verification and sorting on them, and record and process engineering change notifications; Step S200: automatically identifying and analyzing the component layout and component type on the PCB board, and performing a comparative analysis with the analysis results of the data processing module for comprehensive verification; Step S300: optimizing the component layout by comprehensively considering the layout density of the components on the PCB board and the placement efficiency of the placement machine; Step S400: receiving data from the data processing module and the image recognition module, adjusting and optimizing the station table according to the layout result of the layout density and efficiency optimization module, and outputting the final station table result; The step S100 includes the following steps: Step S101 is used to import the BOM file and PCB design information and automatically parse them, while backing up the original BOM file and PCB board design information; Step S102 is used to automatically check the errors and omissions in the BOM file, including the completeness, accuracy, consistency and field missing of the data, and perform multi-faceted verification of the PCB design information. If an error is found, the user is shown a specific error message and prompted to make corrections; after the user corrects the error, the relevant information is re-verified until no problem is found, and then the next step is performed; Step S103 is used to record the change notification of the BOM file or PCB design information and prompt to make corresponding changes to the BOM file or PCB design information. The user can choose whether to change the information according to the prompt. Step S104 merges, splits, and organizes the BOM file or PCB design information according to user requirements, and stores the organized material information in a database.

7. The method for generating an intelligent station table for SMT patches according to claim 6, characterized in that: The step S200 includes the following steps: Step S201 uses a convolutional neural network and a residual network to automatically extract various components on the PCB board and corresponding attribute information through multi-layer convolution and pooling operations; Step S202 uses the YOLO target detection algorithm to locate the position of the component in the image and uses image segmentation technology to segment the components in the image and assign corresponding labels. At the same time, the context reasoning technology is used to analyze the relative position and relationship between the components and the layout of the components on the PCB board to infer the information of the components that are blocked or difficult to identify; Step S203 is used to receive the parsed BOM file and PCB design information from the data processing module, compare them with the component identification results and layout information results, and compare them according to the set verification rules. If the verification passes, the correct information is output. If it fails, a specific error message is output to display to the user to prompt for inspection and modification.

8. The method for generating an intelligent station table for SMT patches according to claim 6, characterized in that: The step S300 includes the following steps: Step S301 calculates the area occupied by each component on the PCB board by the package size and spacing of the component, according to the formula: A i =l i *w i +ΔA i ; Among them A i represents the area of ​​the ith element, l i represents the length of the i-th element, w i represents the width of the i-th element, ΔA i It indicates that the extra spacing area reserved for the i-th component in the PCB layout considering the safety distance between components, heat dissipation requirements and layout optimization; Step S302 calculates the ratio of the area occupied by the laid-out components to the total area of ​​the PCB according to the formula: Where D represents the component layout density, n represents the total number of components, and A PCB Indicates the total area of ​​the PCB board, A r Indicates the area on the PCB that is reserved and cannot be used for component layout; Step S303 calculates the moving path length of the placement machine during the placement process by calculating the sum of the distances from each component to its previous component or starting point, according to the formula: Where L p represents the length of the patch path, (x0, y0) represents the starting coordinates of the patch machine, (x1, y1) represents the coordinates of the first component, (x i ,y i ) represents the coordinates of the ith element, (x i+1 ,y i+1 ) represents the coordinates of the i+1th element; Step S304 calculates the patch efficiency by combining the patch path length, the moving speed of the patch machine, and the patch time, according to the formula: Where E represents the placement efficiency, v represents the average moving speed of the placement machine, T i represents the patch time of the i-th component; Step S305 comprehensively considers the layout density and patch efficiency and defines a comprehensive optimization objective function F: Where w1 and w2 are the weight coefficients of component layout density and patch efficiency, respectively, which are used to balance the importance of layout density and patch efficiency in the optimization process, set a comprehensive optimization objective function threshold K, and evaluate the performance of the station table.

9. The method for generating an intelligent station table for SMT patches according to claim 6, characterized in that: In step S500, the system provides a variety of different station table templates, and the user selects a template from them. The system reads the information of the selected station table from the database, and evaluates the performance of the current station table according to the value of the comprehensive optimization objective function F. If the F value is less than the set threshold K, the optimization is stopped and the current station table is output. If it is greater than the threshold K, a group of new station tables are generated as candidates according to the particle swarm algorithm, and each candidate station table is evaluated and compared, and the station table with the smallest F value is selected as the final station table result and output.

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