Method for calculating defects in key area

Abstract

The invention provides a method for calculating defects in a key area, which comprises the following steps: the whole die scanning of a wafer is completed, and a corresponding defect report file is output, and the defect report file comprises each defect coordinate; determining the position of the (0, 0) point of the die in the die grid, and determining the layout coordinates (x, y) of the corresponding origin position; forming a first area coordinate of each design area of the layout; the layout coordinates (x, y) are returned to zero to obtain second area coordinates of all the design areas, and defect codes in all the design areas are defined; and comparing and calculating each defect coordinate in the output defect report file with the second region coordinate, and dividing defect types according to the design region. The method is high in efficiency, does not need to occupy machine hours for a long time, and is more accurate in calculation compared with manual area framing.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a method for calculating defects in a critical area. Background Art

[0002] The size of integrated circuit components manufactured by the semiconductor industry is getting smaller and smaller, and their yield will be more affected by INLINE defects; in particular, some key areas are particularly sensitive to defects. Therefore, the correlation analysis between defects and yield in key areas and the control of defects in key areas are gradually becoming urgent.

[0003] Currently, the defect scanning machine can load the wafer into the device and manually search for certain key areas on the wafer and manually frame them in the key area marking function interface, and then scan and generate a defect list for the key areas.

[0004] There are the following problems:

[0005] 1. Before wafer scanning, engineers need to create files based on the wafers at the current scanning site, spend a long time looking for key areas in a certain die on the wafer, and frame them one by one. If the die is more complex, it often takes n hours, which is inefficient and takes up machine time.

[0006] 2. The key area of ​​the machine drawing has size restrictions, and areas that are too small cannot be drawn.

[0007] 3. The boundaries of the key areas drawn by the machine will not be included in the drawn key areas.

[0008] In order to solve the above problems, a new method for calculating defects in critical areas needs to be proposed. Summary of the invention

[0009] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for calculating defects in key areas, so as to solve the problem of manually marking defects in key areas in the prior art.

[0010] To achieve the above objectives and other related objectives, the present invention provides a method for calculating critical area defects, comprising:

[0011] Step 1: After the entire die of the wafer is scanned, the corresponding defect report file is output, and the defect report file includes the coordinates of each defect;

[0012] Step 2: Confirm the position of the (0,0) point of the die in the die grid, and confirm the layout coordinates (x, y) of the corresponding origin position;

[0013] Step 3, forming the first area coordinates of each design area of ​​the layout;

[0014] Step 4: reset the layout coordinates (x, y) to zero, obtain the second region coordinates of each design region, and define the defect code in each design region;

[0015] Step 5: Compare and calculate the coordinates of each defect in the output defect report file with the coordinates of the second area, and classify the defect types according to the design area.

[0016] Preferably, in step one, a defect scanning machine is used to scan the entire die of the wafer.

[0017] Preferably, the defect report file in step 1 is a klarf file.

[0018] Preferably, the method further comprises step six, performing defect analysis using the defect code.

[0019] Preferably, in step six, the defect code is used to perform defect analysis through a defect management system.

[0020] As described above, the method for calculating critical area defects of the present invention has the following beneficial effects:

[0021] The present invention has high efficiency, does not need to occupy machine time for a long time, and the calculation is more accurate than manually outlining the area. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Shown is a schematic diagram of a method for calculating critical area defects of the present invention;

[0023] Figure 2 Shown is a schematic diagram of the position of the (0,0) point of the die in the die grid of the present invention;

[0024] Figure 3 A schematic diagram showing the layout coordinates (x, y) of the corresponding origin position of the present invention;

[0025] Figure 4 Shown is a schematic diagram of area a and area b in the die layout of the present invention. DETAILED DESCRIPTION

[0026] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0027] See also Figure 1 The present invention provides a method for calculating critical area defects, comprising:

[0028] Step 1: After the entire die of the wafer is scanned, the corresponding defect report file is output, and the defect report file includes the coordinates of each defect;

[0029] Step 2: Confirm the position of the die (0,0) point in the die grid in the machine menu (such as Figure 2 ), confirm the layout coordinates (x, y) of the corresponding origin position (as shown in Figure 3 shown);

[0030] Step 3: Form the first area coordinates of each design area of ​​the layout; refer to Figure 4 , for example: a area (ax1,ay1)(ax2,ay2)(ax3,ay3)(ax4,ay4); b area (bx1,by1)(bx2,by2)(bx3,by3)(bx4,by4)...

[0031] Step 4: Reset the layout coordinates (x, y) to zero, obtain the second area coordinates of each design area, and define the defect code in each design area; for example, area a (ax1-x, ay1-y) (ax2-x, ay2-y) (ax3-x, ay3-y) (ax4-x, ay4-y); area b..., and define the defect code 1, 2, 3... in each area.

[0032] Step 5: Compare and calculate the coordinates of each defect in the output defect report file with the coordinates of the second area, and classify the defect types according to the design area.

[0033] For example, if defect 1 is in area a, a certain defect type or another defect type of the defect is written as code 1.

[0034] In some embodiments, the method further includes step six, performing defect analysis using defect coding.

[0035] In some embodiments, in step six, defect analysis is performed using a defect management system using defect codes.

[0036] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0037] In summary, the present invention is highly efficient, does not require long machine hours, and is more accurate than manually delimiting the area. Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial utilization value.

[0038] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for calculating critical area defects, characterized in that: At least: Step 1: After the entire die of the wafer is scanned, the corresponding defect report file is output. The defect report file includes the coordinates of each defect, and the defect coordinates are based on the lower left of the die grid as point (0,0); Step 2: Confirm the position of the (0,0) point of the die in the die grid, and confirm the layout coordinates (x, y) of the corresponding origin position; Step 3, forming the first area coordinates of each design area of ​​the layout; Step 4: reset the layout coordinates (x, y) to zero, obtain the second region coordinates of each design region, and define the defect code in each design region; Step 5: Compare and calculate the coordinates of each defect in the output defect report file with the coordinates of the second area, and classify the defect types according to the design area.

2. The method for calculating critical area defects according to claim 1, characterized in that: In step one, a defect scanning machine is used to scan the entire die of the entire wafer.

3. The method for calculating critical area defects according to claim 1, characterized in that: The defect report file in step 1 is a klarf file.

4. The method for calculating critical area defects according to claim 1, characterized in that: The method also includes step six, performing defect analysis using the defect code.

5. The method for calculating critical area defects according to claim 5, characterized in that: In step six, the defect code is used to perform defect analysis through a defect management system.

Images