HBM memory system, electronic equipment and high-bandwidth interface design method

Abstract

The invention belongs to the field of integrated circuit design, and particularly relates to an HBM memory system, electronic equipment and a high-bandwidth interface design method. The HBM memory system comprises an HBM controller and an HBM memory, the HBM memory comprises a DRAM memory, an interface circuit and a VREFDQ voltage regulation circuit, and the interface circuit comprises a comparison unit and an amplification unit. The interface circuit receives a first DQ signal; the HBM controller controls a VREFDQ voltage adjusting circuit to adjust a current VREFDQ voltage value to a target VREFDQ voltage value based on the first DQ signal; the interface circuit receives a second DQ signal after the VREFDQ voltage value is adjusted to the target VREFDQ voltage value; the comparison unit obtains the level of the second DQ signal according to the second DQ signal and the target VREFDQ voltage value; the amplifying unit amplifies the level of the second DQ signal; and the interface circuit outputs the amplified second DQ signal to the DRAM. According to the embodiment of the invention, the VREFDQ voltage value is trained to ensure that the VREFDQ voltage value is the central point of the DQ signal, so that the data transmission accuracy of the data interface is improved.

Description

Technical Field

[0001] The present application belongs to the field of integrated circuit design, and in particular, relates to an HBM memory system, an electronic device, and a high-bandwidth interface design method. Background Art

[0002] Nowadays, many applications require large bandwidth, such as high-performance computing (HPC), Ethernet, and graphics processing units (GPUs). In addition, due to the accumulation of big data, the innovation of theoretical algorithms, the improvement of computing power, and the evolution of network facilities, the artificial intelligence industry, which has accumulated for more than half a century, has once again ushered in revolutionary progress, and the research and application of artificial intelligence has entered a new stage of development. In artificial intelligence computing, the number of process parameters processed is very large, and the memory needs to have large storage capacity, high bandwidth, and low latency access capabilities. 3D stacked HBM memory can stack multiple layers of memory through silicon via (TSV) technology to double the capacity and bandwidth.

[0003] However, according to the JEDEC standard, HBM memory does not have a VERFDQ power port. When the input signal is affected by external noise or swing fluctuations, the port rate will be reduced, reducing the bandwidth of chip data transmission. The current solution is to use an on-chip VREFDQ power solution, design a VERFDQ power supply inside the HBM memory chip, use VERFDQ at the DQ data signal receiving port to compare the DQ signal, and amplify the signal for output. However, as far as the current on-chip VREFDQ power solution is concerned, its anti-interference ability is weak. On the one hand, when noise appears in the DQ pin input signal and the noise amplitude is large, it may cause the original input high level to be recognized as a low level, or the input low level to be recognized as a high level, causing data transmission errors; on the other hand, when data is transmitted from the HBM controller to the DRAM memory chip, a non-full-swing analog signal is used, and the position of the signal center point may change, while the internal VREFDQ power supply is a fixed value, which may also cause the original input high level to be recognized as a low level, or the input low level to be recognized as a high level, causing data transmission errors.

[0004] Therefore, the existing DQ data signal receiving port has the problem of being easily affected by external noise and signal swing fluctuation, resulting in reduced accuracy of data transmission. Summary of the invention

[0005] The purpose of the present application is to provide an HBM memory system, an electronic device and a high-bandwidth interface design method, aiming to solve the problem that the existing DQ data signal receiving port is easily affected by external noise and signal swing fluctuations, resulting in reduced accuracy of data transmission.

[0006] In order to solve the above technical problems, the first aspect of the embodiment of the present application provides an HBM memory system, including an HBM controller and an HBM memory, wherein the HBM memory includes: a DRAM memory, an interface circuit and a VREFDQ voltage adjustment circuit, wherein the interface circuit includes a comparison unit, an amplification unit, and the HBM memory;

[0007] The interface circuit is configured to receive a first DQ signal;

[0008] The HBM controller is configured to control the VREFDQ voltage adjustment circuit to adjust the current VREFDQ voltage value to a target VREFDQ voltage value based on the first DQ signal;

[0009] The interface circuit is further configured to receive a second DQ signal after the VREFDQ voltage value is adjusted to the target VREFDQ voltage value;

[0010] The comparison unit is configured to obtain a level of the second DQ signal according to the second DQ signal and the target VREFDQ voltage value;

[0011] The amplifying unit is configured to amplify the level of the second DQ signal;

[0012] The interface circuit is further configured to output the amplified second DQ signal to the DRAM memory.

[0013] In one embodiment, the HBM controller is further configured to: obtain a range interval of the VREFDQ voltage value to be selected; obtain an intermediate value of the VREFDQ voltage value to be selected based on the range interval of the VREFDQ voltage value to be selected; and use the intermediate value of the VREFDQ voltage value to be selected as the target VREFDQ voltage value.

[0014] In one embodiment, the VREFDQ voltage adjustment circuit includes: a resistor string, a selector, a decoder and an output driving unit;

[0015] The input end of the decoder is electrically connected to the output end of the HBM controller, and the output end of the decoder is electrically connected to the first input end of the selector;

[0016] The second input terminal of the selector is electrically connected to different numbers of access resistors in the resistor string, and the output terminal of the selector is electrically connected to the input terminal of the output driving unit;

[0017] The output terminal of the output driving unit is electrically connected to the input terminal of the comparison unit.

[0018] In one embodiment, the HBM controller is further configured to obtain an allowable range of the VREFDQ voltage value;

[0019] The selector is configured to select different numbers of access resistors to adjust the VREFDQ voltage value within the allowable range;

[0020] The HBM controller is also configured to: after each adjustment of the VREFDQ voltage value, perform write and read operations on the HBM memory according to the first DQ signal, and determine whether the write and read operations are correct; record the VREFDQ voltage value corresponding to the correct write and read operations as a to-be-selected VREFDQ voltage value; and determine a range interval of the to-be-selected VREFDQ voltage value based on all the to-be-selected VREFDQ voltage values.

[0021] In one embodiment, the HBM controller is further configured to: generate a decoder control instruction based on an external controller input code;

[0022] The decoder is configured to decode the external controller input code according to the decoder control instruction to obtain a first resistance selection signal;

[0023] The selector is configured to select a corresponding number of access resistors according to the first resistor selection signal.

[0024] In one embodiment, the HBM controller is further configured to: first set the current VREFDQ voltage value to the minimum value within the allowable range, and then increase the current VREFDQ voltage value in steps until the current VREFDQ voltage value reaches the maximum value within the allowable range.

[0025] In one embodiment, the output driving unit is configured to drive the adjusted VREFDQ voltage value to output to the comparing unit;

[0026] The comparison unit is configured to obtain a level of the first DQ signal according to the first DQ signal and the VREFDQ voltage value;

[0027] The amplifying unit is configured to amplify the level of the first DQ signal, and output the first DQ signal after the level amplification through the interface circuit and write it into the DRAM memory;

[0028] The HBM controller is also configured to: read out the first DQ signal stored in the DRAM memory, and determine whether the level states of the first DQ signal in the write and read operations are consistent, so as to determine whether the write and read operations are correct; wherein, if the level states of the first DQ signal in the write and read operations are consistent, it is determined that the write and read operations are correct.

[0029] In one embodiment, the comparison unit set in the interface circuit is a hysteresis comparator, which is configured to: obtain a current voltage threshold according to the VREFDQ voltage value and the preset voltage threshold; wherein the current voltage threshold includes: a current high level voltage threshold and a current low level voltage threshold; compare the real-time voltage value of the first DQ signal with the current voltage threshold, and obtain the level state of the first DQ signal according to the comparison result; wherein, if the real-time voltage value is lower than the current low level voltage threshold, the level state of the first DQ signal is determined to be a low level.

[0030] In one embodiment, the hysteresis comparator is further configured to: after the level state of the first DQ signal is judged to be a low level, if the real-time voltage value of the first DQ signal is not higher than the current high-level voltage threshold, continue to determine the level state of the first DQ signal as a low level; after the level state of the first DQ signal is judged to be a high level, if the real-time voltage value of the first DQ signal is not lower than the current low-level voltage threshold, continue to determine the level state of the first DQ signal as a high level.

[0031] In one embodiment, the VREFDQ voltage adjustment circuit further includes a temperature sensor and a temperature comparator;

[0032] The temperature sensor is configured to generate a real-time detection voltage according to the collected internal temperature of the chip, and output the real-time detection voltage to the temperature comparator;

[0033] The temperature comparator is configured to determine the reference temperature voltage interval to which the real-time detection voltage belongs according to a preset reference temperature voltage interval, and to generate an internal temperature control code based on the reference temperature voltage interval and output it to the decoder;

[0034] The decoder is further configured to decode the internal temperature control code to obtain a second resistance selection signal;

[0035] The selector is further configured to adjust the number of the access resistors according to the second resistor selection signal.

[0036] In one embodiment, the comparison unit provided in the interface circuit is a hysteresis comparator;

[0037] The output driving unit is further configured to drive the target VREFDQ voltage value to output to the hysteresis comparator;

[0038] The hysteresis comparator is configured to: obtain a target voltage threshold according to the target VREFDQ voltage value and the preset voltage threshold; wherein the target voltage threshold includes: a target high level voltage threshold and a target low level voltage threshold; compare the real-time voltage value of the second DQ signal with the target voltage threshold, and obtain the level state of the second DQ signal according to the comparison result; wherein, if the real-time voltage value is lower than the target low level voltage threshold, the level state of the second DQ signal is determined to be a low level.

[0039] In one embodiment, the hysteresis comparator is further configured to: after the level state of the second DQ signal is judged to be a low level, if the real-time voltage value of the second DQ signal is not higher than the target high-level voltage threshold, continue to determine the level state of the second DQ signal as a low level; after the level state of the second DQ signal is judged to be a high level, if the real-time voltage value of the second DQ signal is not lower than the target low-level threshold voltage, continue to determine the level state of the second DQ signal as a high level.

[0040] A second aspect of the present application provides an electronic device, comprising the HBM memory system as described in any one of the above.

[0041] A third aspect of the present application provides a high-bandwidth interface design method, which is applied to an HBM memory system, including an HBM controller and an HBM memory, wherein the HBM memory includes: a DRAM memory, an interface circuit and a VREFDQ voltage adjustment circuit, wherein the interface circuit includes a comparison unit and an amplification unit, and the method includes:

[0042] The interface circuit receives a first DQ signal;

[0043] The HBM controller controls the VREFDQ voltage adjustment circuit to adjust the current VREFDQ voltage value to a target VREFDQ voltage value based on the first DQ signal;

[0044] The interface circuit receives a second DQ signal after the VREFDQ voltage value is adjusted to the target VREFDQ voltage value;

[0045] The comparing unit acquires the level of the second DQ signal according to the second DQ signal and the target VREFDQ voltage value;

[0046] The amplifying unit amplifies the level of the second DQ signal;

[0047] The interface circuit outputs the amplified second DQ signal to the DRAM memory.

[0048] Compared with the prior art, the embodiments of the present application have the following beneficial effects: an HBM memory system, an electronic device and a high-bandwidth interface design method are provided. By designing a training process for the VREFDQ voltage value, the VREFDQ voltage value is trained before the HBM memory system and the controller start transmitting data to ensure that the voltage value of VREFDQ is the center point of the DQ signal, thereby improving the accuracy of data transmission when the DQ data signal receiving port is affected by external noise and signal swing fluctuations. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the related technologies or the embodiments of the present application, the drawings required for use in the description of the related technologies or the embodiments of the present application will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, not all embodiments. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0050] Figure 1 A schematic diagram of the structure of an HBM memory system provided for the first aspect of an embodiment of the present application;

[0051] Figure 2 A schematic diagram of a detailed HBM memory system structure provided for the first aspect of the embodiment of the present application;

[0052] Figure 3 A schematic diagram of another detailed HBM memory system structure provided in the first aspect of the embodiment of the present application;

[0053] Figure 4 A schematic diagram of an electronic device provided in accordance with a second aspect of an embodiment of the present application;

[0054] Figure 5 A flowchart of a high-bandwidth interface design method provided in the third aspect of an embodiment of the present application. DETAILED DESCRIPTION

[0055] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0056] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0057] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0058] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means one or more, unless otherwise clearly and specifically defined.

[0059] Figure 1 A schematic diagram of the structure of an HBM memory system provided by the first aspect of an embodiment of the present application is shown. For the sake of convenience, only the part related to the present embodiment is shown, which is described in detail as follows:

[0060] The HBM memory system in this embodiment includes an HBM memory 10 and an HBM controller 20 , wherein the HBM memory 10 includes: a DRAM memory 101 , an interface circuit 102 , and a VREFDQ voltage adjustment circuit 103 , and the interface circuit 102 includes a comparison unit 1021 and an amplification unit 1022 .

[0061] The interface circuit 102 is configured to receive a first DQ signal.

[0062] The HBM controller 20 is configured to control the VREFDQ voltage adjustment circuit 103 to adjust the current VREFDQ voltage value to a target VREFDQ voltage value based on the first DQ signal.

[0063] The interface circuit 102 is further configured to receive the second DQ signal after the VREFDQ voltage value is adjusted to the target VREFDQ voltage value.

[0064] The comparison unit 1021 is configured to obtain a level of the second DQ signal according to the second DQ signal and the target VREFDQ voltage value.

[0065] The amplifying unit 1022 is configured to amplify the level of the second DQ signal.

[0066] The interface circuit 102 is further configured to output the amplified second DQ signal to the DRAM memory 101 .

[0067] It can be understood that the interface circuit 102 serves as the data transmission path of the DRAM memory 101, performs data input and output, and has a bidirectional characteristic. During the data transmission process, the VREFDQ voltage value is required to determine the level state of the DQ signal input by the DQ pin in the interface circuit. However, when data is transmitted from the HBM controller 20 to the DRAM memory 101, a non-full-swing analog signal is used, and the position of the center point of the signal may change, and the internal VREFDQ power supply is a fixed value, which may also cause the original input high level to be recognized as a low level, or the input low level to be recognized as a high level, causing data transmission errors. Therefore, in order to ensure the accuracy of the written data, the embodiment of the present application uses the HBM controller 20 to control the VREFDQ voltage adjustment circuit 103 to train the VREFDQ voltage value to prevent data transmission errors caused by changes in the position of the signal center point. The specific training process will be described in detail in other steps.

[0068] It can be understood that, in the embodiment of the present application, the first DQ signal actually participates in the training process of the VREFDQ voltage value before data transmission, and the second DQ signal in the embodiment of the present application is the data signal that actually needs to be input after the training process of the VREFDQ voltage value is completed.

[0069] In some embodiments, the HBM controller 20 is further configured to: obtain a range interval of the VREFDQ voltage value to be selected; obtain an intermediate value of the VREFDQ voltage value to be selected based on the range interval of the VREFDQ voltage value to be selected; and use the intermediate value of the VREFDQ voltage value to be selected as the target VREFDQ voltage value.

[0070] It is understandable that when the DQ signal is compared using the VREFDQ voltage value to obtain the level state, the VREFDQ voltage value is usually selected to be exactly in the middle of the input signal. During the training process of the VREFDQ voltage value of the embodiment of the present application, a series of VREFDQ voltage values ​​that can correctly determine the level state of the DQ signal are obtained, and a range interval of the VREFDQ voltage value to be selected is obtained. The middle value is selected from this range interval as the target VREFDQ voltage value. Therefore, when the position of the center point of the signal changes, the embodiment of the present application trains the VREFDQ voltage value to ensure that the VREFDQ voltage value remains at the center point of the signal, thereby preventing data transmission errors caused by changes in the position of the center point of the signal.

[0071] exist Figure 1 Based on the HBM memory system provided, this embodiment also provides a detailed HBM memory system structure diagram, for details, please refer to Figure 2 In some embodiments, the VREFDQ voltage adjustment circuit 103 includes: a resistor string 1031 , a selector 1032 , a decoder 1033 and an output driving unit 1034 .

[0072] The input end of the decoder 1033 is electrically connected to the output end of the HBM controller 20 , and the output end of the decoder 1033 is electrically connected to the first input end of the selector 1032 .

[0073] The second input terminal of the selector 1032 is electrically connected to different numbers of access resistors in the resistor string 1031 , and the output terminal of the selector 1032 is electrically connected to the input terminal of the output driving unit 1034 .

[0074] The output terminal of the output driving unit 1034 is electrically connected to the input terminal of the comparing unit 1021 .

[0075] It can be understood that the HBM controller 20 sends a decoder control instruction to the decoder 1033, wherein the decoder control instruction includes an external controller input code, and the external controller input code is decoded by the decoder 1033 to obtain a resistance selection signal, and the control selector 1032 selects the corresponding number of access resistors in the resistor string 1031 for voltage division to achieve an adjustable output of the VREFDQ voltage value, and then the adjusted VREFDQ voltage value is output through the output driving unit 1034 and driven to the comparison unit 1021 in the interface circuit 102.

[0076] The VREFDQ voltage value is obtained by resistor voltage division, and the matching accuracy of the resistors directly determines the voltage accuracy of the VREFDQ voltage value. Therefore, in some embodiments, all resistors in the resistor string 1031 are connected in series or in parallel using unit resistors of the same size, and the layout is optimized to achieve high-precision requirements. Among them, unit resistors of the same size can ensure that the resistance error of each resistor is the same, and the resistance error of the series or parallel resistors finally obtained is also the same. At the same time, an operational amplifier with high gain, full swing input and output, and large driving capability is used as the output driver, and the layout of the output driver is optimized.

[0077] In some embodiments, the HBM controller 20 is further configured to obtain an allowable range of the VREFDQ voltage value.

[0078] The selector 1032 is configured to select different numbers of access resistors to adjust the VREFDQ voltage value within the allowable range.

[0079] The HBM controller 20 is also configured to: after each adjustment of the VREFDQ voltage value, perform write and read operations on the HBM memory 20 according to the first DQ signal, and determine whether the write and read operations are correct; record the VREFDQ voltage value corresponding to the correct write and read operations as the VREFDQ voltage value to be selected; and determine the range interval of the VREFDQ voltage value to be selected based on all the VREFDQ voltage values ​​to be selected.

[0080] It can be understood that different numbers of access resistors are selected by the selector 1032 to achieve the adjustment of the VREFDQ voltage value, and based on the adjusted different VREFDQ voltage values, the first DQ signal input to the HBM memory 20 is written and read. By judging whether the write and read operations are correct, it is determined whether the VREFDQ voltage value can be recorded as a candidate value, and then the middle value is selected from the range determined by all the candidate values, so that the VREFDQ voltage value can be indirectly determined as the middle value of the currently input DQ signal.

[0081] In some embodiments, the HBM controller is further configured to generate a decoder control instruction based on an external controller input code.

[0082] The decoder is configured to decode the external controller input code according to the decoder control instruction to obtain a first resistance selection signal.

[0083] The selector is configured to select a corresponding number of access resistors according to the first resistor selection signal.

[0084] It can be understood that the external controller input code is a control code for the selector based on the external input of the VREFDQ adjustment circuit, which can usually be generated by the HBM controller. The external code is used to distinguish it from the internal temperature control code in the VREFDQ adjustment circuit in other embodiments. The internal temperature control will be described in detail in other embodiments.

[0085] In some embodiments, the HBM controller is further configured to: first set the current VREFDQ voltage value to a minimum value within the allowable range, and then increase the current VREFDQ voltage value in steps until the current VREFDQ voltage value reaches a maximum value within the allowable range.

[0086] It can be understood that the access resistors in the resistor string are all unit resistors of the same size. In order to test all possible VREFDQ voltage values, the VREFDQ voltage value can be divided by selecting different numbers of access resistors in sequence, thereby realizing a training process from the minimum value of the VREFDQ voltage value to the maximum value.

[0087] In some embodiments, the output driving unit is configured to drive the adjusted VREFDQ voltage value to output to the comparing unit.

[0088] The comparison unit is configured to obtain a level of the first DQ signal according to the first DQ signal and the VREFDQ voltage value.

[0089] The amplifying unit is configured to amplify the level of the first DQ signal, and output the first DQ signal after the level amplification through the interface circuit and write it into the DRAM memory.

[0090] The HBM controller is also configured to: read out the first DQ signal stored in the DRAM memory, and determine whether the level states of the first DQ signal in the write and read operations are consistent, so as to determine whether the write and read operations are correct; wherein, if the level states of the first DQ signal in the write and read operations are consistent, it is determined that the write and read operations are correct.

[0091] It can be understood that after the VREFDQ voltage value is adjusted, it needs to be input into the comparison unit in the interface circuit to compare the level of the DQ signal and confirm the level state of the DQ signal. The level signal obtained after the comparison is then amplified by the amplification unit and input into the DRAM memory for storage. After that, the level state of the saved DQ signal is read out, and the level states of the written and read DQ signals are compared. If they are consistent, the current VREFDQ voltage value can be judged as a value that can confirm the DQ signal, and it can be recorded as a candidate value in the subsequent steps.

[0092] In some embodiments, the comparison unit set in the interface circuit is a hysteresis comparator, which is configured to: obtain a current voltage threshold based on the VREFDQ voltage value and the preset voltage threshold; wherein the current voltage threshold includes: a current high level voltage threshold and a current low level voltage threshold; compare the real-time voltage value of the first DQ signal with the current voltage threshold, and obtain the level state of the first DQ signal based on the comparison result; wherein, if the real-time voltage value is lower than the current low level voltage threshold, the level state of the first DQ signal is determined to be a low level.

[0093] In some embodiments, the hysteresis comparator is further configured to: after the level state of the first DQ signal is judged to be a low level, if the real-time voltage value of the first DQ signal is not higher than the current high-level voltage threshold, continue to determine the level state of the first DQ signal as a low level; after the level state of the first DQ signal is judged to be a high level, if the real-time voltage value of the first DQ signal is not lower than the current low-level voltage threshold, continue to determine the level state of the first DQ signal as a high level.

[0094] It can be understood that the hysteresis comparator is a comparator with a hysteresis characteristic. When the input signal changes, its output will not immediately follow the change of the input signal, but will change after the input signal reaches a certain threshold. This hysteresis characteristic makes it possible to eliminate the noise of the input signal, thereby improving the anti-noise ability of the data interface and increasing the bandwidth of data transmission. The hysteresis comparator needs to set two thresholds, namely the high-level voltage threshold and the low-level voltage threshold. The high-level threshold is when the input signal reaches this value, the comparator output jumps from a low level to a high level, and the low-level threshold is when the input signal is lower than this value, the comparator output jumps from a high level to a low level. There is a certain lag between these two thresholds, that is, hysteresis. When the input signal changes between these two thresholds, the output of the comparator does not immediately change with the input signal, but maintains the current state until the input signal reaches another threshold.

[0095] Furthermore, in this embodiment, we set a preset voltage threshold for the hysteresis comparator, that is, preset a voltage offset, and the current voltage threshold is the value of the current VREFDQ voltage value increased or decreased on the preset offset, that is, the high level voltage threshold (VREFDQ_p) and the low level voltage threshold (VREFDQ_n), and then compare the input signal with the level voltage threshold to obtain the level.

[0096] exist Figure 1Based on the HBM memory system provided, this embodiment also provides another detailed structural diagram of the HBM memory system, for details, see Figure 3 In some embodiments, the VREFDQ voltage adjustment circuit 103 further includes a temperature sensor 1035 and a temperature comparator 1036 .

[0097] The temperature sensor 1035 is configured to generate a real-time detection voltage according to the acquired internal temperature of the chip, and output the real-time detection voltage to the temperature comparator 1036 .

[0098] The temperature comparator 1036 is configured to determine the reference temperature voltage interval to which the real-time detection voltage belongs according to a preset reference temperature voltage interval, and to generate an internal temperature control code based on the reference temperature voltage interval and output it to the decoder 1033 .

[0099] The decoder 1033 is further configured to decode the internal temperature control code to obtain a second resistance selection signal.

[0100] The selector is further configured to adjust the number of the access resistors according to the second resistor selection signal.

[0101] It is understandable that since the chip works in a wide temperature environment and considering that the resistor is a thermosensitive device, a temperature control function is designed inside the chip. The temperature comparator determines the temperature range inside the chip by comparing the voltage output of the temperature sensor and the reference temperature. Among them, the reference temperature interval can be set in advance, and the temperature monitored in real time falls within the preset temperature interval according to the comparison voltage value, and then the internal temperature control code is output corresponding to the preset interval, and sent to the selector after decoding by the decoder, so as to control the selector to adjust the number of connected resistors accordingly to realize the temperature control function and ensure that the VREFDQ voltage value is in the middle of the signal.

[0102] In some embodiments, the comparison unit provided in the interface circuit is a hysteresis comparator.

[0103] The output driving unit is further configured to drive the target VREFDQ voltage value to output to the hysteresis comparator.

[0104] The hysteresis comparator is configured to: obtain a target voltage threshold according to the target VREFDQ voltage value and the preset voltage threshold; wherein the target voltage threshold includes: a target high level voltage threshold and a target low level voltage threshold; compare the real-time voltage value of the second DQ signal with the target voltage threshold, and obtain the level state of the second DQ signal according to the comparison result; wherein, if the real-time voltage value is lower than the target low level voltage threshold, the level state of the second DQ signal is determined to be a low level.

[0105] In some embodiments, the hysteresis comparator is further configured to: after the level state of the second DQ signal is judged to be a low level, if the real-time voltage value of the second DQ signal is not higher than the target high level voltage threshold, continue to determine the level state of the second DQ signal as a low level; after the level state of the second DQ signal is judged to be a high level, if the real-time voltage value of the second DQ signal is not lower than the target low level threshold voltage, continue to determine the level state of the second DQ signal as a high level.

[0106] It can be understood that the second DQ signal is the data signal that actually needs to be transmitted after the training process is completed. In the aforementioned steps, the target VREFDQ voltage value is finally determined through the training process of the VREFDQ voltage value, and then the target VREFDQ voltage value is input into the comparison unit to compare the second DQ signal that actually needs to be transmitted after the training process. The comparison process of the DQ signal has been described in detail in the aforementioned steps and will not be repeated here.

[0107] Figure 4 A schematic diagram of an electronic device provided in the second aspect of an embodiment of the present application is shown, wherein the electronic device A includes the HBM memory system 01 as described in any one of the above items.

[0108] Figure 5 A flow chart of a high-bandwidth interface design method provided in the third aspect of an embodiment of the present application is shown. The high-bandwidth interface design method is applied to an HBM memory system, the HBM memory system includes an HBM controller and an HBM memory, the HBM memory includes: a DRAM memory, an interface circuit and a VREFDQ voltage adjustment circuit, the interface circuit includes a comparison unit and an amplification unit, and the method includes the following steps 501 to 506.

[0109] Step 501: The interface circuit receives a first DQ signal.

[0110] Step 502: The HBM controller controls the VREFDQ voltage adjustment circuit to adjust the current VREFDQ voltage value to a target VREFDQ voltage value based on the first DQ signal.

[0111] Step 503: After the VREFDQ voltage value is adjusted to the target VREFDQ voltage value, the interface circuit receives the second DQ signal.

[0112] Step 504: The comparing unit obtains the level of the second DQ signal according to the second DQ signal and the target VREFDQ voltage value.

[0113] Step 505: The amplifying unit amplifies the level of the second DQ signal.

[0114] Step 506: The interface circuit outputs the amplified second DQ signal to the DRAM memory.

[0115] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0116] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0117] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A HBM memory system, comprising an HBM controller and an HBM memory, wherein the HBM memory comprises: DRAM memory, interface circuit and VREFDQ voltage adjustment circuit, the interface circuit includes a comparison unit and an amplification unit; The interface circuit is configured to receive a first DQ signal; The HBM controller is configured to control the VREFDQ voltage adjustment circuit to adjust the current VREFDQ voltage value to a target VREFDQ voltage value based on the first DQ signal; The interface circuit is further configured to receive a second DQ signal after the VREFDQ voltage value is adjusted to the target VREFDQ voltage value; The comparison unit is configured to obtain a level of the second DQ signal according to the second DQ signal and the target VREFDQ voltage value; The amplifying unit is configured to amplify the level of the second DQ signal; The interface circuit is further configured to output the amplified second DQ signal to the DRAM memory.

2. The HBM memory system according to claim 1, wherein: The HBM controller is further configured to: obtain a range interval of the VREFDQ voltage value to be selected; and obtain an intermediate value of the VREFDQ voltage value to be selected according to the range interval of the VREFDQ voltage value to be selected; An intermediate value of the candidate VREFDQ voltage values ​​is used as the target VREFDQ voltage value.

3. The HBM memory system according to claim 2, wherein: The VREFDQ voltage adjustment circuit includes: a resistor string, a selector, a decoder and an output driving unit; The input end of the decoder is electrically connected to the output end of the HBM controller, and the output end of the decoder is electrically connected to the first input end of the selector; The second input terminal of the selector is electrically connected to different numbers of access resistors in the resistor string, and the output terminal of the selector is electrically connected to the input terminal of the output driving unit; The output terminal of the output driving unit is electrically connected to the input terminal of the comparison unit.

4. The HBM memory system according to claim 3, characterized in that: The HBM controller is further configured to obtain an allowable range of the VREFDQ voltage value; The selector is configured to select different numbers of access resistors to adjust the VREFDQ voltage value within the allowable range; The HBM controller is also configured to: after each adjustment of the VREFDQ voltage value, perform write and read operations on the HBM memory according to the first DQ signal, and determine whether the write and read operations are correct; record the VREFDQ voltage value corresponding to the correct write and read operations as a to-be-selected VREFDQ voltage value; and determine a range interval of the to-be-selected VREFDQ voltage value based on all the to-be-selected VREFDQ voltage values.

5. The HBM memory system according to claim 4, characterized in that: The HBM controller is further configured to: generate a decoder control instruction based on an external controller input code; The decoder is configured to decode the external controller input code according to the decoder control instruction to obtain a first resistance selection signal; The selector is configured to select a corresponding number of access resistors according to the first resistor selection signal.

6. The HBM memory system according to claim 4, characterized in that: The HBM controller is further configured to: first set the current VREFDQ voltage value to a minimum value within the allowable range, and then increase the current VREFDQ voltage value in steps until the current VREFDQ voltage value reaches a maximum value within the allowable range.

7. The HBM memory system according to claim 4, wherein: The output driving unit is configured to drive and output the adjusted VREFDQ voltage value to the comparing unit; The comparison unit is configured to obtain a level of the first DQ signal according to the first DQ signal and the VREFDQ voltage value; The amplifying unit is configured to amplify the level of the first DQ signal, and output the first DQ signal after the level amplification through the interface circuit and write it into the DRAM memory; The HBM controller is also configured to: read out the first DQ signal stored in the DRAM memory, and determine whether the level states of the first DQ signal in the write and read operations are consistent, so as to determine whether the write and read operations are correct; wherein, if the level states of the first DQ signal in the write and read operations are consistent, it is determined that the write and read operations are correct.

8. The HBM memory system according to claim 7, wherein: The comparison unit set in the interface circuit is a hysteresis comparator, which is configured to: obtain a current voltage threshold according to the VREFDQ voltage value and the preset voltage threshold; wherein the current voltage threshold includes: a current high-level voltage threshold and a current low-level voltage threshold; compare the real-time voltage value of the first DQ signal with the current voltage threshold, and obtain the level state of the first DQ signal according to the comparison result; wherein, if the real-time voltage value is lower than the current low-level voltage threshold, the level state of the first DQ signal is determined to be a low level.

9. The HBM memory system according to claim 8, wherein: The hysteresis comparator is further configured to: after the level state of the first DQ signal is judged to be a low level, if the real-time voltage value of the first DQ signal is not higher than the current high-level voltage threshold, continue to determine the level state of the first DQ signal as a low level; after the level state of the first DQ signal is judged to be a high level, if the real-time voltage value of the first DQ signal is not lower than the current low-level voltage threshold, continue to determine the level state of the first DQ signal as a high level.

10. The HBM memory system according to claim 7, wherein: The VREFDQ voltage adjustment circuit also includes a temperature sensor and a temperature comparator; The temperature sensor is configured to generate a real-time detection voltage according to the collected internal temperature of the chip, and output the real-time detection voltage to the temperature comparator; The temperature comparator is configured to determine the reference temperature voltage interval to which the real-time detection voltage belongs according to a preset reference temperature voltage interval, and to generate an internal temperature control code based on the reference temperature voltage interval and output it to the decoder; The decoder is further configured to decode the internal temperature control code to obtain a second resistance selection signal; The selector is further configured to adjust the number of the access resistors according to the second resistor selection signal.

11. The HBM memory system according to claim 7, wherein: The comparison unit provided in the interface circuit is a hysteresis comparator; The output driving unit is further configured to drive the target VREFDQ voltage value to output to the hysteresis comparator; The hysteresis comparator is configured to: obtain a target voltage threshold according to the target VREFDQ voltage value and the preset voltage threshold; wherein the target voltage threshold includes: a target high level voltage threshold and a target low level voltage threshold; compare the real-time voltage value of the second DQ signal with the target voltage threshold, and obtain the level state of the second DQ signal according to the comparison result; wherein, if the real-time voltage value is lower than the target low level voltage threshold, the level state of the second DQ signal is determined to be a low level.

12. The HBM memory system according to claim 11, wherein: The hysteresis comparator is further configured to: after the level state of the second DQ signal is judged to be a low level, if the real-time voltage value of the second DQ signal is not higher than the target high-level voltage threshold, continue to determine the level state of the second DQ signal as a low level; after the level state of the second DQ signal is judged to be a high level, if the real-time voltage value of the second DQ signal is not lower than the target low-level threshold voltage, continue to determine the level state of the second DQ signal as a high level.

13. An electronic device, characterized in that: The HBM memory system comprises the HBM memory system as claimed in any one of claims 1 to 12.

14. A high bandwidth interface design method, characterized in that: The method is applied to an HBM memory system, including an HBM controller and an HBM memory, wherein the HBM memory includes a DRAM memory, an interface circuit and a VREFDQ voltage adjustment circuit, wherein the interface circuit includes a comparison unit and an amplification unit, and wherein the method includes: The interface circuit receives a first DQ signal; The HBM controller controls the VREFDQ voltage adjustment circuit to adjust the current VREFDQ voltage value to a target VREFDQ voltage value based on the first DQ signal; The interface circuit receives a second DQ signal after the VREFDQ voltage value is adjusted to the target VREFDQ voltage value; The comparing unit acquires the level of the second DQ signal according to the second DQ signal and the target VREFDQ voltage value; The amplifying unit amplifies the level of the second DQ signal; The interface circuit outputs the amplified second DQ signal to the DRAM memory.

Images