Control device of simulation, storage and calculation integrated array based on asynchronous normal form

Abstract

The invention discloses an asynchronous normal form-based simulation, storage and calculation integrated array control device, which comprises an asynchronous loopback handshake module for generating an asynchronous clock according to an operation result of a simulation, storage and calculation integrated array, a pre-stage circuit instruction and a state signal of a finite-state machine control module, handshake communication between the asynchronous loopback handshake module and the digital-to-analog converter is controlled through the asynchronous clock; and the finite-state machine control module is used for generating a gating signal according to the number of handshake communication times and sending the gating signal and an asynchronous clock to the gating module, and the gating module controls the analog storage and calculation integrated array through the gating signal and the asynchronous clock. According to the asynchronous normal form-based control device for the analog storage and calculation integrated array, the accurate transmission of data in a system unit is ensured, the data processing intensity and operation efficiency are improved, the circuit design and time delay are optimized, the charge loss is reduced, and the energy efficiency ratio of the whole architecture is improved.

Description

Technical Field

[0001] The present application belongs to the field of microelectronics technology, and in particular, relates to a control device for an analog storage-computation integrated array based on an asynchronous paradigm. Background Art

[0002] As an emerging computing architecture in the field of AI chips, the computing-in-memory (CIM) technology represents one of the most cutting-edge directions in computer science and AI neural networks. The computing-in-memory AI chip architecture can be divided into a digital computing-in-memory architecture and an analog computing-in-memory architecture. The digital computing-in-memory architecture inherits the flexibility and reliability of traditional digital circuits, but when performing complex floating-point operations in AI models, a large number of multipliers and adders are required, resulting in its power consumption and area being inferior to the analog computing-in-memory architecture.

[0003] In the analog storage and computing unit, the control circuit plays a vital role. The control circuit uses a finite state machine (FSM) to send selection signals, start signals, etc. to control the analog storage and computing array to perform convolution calculations to ensure the correct output results. According to different types of analog storage and computing arrays and the accompanying control signal requirements, designers will use Verilog and other codes to generate counter and decoder schematics through the compiler, and call asynchronous logic modules to achieve the power consumption and delay indicators of the asynchronous control circuit.

[0004] The existing analog storage and computing architecture integrated unit uses a control circuit to determine the execution order of computing tasks, and is responsible for efficiently allocating data between the various components of the system. In the existing mainstream design, synchronous clock communication is used between the components in the architecture, and the pipeline operation is uniformly controlled by an external clock tree. However, since the time required for each component to complete the task is different, the unified synchronous clock signal will be formulated based on the component with the worst speed, thereby increasing the overall calculation time of the unit. The currently designed asynchronous logic finite state machine control circuit has a relatively complex program description for generating asynchronous logic circuits, and the asynchronous logic finite state machine control circuit generated by ordinary code will cause additional delay overhead. Summary of the invention

[0005] In order to solve the deficiencies in the prior art, the present application proposes a control device for simulating a storage-computing integrated array based on an asynchronous paradigm, which is described in detail as follows:

[0006] A control device for a storage-computation-in-one array based on an asynchronous paradigm, comprising:

[0007] The asynchronous loop handshake module is used to generate an asynchronous clock according to the operation results of the analog storage and computing integrated array, the instructions of the previous circuit and the state signal of the finite state machine control module, and control the asynchronous loop handshake module to communicate with the digital-to-analog converter through the asynchronous clock;

[0008] The finite state machine control module is used to generate a selection signal according to the number of handshake communications, and send the selection signal and asynchronous clock to the selection module. The selection module controls the analog storage and computing integrated array through the selection signal and asynchronous clock.

[0009] Optionally, the asynchronous loopback handshake module includes: an internal asynchronous loopback module and an external asynchronous handshake module;

[0010] The internal asynchronous loopback module is implemented by a circuit including a binary input and a memory gate, takes the clock of the digital-to-analog converter, the state signal of the finite state machine control module and the asynchronous zeroing signal as input, and takes the asynchronous clock as output, so as to realize handshake communication with the digital-to-analog converter;

[0011] The external asynchronous handshake module is implemented using a circuit with a start-stop structure, and is used to communicate with the front-stage circuit of the control device of the analog storage and computing integrated array to control the internal asynchronous loop module. It takes the operation completion signal of the finite state machine control module, the starting voltage signal of the analog storage and computing integrated array, and the internal asynchronous loop module start output event signal as input, and takes the internal asynchronous loop module handshake count signal and the internal asynchronous loop module stop output event signal as output.

[0012] Optionally, there is a delay during the period when the handshake count signal of the internal asynchronous loop module is set to 1 and the state signal of the finite state machine control module is set to 1, and the delay time period is used to start the voltage source of the analog storage and computing integrated array.

[0013] Optionally, the finite state machine control module includes: a counter and a decoder;

[0014] The counter uses an asynchronous clock counter circuit to implement staggered counting, and is used to record the number of handshakes between the internal asynchronous loopback module and the digital-to-analog converter;

[0015] The decoder is used to generate a selection signal according to the number of handshakes between the internal asynchronous loopback module and the digital-to-analog converter when the asynchronous clock of the handshake rises, and the signal lasts until the asynchronous clock ends.

[0016] Optionally, the finite state machine control module also includes: a zeroing signal generating circuit, used to clear the residual charge in the analog storage and computing integrated array, with a low-level type asynchronous clock and a low-level type zeroing signal as input, and a reset signal and a reset selection signal as output, wherein the reset signal is used to clear the data stored in the decoder, and the reset selection signal is used to control the analog storage and computing integrated array to discharge.

[0017] Optionally, the internal asynchronous loop module uses a first inverter, a second inverter, a first AND gate, a second AND gate, and a binary input memory gate circuit to form a loop structure;

[0018] Using the clock of the digital-to-analog converter as the input of the first inverter, using the output of the first inverter as the first input of the first AND gate, using the asynchronous zeroing signal as the second input of the first AND gate, and using the output of the first AND gate as the first input of the binary input memory gate circuit;

[0019] Using the asynchronous clock as the input of the second inverter, using the output of the second inverter as the first input of the second AND gate, using the state signal of the finite state machine control module as the second input of the second AND gate, and using the output of the second AND gate as the second input of the binary input memory gate circuit;

[0020] The output of the binary input memory gate circuit is used as the asynchronous clock.

[0021] Optionally, the zeroing signal generating circuit comprises: a D flip-flop, a delay circuit, a NOR gate, a third inverter, a fourth inverter and a fifth inverter;

[0022] The data input terminal of the D flip-flop is connected to a high-level signal, the clock input terminal of the D flip-flop is connected to one end of the delay circuit, the other end of the delay circuit is also connected to the reset input terminal of the D flip-flop, the output terminal of the D flip-flop is respectively connected to the input terminal of the third inverter and the second input terminal of the NOR gate, the output terminal of the third inverter is connected to the input terminal of the fifth inverter, the output terminal of the fifth inverter outputs a reset signal, the first input terminal of the NOR gate is connected to a low-level type zeroing signal, the output terminal of the NOR gate is connected to the input terminal of the fourth inverter, and the output terminal of the fourth inverter outputs a reset selection signal.

[0023] The beneficial effects brought about by the technical solutions provided by some embodiments of the present application include at least:

[0024] 1. The design of the asynchronous handshake module in this application can achieve low power consumption standby in idle state while ensuring the computing speed;

[0025] 2. The finite state machine control module in this application adopts the staggered counting method to avoid the double delay of handshake first and then counting, and the pulse coding method adopted has low bandwidth requirements. It only needs to count 6 pulses to convert from 8421 code to pulse coding. The shift register is only 2 more D flip-flops than the asynchronous counter, and the circuit area overhead is negligible. This design avoids the accumulation of delays of the D flip-flops themselves and reduces the bit error rate, so that the total delay of the control circuit is reduced and the reliability is improved;

[0026] 3. The decoder and zeroing signal generating circuit in the present application adopt static logic circuits, which reduces delay and power consumption overhead, and realizes the low power consumption and miniaturization advantages of asynchronous clock communication.

[0027] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or understood by practicing the present application. The purpose and other advantages of the present application are realized and obtained by the structures specifically pointed out in the description, claims and drawings.

[0028] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the following is a detailed description of the preferred embodiments in conjunction with the attached drawings. The advantages of the additional aspects of the present application will be partially given in the following description, and partly become obvious from the following description, or be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0030] Figure 1 It is a principle block diagram of a control device for an analog storage-computation-in-one array based on an asynchronous paradigm as shown in an embodiment of the present application;

[0031] Figure 2 A circuit schematic diagram of the internal asynchronous loopback module shown in an embodiment of the present application;

[0032] Figure 3 A circuit schematic diagram of the external asynchronous handshake module shown in an embodiment of the present application;

[0033] Figure 4 This is a structural diagram of a low latency counter shown in an embodiment of the present application;

[0034] Figure 5 The circuit schematic diagram of the decoder shown in the embodiment of the present application

[0035] Figure 6 It is a principle block diagram of the gating circuit module shown in the embodiment of the present application;

[0036] Figure 7 Schematic diagram of a zeroing signal generating circuit shown in an embodiment of the present application. DETAILED DESCRIPTION

[0037] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0038] When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are only examples of methods and systems consistent with some aspects of the present application as detailed in the attached claims.

[0039] In the description of the present application, it should be understood that the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances. In addition, in the description of the present application, unless otherwise specified, "multiple" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship.

[0040] The application scenarios of AI models in network server deployment and end-side deployment are different as follows: the AI ​​chips in network servers emphasize reliability and calculation accuracy; while the AI ​​chips used in end-side smart terminals require fast response, but do not need to frequently process large amounts of data. In order to create end-side AI chips suitable for urban digital development, compared with synchronous clock circuits, asynchronous clock circuits can achieve low power standby in idle state while ensuring calculation speed, which is more suitable for the needs of urban digital development than synchronous clock circuits.

[0041] The present application proposes a control device for an analog storage and computing integrated array based on an asynchronous paradigm, including: an asynchronous handshake module and a finite state machine control module. Among them, the asynchronous handshake module includes an internal asynchronous loopback module implemented by using C-element (binary input with memory gate) and an external asynchronous handshake module implemented by using D flip-flop. The finite state machine control module adopts staggered counting design and pulse coding, and includes a low-latency counter and decoder and a zeroing signal generating circuit. The internal asynchronous loopback module is used to generate an asynchronous clock to control the analog storage and computing integrated array, and the external asynchronous handshake module realizes communication with other modules; the low-latency counter and decoder are used to mark the asynchronous clock sequence, and the zeroing signal generating circuit can control other modules to refresh the charge. The low-latency control circuit not only ensures the accurate transmission of data in the system unit, but also improves the density and operation efficiency of data processing, and optimizes the design and delay of the circuit, reduces charge loss, and improves the energy efficiency of the overall architecture.

[0042] This application is based on the Muller asynchronous pipeline unit to construct an asynchronous handshake module and an asynchronous loopback module with a start-stop structure, which can control the delay and reduce the area overhead. Based on the asynchronous handshake module, a peak-shifting counting finite state machine module is designed and pulse coding is used to generate various control signals, which has low bandwidth requirements, reduces the total delay of the control circuit, and improves reliability.

[0043] Example

[0044] A control device for simulating a storage-computing integrated array based on an asynchronous paradigm, such as Figure 1 As shown, including:

[0045] 1. An asynchronous loop handshake module is used to generate an asynchronous clock according to the operation results of the analog storage and computing integrated array, the instructions of the previous circuit and the state signal of the finite state machine control module, and control the asynchronous loop handshake module to communicate with the digital-to-analog converter through the asynchronous clock;

[0046] In the specific implementation process, the asynchronous loopback handshake module includes: an internal asynchronous loopback module and an external asynchronous handshake module;

[0047] The internal asynchronous loopback module is implemented by a circuit including a binary input and a memory gate, takes the clock of the digital-to-analog converter, the state signal of the finite state machine control module and the asynchronous zeroing signal as input, and takes the asynchronous clock as output, so as to realize the handshake communication with the digital-to-analog converter;

[0048] In a feasible implementation scheme, there is a delay during the period when the handshake count signal of the internal asynchronous loop module is set to 1 and the state signal of the finite state machine control module is set to 1, and the delay period is used to start the voltage source of the analog storage and computing integrated array.

[0049] In a feasible implementation scheme, the internal asynchronous loop module uses a first inverter, a second inverter, a first AND gate, a second AND gate, and a binary input memory gate circuit to form a loop structure;

[0050] Using the clock of the digital-to-analog converter as the input of the first inverter, using the output of the first inverter as the first input of the first AND gate, using the asynchronous zeroing signal as the second input of the first AND gate, and using the output of the first AND gate as the first input of the binary input memory gate circuit;

[0051] Using the asynchronous clock as the input of the second inverter, using the output of the second inverter as the first input of the second AND gate, using the state signal of the finite state machine control module as the second input of the second AND gate, and using the output of the second AND gate as the second input of the binary input memory gate circuit;

[0052] The output of the binary input memory gate circuit is used as the asynchronous clock.

[0053] The external asynchronous handshake module is implemented using a start-stop structure circuit and is used to communicate with the front-stage circuit of the control device of the analog storage and computing integrated array to control the internal asynchronous loop module. It takes the operation completion signal of the finite state machine control module, the start voltage signal of the analog storage and computing integrated array and the internal asynchronous loop module start output event signal as input, and takes the internal asynchronous loop module handshake count signal and the internal asynchronous loop module stop output event signal as output.

[0054] 2. A finite state machine control module is used to generate a selection signal according to the number of handshake communications, and send the selection signal and asynchronous clock to the selection module. The selection module controls the analog storage and computing integrated array through the selection signal and asynchronous clock.

[0055] In a feasible implementation scheme, the finite state machine control module includes: a counter and a decoder;

[0056] The counter uses an asynchronous clock counter circuit to achieve staggered counting, and is used to record the number of handshakes between the internal asynchronous loopback module and the digital-to-analog converter;

[0057] The decoder is used to generate a selection signal according to the handshake times between the internal asynchronous loopback module and the digital-to-analog converter when the asynchronous clock of the handshake rises, and the signal lasts until the asynchronous clock ends.

[0058] In a feasible implementation scheme, the finite state machine control module also includes: a zeroing signal generating circuit for clearing the residual charge in the analog storage and computing array, with a low-level asynchronous clock and a low-level zeroing signal as input, and a reset signal and a reset selection signal as output, wherein the reset signal is used to clear the data stored in the decoder, and the reset selection signal is used to control the storage and computing array to discharge.

[0059] In a feasible implementation scheme, the zeroing signal generating circuit includes: a D flip-flop, a delay circuit, a NOR gate, a third inverter, a fourth inverter and a fifth inverter;

[0060] The data input terminal of the D flip-flop is connected to a high-level signal, the clock input terminal of the D flip-flop is connected to one end of the delay circuit, the other end of the delay circuit is also connected to the reset input terminal of the D flip-flop, the output terminal of the D flip-flop is respectively connected to the input terminal of the third inverter and the second input terminal of the NOR gate, the output terminal of the third inverter is connected to the input terminal of the fifth inverter, the output terminal of the fifth inverter outputs a reset signal, the first input terminal of the NOR gate is connected to a low-level type zeroing signal, the output terminal of the NOR gate is connected to the input terminal of the fourth inverter, and the output terminal of the fourth inverter outputs a reset selection signal.

[0061] In order to explain the present application in more detail, specific examples are listed as follows. The circuit schematic diagram of the internal asynchronous loopback module is shown in FIG. Figure 2 , where adck corresponds to the digital-to-analog converter clock in the embodiment, and pulse corresponds to the asynchronous clock. The specific composition and working principle are described as follows:

[0062] The loop structure of the internal asynchronous loop module is based on C-element, which realizes pulse signal transmission and low-latency adck monitoring. Its output signal is pulse, input signal is adck, state control signal is state, and asynchronous zeroing signal is PRst. C-element is a binary input memory gate circuit with inputs A and B and output Y. The truth table is shown in Table 1. State and PRst are connected to the two input ends of C-element through AND gates, non-pulse and non-adck respectively. Pulse is connected to the output end of C-element. In the initial state, the adck input is 0, state and PRst are low, then A, B, and Y are all 0. After PRst switches to a high level, the module works normally, and A is set to 1 due to the influence of non-adck, but because state is a low level, B=0, Y=0 remains unchanged and is still 0. When the state signal from the finite state machine is pulled high, since A=B=1 leads to Y=1, the module outputs pulse at a high level, which serves as an event signal for other components such as the analog storage and computing array. Subsequently, due to the change of pulse, B=0 and Y=1 remain unchanged. After the calculation is completed, the array returns a high level adck as a confirmation signal. At this time, A=0, making Y=0, and the module stops outputting event signals until a new round of event signals is initiated after the confirmation signal ends. After the last adck rises, the finite state machine will pull down the state, and the control loop module ends its work.

[0063] Table 1 C-element truth table

[0064]

[0065] The circuit principle of the external asynchronous handshake module is as follows Figure 3As shown in the figure, after the transformation of the asynchronous Muller pipeline unit, the D1, D2, and D3 trigger modules are designed into an asynchronous handshake module with a start-stop structure. Its output signals are out_v, in_a, and the input signals are in_v, out_a, done. The internal state control signals are en and enB, and tiehi is connected to a high level. PRst has been integrated into the 2AND logic gate as a zeroing signal. Its functional logic is: if en=1 and out_a=0, the system is in an idle state. When in_v=1, the system starts, out_v=1, and the internal asynchronous loopback module starts to count with the ADC handshake. If the ADC handshake ends, the asynchronous state machine sends a signal done=1 to indicate that the operation is completed, then in_a=1, en=0, and the module completes the communication. If out_a=1 and in_a=1, the module is reset as a whole, so that out_v=0, in_a=0, en=1, and prepares for the next startup. In addition, there is a delay design of about 1ns from the time when out_v of the external asynchronous handshake module is set to 1 to the time when state of the internal asynchronous loopback module is set to 1. This time difference is used to start the voltage source of the analog storage and computing integrated array.

[0066] The counter and decoder in the finite state machine control module generate the main control signals. The shift register acts as a low-latency counter to record the six pulse handshakes made by pulse to complete the calculation of all weights. Among them, the first three handshakes correspond to data<1:0>. Each time the pulse is pulled high, the analog storage and calculation array is controlled to perform 1 unit of calculation; the highbit signal will be pulled high during the last three handshakes, indicating that this handshake performs 4 units of calculation. The specific function is implemented by the cnt-12 accumulator counter in the FSM ( Figure 4 ), the type is an asynchronous clock counter circuit. Since the internal asynchronous loop structure has a very low delay, using pulse as the counter accumulation signal will take up a lot of response time, so cnt-12 adopts a peak-shifting counting structure, which makes the counter +1 every time the pulse drops, avoiding the problem of squeezing delay. In order to make the pulse selected according to the data, Figure 5 The decoder generates the sel<3:0> signal according to the counter data, using bit 0 to identify the first pulse signal, bit 1 to identify the second and third pulse signals, bit 2 to identify the fourth pulse signal, and bit 3 to identify the fifth and sixth pulses.

[0067] signal. Only when the pulse rises, the decoder makes a sel signal valid and lasts until the pulse ends. The strobe module controls the bitwise AND operation of sel and data to select the pulse. The function of the strobe module is expressed by the following formula:

[0068] assign pulse_out=(|(sel&data))&pulse;

[0069] pulse_out is obtained by combining the logic of three signals: sel, data, and pulse.

[0070] Figure 6 This is the structure of the gating circuit module. The gating circuit module performs bitwise AND on sel and data, and the result represents whether sel and data match. If the match is successful, that is, the gating is successful, pulse_out will copy the pulse signal as the output of the gating circuit module, and the analog storage and calculation integrated array will call the data stored in SRAM for a calculation, and return adck as a confirmation signal after completion; if the match fails, that is, the gating fails, pulse_out will be set to 0, the analog storage and calculation integrated array will not perform calculations, and quickly return adck as a confirmation signal, prompting the control circuit to make the next calculation request as soon as possible.

[0071] After each calculation, the analog storage and computing array has residual charge, which requires a short-time pulse signal control to discharge, and it must not conflict with the calculation process. All zeroing signals in the analog storage and computing unit will be summarized in the control circuit, and its structure is as follows: Figure 7 As shown. Among them, tiehi is a high level, pulse_n comes from the internal asynchronous loop structure, and the output signals are rstsel and rst. Every time the pulse drops, the D flip-flop will generate a short pulse signal that can last for a short period of time through the control of the delay circuit, and will be split into rstsel and rst after modulation. Among them, rstsel is responsible for clearing the D flip-flop storage data in the decoder module; rst is responsible for outputting to the analog storage and computing integrated array to control discharge. The reason for the split is that when PRst is valid (0), the two functions are different: rstsel is required to be 1 to control the D flip-flop in the decoder module to clear the data; and rst is required to be 0, and the VDD-VSS path must not be formed when the analog storage and computing integrated array is reset to zero.

[0072] The present application provides a control device for an analog storage-computing integrated array based on an asynchronous paradigm, which realizes the communication protocol standard of an external asynchronous handshake and the low-latency requirement of an internal asynchronous loop through two design schemes of an asynchronous handshake module design; the asynchronous finite state machine control module adopts an offset counting and pulse coding circuit, and a decoder and a zeroing signal generating circuit designed based on internal and external asynchronous circuit control signals, thereby overcoming the problem of additional delay overhead caused by the asynchronous logic finite state machine control circuit designed by the usual method, and realizing low power consumption and miniaturization of asynchronous clock communication for the circuit of the analog storage-computing integrated architecture.

[0073] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-mentioned embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-mentioned embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

[0074] The applicant of this application has made a detailed explanation and description of the implementation examples of this application in conjunction with the drawings in the specification. However, those skilled in the art should understand that the above implementation examples are only preferred implementation schemes of this application, and the detailed description is only to help readers better understand the spirit of this application, and it is not a limitation on the scope of protection of this application. On the contrary, any improvements or modifications based on the inventive spirit of this application should fall within the scope of protection of this application.

Claims

1. A control device for simulating a storage-computation integrated array based on an asynchronous paradigm, characterized in that: include: The asynchronous loop handshake module is used to generate an asynchronous clock according to the operation results of the analog storage and computing integrated array, the instructions of the previous circuit and the state signal of the finite state machine control module, and control the asynchronous loop handshake module to communicate with the digital-to-analog converter through the asynchronous clock; The finite state machine control module is used to generate a selection signal according to the number of handshake communications, and send the selection signal and asynchronous clock to the selection module. The selection module controls the analog storage and computing integrated array through the selection signal and asynchronous clock.

2. The control device for the analog storage-computation integrated array based on the asynchronous paradigm according to claim 1 is characterized in that: The asynchronous loopback handshake module comprises: an internal asynchronous loopback module and an external asynchronous handshake module; The internal asynchronous loopback module is implemented by a circuit including a binary input and a memory gate, takes the clock of the digital-to-analog converter, the state signal of the finite state machine control module and the asynchronous zeroing signal as input, and takes the asynchronous clock as output, so as to realize handshake communication with the digital-to-analog converter; The external asynchronous handshake module is implemented using a circuit with a start-stop structure, and is used to communicate with the front-stage circuit of the control device of the analog storage and computing integrated array to control the internal asynchronous loop module. It takes the operation completion signal of the finite state machine control module, the starting voltage signal of the analog storage and computing integrated array, and the internal asynchronous loop module start output event signal as input, and takes the internal asynchronous loop module handshake count signal and the internal asynchronous loop module stop output event signal as output.

3. The control device for the analog storage-computation integrated array based on the asynchronous paradigm according to claim 2 is characterized in that: There is a delay during the period when the handshake count signal of the internal asynchronous loop module is set to 1 and the state signal of the finite state machine control module is set to 1. The delay period is used to start the voltage source of the analog storage and computing integrated array.

4. The control device for the analog storage-computation integrated array based on the asynchronous paradigm according to claim 1 is characterized in that: The finite state machine control module includes: a counter and a decoder; The counter uses an asynchronous clock counter circuit to implement staggered counting, and is used to record the number of handshakes between the internal asynchronous loopback module and the digital-to-analog converter; The decoder is used to generate a selection signal according to the number of handshakes between the internal asynchronous loopback module and the digital-to-analog converter when the asynchronous clock of the handshake rises, and the signal lasts until the asynchronous clock ends.

5. The control device for the analog storage-computation integrated array based on the asynchronous paradigm according to claim 1 is characterized in that: The finite state machine control module also includes: a zeroing signal generating circuit, which is used to clear the residual charge in the analog storage and computing integrated array, with a low-level type asynchronous clock and a low-level type zeroing signal as input, and a reset signal and a reset selection signal as output, wherein the reset signal is used to clear the data stored in the decoder, and the reset selection signal is used to control the analog storage and computing integrated array to discharge.

6. The control device for the analog storage-computation integrated array based on asynchronous paradigm according to claim 2, characterized in that: The internal asynchronous loop module uses a first inverter, a second inverter, a first AND gate, a second AND gate, and a binary input memory gate circuit to form a loop structure; Using the clock of the digital-to-analog converter as the input of the first inverter, using the output of the first inverter as the first input of the first AND gate, using the asynchronous zeroing signal as the second input of the first AND gate, and using the output of the first AND gate as the first input of the binary input memory gate circuit; Using the asynchronous clock as the input of the second inverter, using the output of the second inverter as the first input of the second AND gate, using the state signal of the finite state machine control module as the second input of the second AND gate, and using the output of the second AND gate as the second input of the binary input memory gate circuit; The output of the binary input memory gate circuit is used as the asynchronous clock.

7. The control device for the analog storage-computation integrated array based on asynchronous paradigm according to claim 5 is characterized in that: The zeroing signal generating circuit comprises: a D flip-flop, a delay circuit, a NOR gate, a third inverter, a fourth inverter and a fifth inverter; The data input terminal of the D flip-flop is connected to a high-level signal, the clock input terminal of the D flip-flop is connected to one end of the delay circuit, the other end of the delay circuit is also connected to the reset input terminal of the D flip-flop, the output terminal of the D flip-flop is respectively connected to the input terminal of the third inverter and the second input terminal of the NOR gate, the output terminal of the third inverter is connected to the input terminal of the fifth inverter, the output terminal of the fifth inverter outputs a reset signal, the first input terminal of the NOR gate is connected to a low-level type zeroing signal, the output terminal of the NOR gate is connected to the input terminal of the fourth inverter, and the output terminal of the fourth inverter outputs a reset selection signal.

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