Array welding spot fault scaleplate structure based on bonding pad size regulation and control and manufacturing method of array welding spot fault scaleplate structure

Abstract

The invention relates to the technical field of printed circuit boards, in particular to an array welding spot fault scale structure based on bonding pad size regulation and control and a manufacturing method. The array welding spot fault scale structure based on bonding pad size regulation and control comprises a chip and a substrate, the chip is provided with a first welding surface, the first welding surface is divided into a first welding area and a second welding area, and the second welding area is arranged around the first welding area; the substrate is provided with a second welding surface which is parallel to the first welding surface at an interval; wherein the first welding area and the second welding surface are connected through a plurality of first welding spots so as to realize functional signal interaction between the chip and the substrate, the second welding area and the second welding surface are connected through a plurality of second welding spots, and a current monitoring loop connected with the first welding spots is configured on the chip / substrate. And the pad area of the second welding spot is not greater than that of the first welding spot. The service life of the welding spot can be predicted / monitored more accurately, the structure is simple, and the space occupancy rate is smaller.

Description

Technical Field

[0001] The present application relates to the technical field of printed circuit boards, and in particular to a structure and a manufacturing method for an array solder joint fault scale based on pad size regulation. Background Art

[0002] With the rapid development of science and technology, the reliability of electronic products has become an important issue of concern to both manufacturers and consumers. Modern chips are getting smaller and smaller and more integrated, resulting in a significant increase in the size and density of solder joints. Electronic devices usually work in harsh environments, including high temperature, high humidity, vibration, etc. These environmental factors impose additional burdens on solder joints, which may cause physical and chemical degradation of solder joints and accelerate the failure process. A canary fault ruler is a product that is more sensitive to the load conditions experienced by its surroundings or the monitored product. Under the same environmental and operating load conditions, the fault ruler is more sensitive and can fail faster than the monitored object, thereby providing early warning and life prediction for the monitored object.

[0003] A Japanese invention patent with patent number JP2016100361A5 discloses a circuit board with a life prediction function and a life prediction method for solder connections. By additionally arranging a life prediction unit on the circuit board, the fracture condition of the solder connection part in the life prediction unit can be used to predict / warn the life of the solder connection part of the electronic component / device. However, this method requires providing an additional connection area / space for the life prediction unit, resulting in a larger overall space occupation of the circuit board. At the same time, the patent increases the stress level of the solder connection part by increasing the span of the two solder connection parts in the life prediction unit. The life prediction unit is relatively independent of the electronic component / device structure, and the stress boundary conditions of the life prediction unit and the solder connection part in the electronic component / device are quite different, and the accuracy of life prediction / warning needs to be improved. Summary of the invention

[0004] The present application provides an array solder joint fault scale structure and a manufacturing method based on pad size control. Based on the stress distribution law on the chip welding side, the solder joints between the chip and the substrate are divided, and the life of other solder joints is predicted / warned through the fracture of some of the solder joints between the chip and the substrate. The predicted / warned solder joints and the predicted / warned solder joints are in the same structure, thereby solving the problem of large differences in stress boundary conditions and relatively low accuracy of life prediction / warning in the prior art.

[0005] This application is implemented through the following technical solutions:

[0006] In a first aspect, the present application provides an array solder joint fault scale structure based on pad size control, comprising:

[0007] A chip, wherein the chip has a first welding surface, the first welding surface is divided into a first welding area and a second welding area, and the second welding area is arranged around the first welding area;

[0008] A substrate having a second welding surface arranged parallel to and spaced from the first welding surface;

[0009] The first welding area and the second welding surface are connected through a plurality of first welding points to realize functional signal interaction between the chip and the substrate, and the second welding area and the second welding surface are connected through a plurality of second welding points, wherein a current monitoring loop connected to the second welding point is arranged on the chip / substrate, and the pad area of ​​the second welding point is not larger than the pad area of ​​the first welding point.

[0010] The present application provides an array solder joint fault scale structure based on pad size control. In the connection area between the chip and the substrate, the solder joints at the edge of the connection area are subjected to relatively greater stress than the solder joints at other positions. The first soldering surface on the chip is divided into a first soldering area and a second soldering area arranged around the first soldering area. The first solder joints that realize functional signal interaction are arranged in the first soldering area, and the second solder joints are arranged in the second soldering area. In the working state, the stress on the second solder joint is greater than that on the first solder joint. The fracture condition of the second solder joint is monitored through the current monitoring circuit on the chip / substrate, thereby realizing the prediction / early warning of the life of the first solder joint.

[0011] The present application provides an array solder point fault scale structure based on pad size control, in which the first solder point and the second solder point are both connected between the chip and the substrate. Except for the difference in pad area and layout position, the stress boundary conditions of the first solder point and the second solder point are even smaller. Under this condition, when the life of the first solder point is predicted / warned by the second solder point, the accuracy and credibility are higher.

[0012] The array solder point fault scale structure based on pad size control provided in the present application divides the arrangement positions of the first solder point and the second solder point, and the pad area of ​​the second solder point is not larger than the pad area of ​​the first solder point. When the first solder point and the second solder point are in the same working condition, it can ensure that the second solder point breaks before the first solder point, which means that the second solder point can realize the life prediction / warning function before the first solder point breaks, thereby avoiding damage / error of chip function signals due to the breakage of the first solder point, and further avoiding abnormal operation and damage of other peripheral controlled ends. In this life prediction / warning mode, it can protect the peripheral controlled equipment.

[0013] In some optional embodiments, the pad area of ​​the second solder joint is not less than 60% of the pad area of ​​the first solder joint.

[0014] In some optional embodiments, the pad area of ​​the second solder joint is configured to be 85% of the pad area of ​​the first solder joint.

[0015] In some optional embodiments, the pad area of ​​the second solder joint is configured to be 75% of the pad area of ​​the first solder joint.

[0016] In some optional embodiments, the first welding points and the second welding points together form an array arrangement.

[0017] In a second aspect, the present application provides another array solder joint fault scale structure based on pad size control, including:

[0018] A chip, wherein the chip has a first welding surface, the first welding surface has a polygonal welding area, the welding area is divided into a first welding area and a second welding area, wherein the second welding area is located at a corner of the welding area;

[0019] A substrate having a second welding surface arranged parallel to and spaced from the first welding surface;

[0020] Among them, the first welding area and the second welding surface are connected through a plurality of first welding points to realize functional signal interaction between the chip and the substrate, and the second welding area and the second welding surface are connected through a plurality of second welding points, and the pad area of ​​the second welding point is not larger than the pad area of ​​the first welding point.

[0021] The array solder joint fault scale structure based on pad size control provided in the present application is suitable for the case where the first soldering surface of the chip is a polygonal shape, for example, the first soldering surface is a rectangle. In the working state, after the chip is connected to the substrate through the first soldering surface, the stress at the four corner positions on the first soldering surface is the largest, and gradually decreases from the four corners to the inside. By dividing the corner positions on the first soldering surface into second soldering areas, and arranging the first soldering points for realizing functional signal interaction in the first soldering area, the stress on the second soldering points from the corners to the inside in the second soldering area decreases successively. According to this rule, a gradient warning / prediction threshold can be set, which means that the second soldering area is further subdivided according to the distance between each location of the second soldering area and the center position of the first soldering surface. Based on the monitoring of the fracture conditions of the second soldering points at different positions in the second soldering area, it is convenient for the peripheral control equipment to adaptively adjust the working conditions, thereby achieving the purpose of extending the service life of the chip.

[0022] In some optional embodiments, the shape of the second welding area is configured as a triangle.

[0023] In some optional embodiments, the second welding points are arranged in an array.

[0024] In some optional embodiments, the pad area of ​​the second solder joint is not less than 60% of the pad area of ​​the first solder joint.

[0025] In a third aspect, the present application provides a method for making an array solder joint fault scale based on pad size control, comprising the following contents:

[0026] Constructing a test sample model, wherein the test sample model includes a chip part, a substrate part, and a plurality of solder joints connected to the chip part and arranged in a row;

[0027] Perform stress analysis on the test sample model to obtain the stress distribution diagram of the solder joint;

[0028] Dividing the welding surface of the chip part into a first welding area and a second welding area based on the stress distribution diagram of the welding point, wherein the second welding area is located outside the first welding area or the second welding area is located at a corner position within the first welding area;

[0029] Configuring the functional signal nodes of the chip to be located in the first welding area;

[0030] Providing a chip entity and a substrate entity;

[0031] A first welding area in the chip entity is connected to the substrate entity through a first welding point, and a second welding area in the chip entity is connected to the substrate entity through a second welding point, wherein a current monitoring loop connected to the second welding point is configured on the chip entity / substrate entity.

[0032] Compared with the prior art, this application has the following advantages and beneficial effects:

[0033] 1. The present application provides an array solder joint fault scale structure and a manufacturing method based on pad size control. In the connection area between the chip and the substrate, the solder joints at the edge of the connection area are subjected to relatively greater stress than the solder joints at other positions. The first welding surface on the chip is divided into a first welding area and a second welding area arranged around the first welding area. The first solder joints for realizing functional signal interaction are arranged in the first welding area, and the second solder joints are arranged in the second welding area. In the working state, the stress on the second solder joint is greater than that on the first solder joint. The fracture condition of the second solder joint is monitored through the current monitoring circuit on the chip / substrate, thereby realizing the prediction / early warning of the life of the first solder joint.

[0034] 2. The present application provides an array solder point fault scale structure and manufacturing method based on pad size control. The first solder point and the second solder point are both connected between the chip and the substrate. Except for the different pad areas and layout positions, the stress boundary conditions of the first solder point and the second solder point are even smaller. Under this condition, when the life of the first solder point is predicted / warned by the second solder point, the accuracy and reliability are higher.

[0035] 3. The array solder point fault scale structure and manufacturing method based on pad size control provided in the present application divide the arrangement positions of the first solder point and the second solder point, and the pad area of ​​the second solder point is not larger than the pad area of ​​the first solder point. When the first solder point and the second solder point are in the same working condition, it can ensure that the second solder point breaks before the first solder point, which means that the second solder point can realize the life prediction / warning function before the first solder point breaks, thereby avoiding damage / error of chip function signals due to the breakage of the first solder point, and further avoiding abnormal operation and damage of other peripheral controlled ends. In this life prediction / warning mode, it can protect the peripheral controlled equipment.

[0036] 4. The array solder point fault scale structure and manufacturing method based on pad size control provided in the present application can be particularly suitable for the case where the first welding surface of the chip is a polygonal shape. For example, the first welding surface is a rectangle. In the working state, after the chip is connected to the substrate through the first welding surface, the stress at the four corner positions on the first welding surface is the largest and gradually decreases from the four corners to the inside. By dividing the corner positions on the first welding surface into second welding areas, and arranging the first solder points for realizing functional signal interaction in the first welding area, the stress on the second solder points from the corners to the inside in the second welding area decreases successively. According to this rule, a gradient warning / prediction threshold can be set, which means that the second welding area is further subdivided according to the distance between each location of the second welding area and the center position of the first welding surface. Based on the monitoring of the fracture conditions of the second solder points at different positions in the second welding area, it is convenient for the peripheral control equipment to adaptively adjust the working conditions, thereby achieving the purpose of extending the service life of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present application and should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work. In the drawings:

[0038] Figure 1 A schematic diagram of the structure of an array solder point fault scale based on pad size control provided in an embodiment of the present application;

[0039] Figure 2 A schematic diagram of a chip plane when the pad areas of the first solder joint and the second solder joint provided in the embodiment of the present application are equal;

[0040] Figure 3 Another schematic diagram of a chip plane when the pad areas of the first solder joint and the second solder joint provided in the embodiment of the present application are equal;

[0041] Figure 4 A schematic diagram of a chip plane when the pad area of ​​the first solder joint provided in the embodiment of the present application is larger than the pad area of ​​the second solder joint;

[0042] Figure 5 A schematic diagram of a chip plane in another array solder joint fault scale structure based on pad size control provided in an embodiment of the present application;

[0043] Figure 6 A schematic diagram of a substrate plane provided in an embodiment of the present application.

[0044] Marks and corresponding parts names in the attached drawings:

[0045] 100 - chip, 101 - first welding area, 102 - second welding area, 103 - first welding surface, 200 - substrate, 201 - second welding surface, 300 - first welding point, 400 - second welding point. DETAILED DESCRIPTION

[0046] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with examples and drawings. The illustrative implementation scheme of the present application and its description are only used to explain the present application and are not intended to limit the present application.

[0047] First, please refer to Figure 1 to Figure 6 ,in Figure 1 to Figure 6 The dotted line in the figure is a dividing line. The embodiment of the present application provides an array solder joint fault scale structure based on pad size regulation, and the array solder joint fault scale structure based on pad size regulation includes a chip 100 and a substrate 200; the chip 100 has a first welding surface 103, and the first welding surface 103 is divided into a first welding area 101 and a second welding area 102, and the second welding area 102 is arranged around the first welding area 101; the substrate 200 has a second welding surface 201 arranged parallel to the first welding surface 103 and spaced apart; wherein the first welding area 101 and the second welding surface 201 are connected through a plurality of first welding points 300 to realize functional signal interaction between the chip 100 and the substrate 200, and the second welding area 102 and the second welding surface 201 are connected through a plurality of second welding points 400, wherein a current monitoring loop connected to the second welding point 400 is configured on the chip 100 / substrate 200, and the pad area of ​​the second welding point 400 is not greater than the pad area of ​​the first welding point 300.

[0048] In the embodiment of the present application, the substrate 200 is generally configured as a printed circuit board.

[0049] In the embodiment of the present application, the shape of the chip 100 is generally rectangular, so the first welding surface 103 described in the embodiment of the present application is generally a rectangular plate surface of the chip 100 or a rectangular area within a rectangular plate surface on the chip 100. The first welding area 101 in the embodiment of the present application can generally be arranged in a rectangular shape, and the second welding area 102 can generally be arranged in a rectangular ring shape. In other embodiments, the first welding surface 103 on the chip 100 may be configured as other shapes such as a circle, a polygon, a star, etc. based on different functional requirements or different connection requirements. In this case, the first welding area 101 can be adapted to any shape according to the actual manufacturing process, and the second welding area 102 can be set to a ring shape similar to the shape of the first welding surface 103. Under this connection condition, the stress level on the side of the first welding area 101 is usually greater than the stress level on the inner side of the first welding area 101. Therefore, under the working state, the failure probability of the second welding point 400 is greater than the failure probability of the first welding point 300. Under extreme working conditions, when the second welding point 400 breaks, the electrical signal in the current monitoring circuit fluctuates abnormally / is lost. At this time, a life prediction / warning signal can be fed back to other devices such as the control system / processor, so that the peripheral controlled equipment can be shut down / standby quickly, avoiding abnormal operation of the peripheral controlled equipment due to functional disorder / abnormality caused by the breakage of the first welding point 300.

[0050] The functional signal interaction described in the embodiment of the present application refers to the interaction of control signals, data signals and other control-related signals between the chip 100 and the substrate 200 or other peripheral controlled terminals, which means that the first welding point 300 is a necessary welding node for the chip 100 to achieve control; the second welding point 400 only plays a connecting role and the role of conducting current in the current monitoring loop.

[0051] In the array solder joint fault scale structure based on pad size control provided by the embodiment of the present application, the first solder joint 300 and the second solder joint 400 are both connected between the chip 100 and the substrate 200. In addition to the difference in pad area and arrangement position between the two, the stress boundary conditions of the first solder joint 300 and the second solder joint 400 are smaller. Under this condition, when the life of the first solder joint 300 is predicted / warned by the second solder joint 400, the accuracy and credibility are higher. Compared with the life prediction structure provided by the prior art, the embodiment of the present application does not need to set other structures on the substrate 200 to extend the span of the solder connection part, and the first solder joint 300 and the second solder joint 400 are in the same structure (that is, both are connected between the chip 100 and the substrate 200). On the one hand, the overall size of the structure is controlled and the space occupancy rate is smaller. On the other hand, the life of the second solder joint 400 is closer to the life of the first solder joint 300, and the life prediction / warning result provided by the second solder joint 400 is closer to the actual life of the first solder joint 300, and the tolerance of the applicable extreme working conditions is relatively better.

[0052] The array solder joint fault scale structure based on pad size control provided in the embodiment of the present application divides the arrangement positions of the first solder joint 300 and the second solder joint 400, and the pad area of ​​the second solder joint 400 is not larger than the pad area of ​​the first solder joint 300. When the first solder joint 300 and the second solder joint 400 are in the same working condition, it can ensure that the second solder joint 400 breaks before the first solder joint 300, which means that the second solder joint 400 can realize the life prediction / warning function before the first solder joint 300 breaks, thereby avoiding damage / error of the functional signal of the chip 100 due to the breakage of the first solder joint 300, and further avoiding abnormal operation and damage of other peripheral controlled terminals. In this life prediction / warning mode, it can protect the peripheral controlled equipment.

[0053] In some optional embodiments, the pad area of ​​the second solder joint 400 is not less than 60% of the pad area of ​​the first solder joint 300 .

[0054] In the embodiment of the present application, when the pad area of ​​the second solder joint 400 is equal to the pad area of ​​the first solder joint 300, the failure rate of the second solder joint 400 can be higher than the failure rate of the first solder joint 300 based on the different stress distribution of the connection structure between the chip 100 and the substrate 200 under the working condition, or the pad area of ​​the second solder joint 400 can be smaller than the pad area of ​​the first solder joint 300 to improve the life prediction / monitoring sensitivity. In particular, in certain working environments, the working conditions are prone to sudden changes. By improving the life prediction / monitoring sensitivity, it can be further ensured that the control state / working state is adjusted in time after the second solder joint 400 breaks and before the first solder joint 300 breaks; of course, the pad area of ​​the second solder joint 400 cannot be too small. Usually, the pad area of ​​the second solder joint 400 is set to be not less than 60% of the pad area of ​​the first solder joint 300 to ensure that the second solder joint 400 has a normal life prediction / warning function.

[0055] In some optional embodiments, according to different functional requirements and working environments, the pad area of ​​the second solder joint 400 may be configured to be 85% of the pad area of ​​the first solder joint 300 .

[0056] In some optional embodiments, according to different functional requirements and working environments, the pad area of ​​the second solder joint 400 may be configured to be 75% of the pad area of ​​the first solder joint 300 .

[0057] In some optional embodiments, the first solder joints 300 and the second solder joints 400 are arranged in an array together. This means that the first solder joints 300 and the second solder joints 400 are arranged in the same manner. In a common design, the solder joints between the chip 100 and the substrate 200 are arranged in an array structure, which can facilitate manufacturing and enhance thermal management. In the embodiment of the present application, the first solder joints 300 and the second solder joints 400 are arranged in the same manner, which can also ensure that the stress boundary conditions of the first solder joints 300 and the second solder joints 400 are more similar, which will help improve the accuracy of life prediction / monitoring.

[0058] In the embodiments of this application, please refer to Figure 2 and Figure 3 When the first welding area 101 is configured as a rectangular shape and the second welding area 102 is configured as a rectangular ring shape, the second welding points 400 in the second welding area 102 can be one circle or multiple circles from the center of the chip 100 to the outside. At the same time, the first welding area 101 and the first welding surface 103 are not necessarily arranged in the center, which means that the number of rows / columns of the second welding points 400 on both sides of the first welding area 101 can be different. Those skilled in the art can adaptively adjust the number of circles of the second welding points 400 and the number of rows and columns of the second welding points 400 on all sides of the first welding area 101 according to actual operating conditions.

[0059] In the second aspect, the embodiment of the present application provides another array solder joint fault scale structure based on pad size control, which includes a chip 100 and a substrate 200; the chip 100 has a first welding surface 103, the first welding surface 103 has a polygonal welding area, and the welding area is divided into a first welding area 101 and a second welding area 102, wherein the second welding area 102 is located at the corner position of the welding area, which can also be understood as taking the welding area as the first welding area 101, and separating the corner position in the first welding area 101 as the second welding area 102; the substrate 200 has a second welding surface 201 arranged parallel to the first welding surface 103; wherein the first welding area 101 and the second welding surface 201 are connected by a plurality of first welding points 300 to realize the functional signal interaction between the chip 100 and the substrate 200, and the second welding area 102 and the second welding surface 201 are connected by a plurality of second welding points 400, and the pad area of ​​the second welding point 400 is not greater than the pad area of ​​the first welding point 300.

[0060] The difference between the array solder point fault scale structure based on pad size regulation provided in the embodiment of the present application and the array solder point fault scale structure based on pad size regulation provided above is that the arrangement of the first soldering area 101 and the second soldering area 102 in the embodiment of the present application is different. The embodiment of the present application is applicable to the case where the first welding surface 103 of the chip 100 is a polygonal shape. For example, when the first welding surface 103 of the chip 100 is a rectangle, the solder joints between the chip 100 and the substrate 200 are usually arranged in a rectangular array. Under the structure of the chip 100, the stress levels of the four corners of the chip 100 are greater than those of the sides and the inside. In this case, the second soldering area 102 can be arranged at the corner position of the first soldering surface 103. At the same time, under the structure of the chip 100, the stress on the solder joints gradually decreases in the direction extending from the corner to the inside, and the stress on the solder joints at the corner vertices is the greatest. According to this rule, a gradient warning / prediction threshold can be set, which means that the second soldering area 102 is further subdivided according to the distance between each part of the second soldering area 102 and the center position of the first soldering surface 103, for example, the corner vertices When the second solder joint 400 at the position is broken, it means that the first prediction / warning threshold is reached; when the second solder joint 400 at the internal position of the corner area is broken, it means that the second prediction / warning threshold is reached; when the second solder joint 400 at the side position close to the center of the first welding surface 103 on the corner area is broken, it means that the third prediction / warning threshold is reached. Based on the monitoring of the fracture conditions of the second solder joints 400 at different positions in the second welding area 102, it is convenient for the peripheral control equipment to adaptively adjust the working conditions. For example, under the first prediction / warning threshold and the second prediction / warning threshold, the working conditions can be improved and adjusted through the peripheral control equipment. Under the third prediction / warning threshold, the peripheral controlled equipment is shut down / put on standby, which will be able to achieve the purpose of extending the service life of the chip 100, reduce the maintenance / replacement frequency of the chip 100, and reduce the cost of use.

[0061] In some optional embodiments, the shape of the second welding region 102 is configured as a triangle.

[0062] In the embodiment of the present application, the corner vertex of the first welding surface 103 corresponds to the vertex of the triangle, and the number of second welding points 400 in the second welding area 102 may not be limited, for example, it may be one, two, three, four... In actual implementation, the number of second welding points 400 may preferably be set to one or three or six or ten..., that is, all the second welding points 400 can form a triangular array arrangement in the triangular-shaped second welding area 102; the stress change of the triangular second welding area 102 from the vertex to the inner side is similar to the stress change in the physical structure of the chip, and when the second welding points 400 are arranged in an array in the second welding area 102, the life prediction / monitoring function can be implemented more accurately.

[0063] In some optional embodiments, the pad area of ​​the second solder joint 400 is not less than 60% of the pad area of ​​the first solder joint 300 .

[0064] In the embodiment of the present application, when the pad area of ​​the second solder joint 400 is equal to the pad area of ​​the first solder joint 300, the failure rate of the second solder joint 400 can be higher than the failure rate of the first solder joint 300 based on the different stress distribution of the connection structure between the chip 100 and the substrate 200 under the working condition, or the pad area of ​​the second solder joint 400 can be smaller than the pad area of ​​the first solder joint 300 to improve the life prediction / monitoring sensitivity. In particular, in certain working environments, the working conditions are prone to sudden changes. By improving the life prediction / monitoring sensitivity, it can be further ensured that the control state / working state is adjusted in time after the second solder joint 400 breaks and before the first solder joint 300 breaks; of course, the pad area of ​​the second solder joint 400 cannot be too small. Usually, the pad area of ​​the second solder joint 400 is set to be not less than 60% of the pad area of ​​the first solder joint 300 to ensure that the second solder joint 400 has a normal life prediction / warning function.

[0065] In some optional embodiments, according to different functional requirements and working environments, the pad area of ​​the second solder joint 400 may be configured to be 85% of the pad area of ​​the first solder joint 300 .

[0066] In some optional embodiments, according to different functional requirements and working environments, the pad area of ​​the second solder joint 400 may be configured to be 75% of the pad area of ​​the first solder joint 300 .

[0067] In a third aspect, an embodiment of the present application provides a method for making an array solder joint fault scale based on pad size control, and the method for making an array solder joint fault scale based on pad size control includes the following contents:

[0068] A test sample model is constructed, wherein the test sample model includes a chip portion, a substrate portion, and a plurality of solder joints connected to the chip portion and arranged in a row.

[0069] Perform stress analysis on the test specimen model to obtain the stress distribution diagram of the solder joint.

[0070] The welding surface of the chip part is divided into a first welding area 101 and a second welding area 102 based on the stress distribution diagram of the welding point, wherein the second welding area 102 is located outside the first welding area 101 or the second welding area 102 is located at a corner position in the first welding area 101.

[0071] The functional signal nodes of the chip are configured to be located within the first bonding area 101 .

[0072] A chip entity and a substrate entity are provided.

[0073] The first welding area 101 in the chip entity is connected to the substrate entity through the first welding point 300, and the second welding area 102 in the chip entity is connected to the substrate entity through the second welding point 400, wherein a current monitoring loop connected to the second welding point 400 is configured on the chip entity / substrate entity.

[0074] The above specific embodiments illustrate the implementation methods of the present application. Those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Although the description of the present application will be introduced in conjunction with some embodiments, this does not mean that the features of this application are limited to the implementation methods. On the contrary, the purpose of introducing the application in conjunction with the implementation methods is to cover other options or modifications that may be extended based on the claims of the present application. In order to provide an in-depth understanding of the present application, the above description contains many specific details. The present application can also be implemented without using these details. In addition, in order to avoid confusion or blurring the focus of the present application, some specific details will be omitted in the description. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0075] It should be noted that in this specification, similar numbers and letters represent similar items in the above drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. In the description of this application, it should be noted that the orientation or position relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc. is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or it can be a connection between the two elements. For those skilled in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0076] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. An array solder joint fault scale structure based on pad size control, characterized in that: include: A chip (100), the chip (100) having a first welding surface (103), the first welding surface (103) being divided into a first welding area (101) and a second welding area (102), the second welding area (102) being arranged around the first welding area (101); A substrate (200), the substrate (200) having a second welding surface (201) arranged parallel to and spaced from the first welding surface (103); The first welding area (101) and the second welding surface (201) are connected via a plurality of first welding points (300) to achieve functional signal interaction between the chip (100) and the substrate (200), and the second welding area (102) and the second welding surface (201) are connected via a plurality of second welding points (400), wherein a current monitoring loop connected to the second welding point (400) is arranged on the chip (100) / substrate (200), and the pad area of ​​the second welding point (400) is not greater than the pad area of ​​the first welding point (300).

2. The array solder joint fault scale structure based on pad size control according to claim 1, characterized in that: The pad area of ​​the second soldering point (400) is not less than 60% of the pad area of ​​the first soldering point (300).

3. The array solder joint fault scale structure based on pad size control according to claim 1, characterized in that: The pad area of ​​the second solder joint (400) is configured to be 85% of the pad area of ​​the first solder joint (300).

4. The array solder joint fault scale structure based on pad size control according to claim 1, characterized in that: The pad area of ​​the second solder joint (400) is configured to be 75% of the pad area of ​​the first solder joint (300).

5. The array solder joint fault scale structure based on pad size control according to claim 1, characterized in that: The first welding points (300) and the second welding points (400) together form an array arrangement.

6. An array solder joint fault scale structure based on pad size control, characterized in that: include: A chip (100), the chip (100) having a first welding surface (103), the first welding surface (103) having a polygonal welding area, the welding area being divided into a first welding area (101) and a second welding area (102), wherein the second welding area (102) is located at a corner of the welding area; A substrate (200), the substrate (200) having a second welding surface (201) arranged parallel to and spaced from the first welding surface (103); The first welding area (101) and the second welding surface (201) are connected via a plurality of first welding points (300) to achieve functional signal interaction between the chip (100) and the substrate (200), and the second welding area (102) and the second welding surface (201) are connected via a plurality of second welding points (400), wherein the pad area of ​​the second welding point (400) is not greater than the pad area of ​​the first welding point (300).

7. The array solder joint fault scale structure based on pad size control according to claim 6, characterized in that: The second welding area (102) is configured in a triangular shape.

8. The array solder joint fault scale structure based on pad size control according to claim 7, characterized in that: The second welding points (400) are arranged in an array.

9. The array solder joint fault scale structure based on pad size control according to claim 6, characterized in that: The pad area of ​​the second soldering point (400) is not less than 60% of the pad area of ​​the first soldering point (300).

10. A method for making an array solder joint fault scale based on pad size control, characterized in that: Includes the following: Constructing a test sample model, wherein the test sample model includes a chip part, a substrate part, and a plurality of solder joints connected to the chip part and arranged in a row; Perform stress analysis on the test sample model to obtain the stress distribution diagram of the solder joint; Dividing the welding surface of the chip part into a first welding area (101) and a second welding area (102) based on the stress distribution diagram of the welding point, wherein the second welding area (102) is located outside the first welding area (101) or the second welding area (102) is located at a corner position within the first welding area (101); Configuring the functional signal nodes of the chip to be located within the first welding area (101); Providing a chip entity and a substrate entity; A first welding area (101) in a chip entity is connected to a substrate entity via a first welding point (300), and a second welding area (102) in the chip entity is connected to a substrate entity via a second welding point (400), wherein a current monitoring loop connected to the second welding point (400) is configured on the chip entity / substrate entity.

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