Semiconductor device, manufacturing method thereof, and memory system

Abstract

The embodiment of the invention provides a semiconductor structure and a manufacturing method thereof, a memory and a memory system. The manufacturing method of the semiconductor structure comprises the following steps: providing a substrate; wherein the substrate comprises a plurality of semiconductor columns which are arranged at intervals, a first groove which extends along a first direction is formed in the substrate, and the first groove is located between the adjacent semiconductor columns; the first direction is parallel to the surface of the substrate; forming a gate material layer on the side wall and the bottom of the first groove; forming a barrier layer on the surface of the gate material layer on the side wall of the first groove; etching the gate material layer based on the barrier layer; wherein the gate material layer which is located on the side wall of the first groove and covered by the barrier layer is partially reserved, and a gate layer is formed.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor device and a manufacturing method thereof, and a memory system. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a high-speed, high-storage-density volatile memory that is widely used in electronic devices and devices such as smartphones, personal computers, and servers. The memory cell array of DRAM includes a transistor array, and each capacitor and a transistor constitute a memory cell. In some examples, the memory cell of DRAM can use a vertical channel transistor, and the word line is set in the transistor array and coupled to the channel region. In this case, the word line formation process is relatively complicated, resulting in a longer process cycle of the device and an increased cost. Summary of the invention

[0003] In view of this, embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof, and a memory system.

[0004] According to a first aspect of the present disclosure, there is provided a method for manufacturing a semiconductor device, comprising:

[0005] A substrate is provided; wherein the substrate comprises a plurality of semiconductor pillars arranged at intervals, a first groove extending along a first direction is formed in the substrate, and the first groove is located between adjacent semiconductor pillars; and the first direction is parallel to the surface of the substrate;

[0006] forming a gate material layer on the surface of the substrate, the sidewalls and the bottom of the first trench;

[0007] forming a barrier layer on a surface of the gate material layer located on a sidewall of the first trench;

[0008] The gate material layer is etched based on the barrier layer; wherein the gate material layer located on the sidewall of the first trench and covered by the barrier layer is partially retained to form a gate layer.

[0009] In some embodiments, forming a barrier layer on a surface of the gate material layer located on a sidewall of the first trench includes:

[0010] forming a barrier material layer covering the gate material layer;

[0011] Injecting doping ions into the barrier material layer located on the surface of the substrate and the bottom of the first trench to form a doping region; wherein the doping region has a first etching rate, and the region located on the sidewall of the first trench where the doping ions are not injected has a second etching rate, and the first etching rate is greater than the second etching rate;

[0012] The barrier material layer is etched to remove the doped region, and the remaining barrier material layer located on the sidewall of the first trench forms the barrier layer.

[0013] In some embodiments, the step of implanting dopant ions into the barrier material layer located on the surface of the substrate and the bottom of the first trench comprises:

[0014] The doping ion beam is implanted into the barrier material layer along a direction perpendicular to the surface of the substrate.

[0015] In some embodiments, the barrier material layer has a crystalline structure;

[0016] In the step of injecting doping ions into the barrier material layer located on the surface of the substrate and the bottom of the first trench, the doping region is transformed from the crystalline structure to the amorphous structure, and the doping region having the amorphous structure has the first etching rate.

[0017] In some embodiments, the material of the barrier material layer includes aluminum oxide.

[0018] In some embodiments, the thickness of the barrier material layer is greater than or equal to 1.5 nm.

[0019] In some embodiments, etching the gate material layer based on the barrier layer includes:

[0020] The gate material layer is etched using an etching solution, the gate material layer located on the substrate surface and the bottom of the first trench is removed, and the upper and lower parts of the gate material layer located on the sidewalls of the first trench are removed, and the remaining middle part of the gate material layer located on the sidewalls of the first trench forms the gate layer; wherein the upper part, the middle part and the lower part are arranged in sequence along a direction perpendicular to the substrate surface.

[0021] In some embodiments, the semiconductor column includes a first source and drain region, a channel region, and a second source and drain region sequentially arranged in a direction perpendicular to the surface of the substrate;

[0022] In the step of forming the gate layer, the gate layer and the channel region are arranged opposite to each other.

[0023] In some embodiments, the manufacturing method further comprises:

[0024] removing the barrier layer;

[0025] A first isolation structure is formed in the first trench; wherein the first isolation structure includes an air gap.

[0026] In some embodiments, the base includes a substrate and a stop layer located on a surface of the substrate, the substrate includes the semiconductor pillar, and the first trench penetrates the stop layer and extends between adjacent semiconductor pillars;

[0027] The manufacturing method further comprises:

[0028] Forming a gate dielectric material layer covering the stop layer, the sidewalls and the bottom of the first trench; wherein the gate material layer covers the surface of the gate dielectric material layer;

[0029] The gate dielectric material layer is processed by a planarization process until the stop layer is exposed; and the remaining gate dielectric material layer forms a gate dielectric layer.

[0030] In some embodiments, providing a substrate comprises:

[0031] providing a substrate;

[0032] A second trench extending along a second direction is formed in the substrate, and a plurality of the second trenches are arranged side by side along the first direction; wherein adjacent second trenches define an active area in the substrate; and the second direction intersects the first direction;

[0033] filling the second trench to form a second isolation material layer;

[0034] The first trench extending along the first direction is formed in the substrate; wherein the first trench passes through the active area and the second isolation material layer, and the remaining active area forms the plurality of semiconductor pillars.

[0035] According to a second aspect of the present disclosure, there is provided a semiconductor device, comprising:

[0036] A semiconductor layer, comprising a plurality of semiconductor columns arranged in an array along a first direction and a second direction intersecting each other, wherein the semiconductor columns comprise a first source and drain region, a channel region, and a second source and drain region sequentially arranged along a vertical direction; the first direction and the second direction are parallel to the semiconductor layer, and the vertical direction is perpendicular to the semiconductor layer;

[0037] a gate layer extending along the first direction and located on a side wall of the semiconductor column parallel to the first direction, the gate layer being arranged opposite to the channel region;

[0038] A first isolation structure is located between the semiconductor pillars adjacent to each other in the second direction, wherein the first isolation structure includes an air gap.

[0039] In some embodiments, the gate layer has a top and a bottom that are oppositely disposed along the vertical direction;

[0040] Wherein, a first dimension of the top of the gate layer in the first direction is equal to a second dimension of the bottom of the gate layer in the first direction.

[0041] In some embodiments, the first isolation structure is made of a single material.

[0042] In some embodiments, a material of the first isolation structure is one of silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide.

[0043] In some embodiments, the air gap is located at one side of the gate layer along the vertical direction.

[0044] According to a third aspect of the present disclosure, a memory system is provided, the memory system comprising:

[0045] One or more semiconductor devices according to the third aspect of the present disclosure;

[0046] A memory controller is coupled to the semiconductor device and configured to control the semiconductor device.

[0047] In the manufacturing method of the semiconductor device provided by the embodiment of the present disclosure, a gate material layer is first formed on the substrate surface, the sidewall and the bottom of the first trench, and then a barrier layer is formed on the surface of the gate material layer located on the sidewall of the first trench, and then the gate material layer is etched. During the etching process, the exposed gate material layer located on the substrate surface and the bottom of the first trench is etched first, so that the upper and lower ends of the gate material layer located between the sidewall of the first trench and the barrier layer are exposed, and then the gate material layer located before the sidewall of the first trench and the barrier layer is partially etched from the upper and lower ends, and the remaining gate material layer located between the sidewall of the first trench and the barrier layer forms a gate layer. In the manufacturing method provided by the embodiment of the present disclosure, only one step of etching is required to form the gate layer, and the position of the top and bottom of the gate layer can be controlled by controlling the etching time. In the formation process of the entire gate layer, there are fewer process steps, which can shorten the process cycle and reduce costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figures 1a to 1k A schematic diagram of the structure of a semiconductor structure during the manufacturing process provided by an embodiment of the present disclosure;

[0049] Figure 2A schematic flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present disclosure;

[0050] Figure 3a to Figure 3o A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present disclosure;

[0051] Figure 4 A schematic diagram of the structure of a memory provided by an embodiment of the present disclosure;

[0052] Figure 5 A schematic diagram of the structure of a memory system provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0053] The technical solution of the present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments.

[0054] It should be understood that spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0055] The terminology used herein is intended only to describe specific embodiments and is not intended to be limiting of the present disclosure. The terms "consisting of" and / or "comprising", when used in this specification, identify the presence of features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0056] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0057] DRAM is a semiconductor memory that can write and read data at high speed and randomly, and is widely used in data storage devices or apparatuses. The storage unit of DRAM can include a transistor and a capacitor. The drain of the transistor is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line (also known as the gate) can control the opening or closing of the transistor, and then read the data in the capacitor through the bit line, or write the data into the capacitor through the bit line for storage. The capacitor represents the data "1" or "0" by the amount of stored charge.

[0058] In some embodiments, the manufacturing process of the transistor array can refer to Figures 1a to 1e .like Figure 1a As shown, a substrate 10 is provided, the substrate 10 includes a plurality of semiconductor pillars 11 arranged in an array along a first direction and a second direction intersecting each other, a groove 20 extending along the first direction is formed in the substrate, and the groove 20 is located between adjacent semiconductor pillars 11. In the present disclosure, the first direction and the second direction are both parallel to the surface of the substrate, and by way of example, the first direction is the Y direction, and the second direction is the X direction.

[0059] like Figure 1b As shown, a first silicon oxide layer 31 is formed to cover the substrate surface, the sidewalls and the bottom of the trench 20 , and then a silicon nitride layer 32 is formed to cover the first silicon oxide layer 31 .

[0060] Then, if Figure 1c As shown, the second silicon oxide layer 33 is filled in the trench 20, and then the second silicon oxide layer 33 is etched back. The thickness of the remaining second silicon oxide layer 33 in this step depends on the bottom position of the designed gate layer, and it can also be understood that in this step, the thickness of the remaining second oxide layer 33 determines the bottom position of the gate layer to be formed subsequently.

[0061] Afterwards, if Figure 1d As shown, the first silicon oxide layer 31 and the silicon nitride layer 32 are etched until the top surfaces of the remaining first silicon oxide layer 31 and the silicon nitride layer 32 are flush with the top surface of the remaining second silicon oxide layer 33. In this step, the remaining first silicon oxide layer 31, the silicon nitride layer 32 and the second silicon oxide layer 33 form a lower isolation structure 30.

[0062] like Figure 1e As shown, a gate dielectric material layer 40 is formed in the trench 300 after the lower isolation structure 30 is formed. The gate dielectric material layer 40 covers the substrate surface, the sidewalls of the trench 20 and the top surface of the lower isolation structure 30 .

[0063] Then, if Figure 1fAs shown, a gate material layer 50 is formed covering the gate dielectric material layer 40, and the gate material layer 50 is also located on the substrate surface, the sidewalls of the trench 20 and the top surface of the lower isolation structure 30. In this embodiment, the gate material layer includes multiple sub-gate material layers stacked in sequence.

[0064] like Figure 1g As shown, at least a portion of the gate material layer located on the top surface of the lower isolation structure 30 is removed until the lower isolation structure 30 is exposed. At this time, the remaining gate material layer 50 is divided into two independent parts to form two gate layers isolated from each other. In the process of etching and removing the gate material layer on the top surface of the lower isolation structure 30, the gate material layer on the substrate surface is removed at the same time.

[0065] like Figure 1h and Figure 1i As shown, a third silicon oxide layer 60 is filled in the groove 20, and the third silicon oxide layer 60 is etched back. The remaining third silicon oxide layer 60 forms an intermediate isolation structure 61. The thickness of the intermediate isolation structure 61 depends on the top position of the designed gate layer. It can also be understood that the thickness of the intermediate isolation structure 61 formed in this step determines the position of the top of the gate layer formed subsequently.

[0066] like Figure 1j As shown, the gate material layer is etched back until the top surface of the remaining gate material layer is flush with the top surface of the intermediate isolation structure 61, and the remaining gate material layer forms two gate layers 51. Figure 1j As shown, each gate layer 51 is roughly "L" shaped, including a main body 51-a extending in a vertical direction (Z direction) and a protrusion 51-b extending in a direction parallel to the substrate surface. The two gate layers 51 located in the same groove can be mirror-symmetrical along a plane perpendicular to the second direction (X direction).

[0067] like Figure 1k As shown, the remaining space in the first trench 300 is filled with the fourth silicon oxide layer and treated by a planarization process to form an upper isolation structure 70 . Figure 1k In the embodiment, the lower isolation structure 30 , the middle isolation structure 61 and the upper isolation structure 70 together form an isolation structure between adjacent gate layers.

[0068] Above Figures 1a to 1k In the manufacturing process of forming the gate layer shown in FIG, the top and bottom positions of the gate layer are determined by depositing silicon oxide multiple times and etching back the silicon oxide multiple times, and the gate material layer is also etched back twice to form the gate layer. That is, the process steps for forming the gate layer are more, resulting in a longer process cycle and higher costs, and as shown in FIG. Figure 1j As shown, the protrusion 51 - b will cause the distance between adjacent gate layers 51 to decrease and the coupling effect to increase, which is not conducive to improving the device performance.

[0069] In view of this, an embodiment of the present disclosure provides a method for manufacturing a gate layer, which can simplify the process steps. Figure 2 The present invention provides a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 2 As shown, the method for manufacturing the semiconductor device includes:

[0070] S100: providing a substrate; wherein the substrate comprises a plurality of semiconductor pillars arranged at intervals, a first trench extending along a first direction is formed in the substrate, and the first trench is located between adjacent semiconductor pillars; and the first direction is parallel to a surface of the substrate;

[0071] S200: forming a gate material layer on the substrate surface, the sidewall and the bottom of the first trench;

[0072] S300: forming a barrier layer on a surface of the gate material layer located on a sidewall of the first trench;

[0073] S400: etching the gate material layer based on the barrier layer; wherein the gate material layer located on the sidewall of the first trench and covered by the barrier layer is partially retained to form a gate layer.

[0074] Figure 3a to Figure 3o A schematic diagram of the structure of a semiconductor device in the manufacturing process provided by the embodiment of the present disclosure. Figure 2 , Figure 3a to Figure 3o The manufacturing method of the semiconductor device provided by the embodiment of the present disclosure is introduced in detail.

[0075] See also Figure 3a to Figure 3c , Figure 3a and Figure 3c is a schematic top view of a semiconductor structure without a stop layer, Figure 3c yes Figure 3b A partial cross-sectional view along line AA. Step S100 is performed to provide a substrate 1000, the substrate 1000 includes a plurality of semiconductor pillars 120 arranged in an array along a first direction and a second direction intersecting each other, and the plurality of semiconductor pillars 120 are arranged at intervals from each other. A first trench 200 extending along the first direction is formed in the substrate 1000, the first trench 200 is located between adjacent semiconductor pillars 120 and exposes the sidewall of each semiconductor pillar 120. The first direction is, for example, the Y direction, and the second direction is, for example, the X direction.

[0076] The base comprises a substrate, the substrate is partially etched to form a plurality of semiconductor pillars, and the first trench extends into the substrate along a vertical direction (Z direction) to expose the sidewalls of the semiconductor pillars.

[0077] In some embodiments, the first trench and the semiconductor pillar are formed simultaneously. Figure 3a to Figure 3c As shown, the step of forming a semiconductor column and a first trench in the substrate may specifically include:

[0078] A substrate 100 is provided, and then the substrate 100 is etched to form a plurality of second grooves arranged side by side along a first direction (Y direction); wherein the depth of the second grooves along the vertical direction is less than the thickness of the substrate, that is, the second grooves do not penetrate the substrate. Adjacent second grooves define active areas 110 in the substrate, and each active area 110 extends along a second direction (X direction).

[0079] Next, the second trench is filled to form a second isolation material layer 300. Figure 3a As shown, the second isolation material layers 300 and the active regions 110 are alternately arranged along the first direction (Y direction).

[0080] Afterwards, if Figure 3b and Figure 3c As shown, the substrate and the second isolation material layer are etched to form a plurality of first trenches 200 arranged side by side along the second direction (X direction) in the substrate; wherein the depth of the first trenches 200 along the vertical direction is less than the thickness of the substrate, and the first trenches do not penetrate the substrate. The first trenches 200 extend along the first direction (Y direction) and pass through the active area and the second isolation material layer, wherein the remaining active areas on both sides of the first trenches 200 form semiconductor pillars 120, and the first trenches 200 expose the sidewalls of the semiconductor pillars 120 parallel to the first direction (Y direction).

[0081] Multiple first trenches 200 pass through the active area so that the remaining active area forms multiple semiconductor pillars 120, and the remaining second isolation material layer forms a second isolation structure 310. The second isolation structure 310 and the semiconductor pillars 120 are alternately arranged along the first direction (Y direction). The second isolation structure 310 is used to isolate two adjacent semiconductor pillars 120 along the first direction.

[0082] In some embodiments, Figure 3c As shown, the base 1000 may further include a stop layer 400 located on the surface of the substrate 100. The stop layer 400 is used as a stop layer in the subsequent etching step or planarization process to protect the substrate surface. The first trench 200 and the second trench both penetrate the stop layer and extend into the substrate.

[0083] In some embodiments, the material of the substrate 100 may be silicon, germanium, silicon germanium semiconductor or silicon carbide, or may be silicon on insulator (SOI) or germanium on insulator (GOI), or may be other materials, such as III-V group compounds such as gallium arsenide. The material of the stop layer 400 includes but is not limited to silicon nitride, silicon oxynitride, etc.

[0084] In some embodiments, Figure 3cAs shown, the semiconductor column 120 includes a first source and drain region 121, a channel region 122, and a second source and drain region 123 sequentially arranged along the vertical direction (Z direction), the second source and drain region 123 is closer to the bottom of the first trench 200, and the first source and drain region 121 is closer to the stop layer 400. One of the first source and drain region 121 and the second source and drain region 123 is a source region, and the other is a drain region.

[0085] For example, the first source and drain regions 121 and the second source and drain regions 123 are formed by injecting N-type doping ions or P-type doping ions into the semiconductor column 120. The doping ions injected into the first source and drain regions 121 and the second source and drain regions 123 are of the same type, that is, both are N-type doped or P-type doped. In some embodiments, the channel region 122 can be an intrinsic semiconductor or a doped semiconductor. For example, P-type doping ions or N-type doping ions can be injected into the channel region 122 of the semiconductor column 120 to form the channel region 122. The doping ion type of the channel region 122 is different from that of the first source and drain region 121. If the first source and drain region 121 is P-type doped, the channel region 122 is N-type doped. Conversely, if the first source and drain region 121 is N-type doped, the channel region 122 is P-type doped.

[0086] In some embodiments, before etching the substrate, doping ions can be injected into the substrate to form a first source and drain layer, a channel layer, and a second source and drain layer arranged in sequence along the vertical direction; thereafter, the substrate is etched to form a plurality of semiconductor pillars 120, each semiconductor pillar 120 including a first source and drain region 121 corresponding to the first source and drain layer, a channel region 122 corresponding to the channel layer, and a second source and drain region 123 corresponding to the second source and drain layer.

[0087] In some other embodiments, after forming the semiconductor pillars 120 , doping ions may be implanted into all the semiconductor pillars 120 , so that each semiconductor pillar 120 includes a first source and drain region 121 , a channel region 122 , and a second source and drain region 123 .

[0088] See also Figure 3d , forming a gate dielectric material layer 500 covering the substrate surface, the sidewalls and the bottom of the first trench 200 .

[0089] The gate dielectric material layer 500 may include silicon oxide, silicon oxynitride or a high dielectric constant (High-K) material. The high dielectric constant material includes but is not limited to hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, zirconium oxide zirconium oxide silicon oxide, etc. The process of forming the gate dielectric material layer includes but is not limited to chemical vapor deposition, atomic layer deposition, thermal oxidation, etc.

[0090] See also Figure 3e, performing step S200 to form a gate material layer 600 on the surface of the substrate 1000 , the sidewalls and the bottom of the first trench 200 , wherein the gate material layer 600 covers the surface of the gate dielectric material layer 500 .

[0091] In some embodiments, Figure 3e As shown, the gate material layer 600 includes a first sub-gate material layer 601 and a second sub-gate material layer 602 stacked in sequence, and the first sub-gate material layer 601 is located between the gate dielectric material layer 500 and the second sub-gate material layer 602. The first sub-gate material layer 601 includes a metal nitride, and the metal nitride includes but is not limited to titanium nitride, tungsten nitride, tantalum nitride, etc. The second sub-gate material layer 602 includes a metal, and the metal includes but is not limited to tungsten, gold, silver, copper, aluminum, titanium, tantalum, etc. The metal nitride is used to prevent the metal from diffusing into the gate dielectric material layer 500.

[0092] See also Figure 3f to Figure 3h , perform step S300 to form a barrier layer 720 on the surface of the gate material layer 600 located on the sidewall of the first trench.

[0093] The step of forming a barrier layer may specifically include: forming a barrier material layer 700 on the surface of the substrate 1000, the sidewall and the bottom of the first trench 200, such as Figure 3f As shown, the barrier material layer 700 covers the surface of the gate material layer 600; then, as shown in Figure 3h As shown, the barrier material layer located on the surface of the substrate and the bottom of the first trench is removed, and the remaining gate material layer 700 located on the sidewall of the first trench 200 forms a barrier layer 720 .

[0094] In some embodiments, a dry etching process may be used to remove the barrier material layer located on the substrate surface and the bottom of the first groove. Specifically, the dry etching process is anisotropic, and when the plasma beam used in the dry etching process is injected into the substrate along a direction perpendicular to the substrate surface (Z direction), the barrier material layer located on the substrate surface and the bottom of the first groove is etched and removed, while the barrier material layer located on the side wall of the first groove is parallel to the plasma beam, and is thus etched a small amount or not etched, so that the barrier material layer located on the side wall of the first groove is retained to form a barrier layer.

[0095] In some other embodiments, Figure 3g and Figure 3h As shown, the method for removing the barrier material layer located on the surface of the substrate and the bottom of the first trench may further include:

[0096] Doping ions are implanted into the barrier material layer 700 located on the surface of the substrate 1000 and the bottom of the first trench 200 to form a doping region 710; wherein the doping region 710 has a first etching rate, and the region located on the sidewall of the first trench where the doping ions are not implanted has a second etching rate, and the first etching rate is greater than the second etching rate;

[0097] The blocking material layer is etched to remove the doped region 710 , and the remaining blocking material layer located on the sidewall of the first trench 200 forms a blocking layer 720 .

[0098] For example, Figure 3g As shown, the doping ion beam is injected into the barrier material layer along a direction perpendicular to the substrate surface (Z direction), wherein the barrier material layer located on the substrate surface and the bottom of the first trench is injected with doping ions due to being perpendicular to the doping ion beam, thereby forming a doped region 710. The barrier material layer 700 located on the sidewall of the first trench is parallel to the doping ion beam, so that a small amount of doping ions or substantially no doping ions enter. Affected by the doping ions, the first etching rate of the doped region 710 may be greater than the second etching rate of the barrier material layer 700 located on the sidewall of the first trench into which the doping ions are not injected. For example, the etching rate of doped polysilicon may be greater than the etching rate of non-doped polysilicon.

[0099] The blocking material layer is etched using a dry etching process or a wet etching process. Since there is a large etching selectivity ratio between the doped region 710 and the undoped blocking material layer 700 located on the sidewall of the first trench, that is, the first etching rate is greater than the second etching rate, the doped region 710 is etched away, while the undoped blocking material layer 700 located on the sidewall of the first trench is retained to form a blocking layer 720.

[0100] Compared with directly using a dry etching process to remove the blocking material layer on the substrate surface and the bottom of the first trench, in this embodiment, ion implantation can increase the etching selectivity of the doped region and the non-doped blocking material layer located on the side wall of the first trench, thereby reducing damage to the blocking layer 720 during the process of removing the doped region using a dry etching process.

[0101] In another embodiment provided by the present disclosure, Figure 3f The barrier material layer 700 formed in the embodiment has a first crystallinity, where the crystallinity represents the proportion of the crystalline phase in the material. Figure 3f The barrier material layer 700 formed in the process has a crystalline structure as a whole.

[0102] For example, a barrier material layer having a crystal structure (i.e., a crystalline barrier material layer) may be formed by chemical vapor deposition, atomic layer deposition, physical vapor deposition, or the like. In addition, a heat treatment process may be performed on the barrier material layer formed by deposition so that the barrier material layer has a better crystal structure. It should be understood that an amorphous barrier material layer may also be deposited and then converted into a crystalline barrier material layer by a heat treatment process.

[0103] The thermal treatment process includes but is not limited to a laser annealing process or a rapid thermal processing (RTP) process.

[0104] See also Figure 3g In the step of injecting doping ions into the barrier material layer located on the substrate surface and the bottom of the first trench 200, the crystallinity of the doped region 710 is reduced and has a second crystallinity less than the first crystallinity, and the doped region 710 having the second crystallinity has a first etching rate.

[0105] In some embodiments, during the step of injecting doping ions into the barrier material layer located on the substrate surface and the bottom of the first trench 200 , the doped region may be transformed from a crystalline structure to an amorphous structure, and the doped region having the amorphous structure has a first etching rate.

[0106] Compared with the etching selectivity ratio obtained simply due to the influence of doped ions, the transformation from the crystalline state to the amorphous state can obtain a larger etching selectivity ratio, which means that the first etching rate is much greater than the second etching rate.

[0107] Taking aluminum oxide as the barrier material layer as an example, amorphous aluminum oxide and crystalline aluminum oxide have a large etching selectivity ratio, which can be greater than or equal to 10. That is, during the etching process, the first etching rate of amorphous aluminum oxide (doped area) is 10 times or even greater than the second etching rate of crystalline aluminum oxide (non-doped barrier material layer). This means that during the etching process, after the doped area is removed, the non-doped barrier material layer located on the side wall of the first groove is almost not etched but is completely retained to form a barrier layer. The barrier layer obtained in this way is continuous and has few defects (the probability of small pores being locally etched in the barrier layer is small or basically no small pores will appear), and the thickness of the barrier layer is relatively uniform everywhere, so that when the gate material layer is subsequently etched, the barrier layer can better block the etching solution to prevent the etching solution from passing through the defects of the barrier layer and damaging the gate layer.

[0108] In some embodiments, the thickness of the barrier material layer 700 is greater than or equal to 1.5 nm, so as to ensure that the barrier material layer has good continuity, few defects, and uniform thickness, that is, the film morphology of the barrier material layer is good.

[0109] In some embodiments, the material of the barrier material layer 700 may include aluminum oxide, silicon, or other materials used in the semiconductor field that can be converted between crystalline and amorphous states. For example, when the width of the first trench 200 is small, the material of the barrier material layer may be aluminum oxide, and 1.5 nm aluminum oxide can have good deposition quality and good film morphology. Considering factors such as the width of the first trench, in this embodiment, the thickness of the aluminum oxide is: greater than or equal to 1.5 nm and less than or equal to 3.0 nm.

[0110] As another example, in some other embodiments, when the width of the first trench 200 is relatively large, the material of the barrier material layer may be aluminum oxide or polysilicon. The thickness of the polysilicon may be, for example, greater than or equal to 7 nm.

[0111] The present disclosure does not limit the type of doping ions, as long as the doping region 710 can be transformed from a crystalline structure to an amorphous structure. In some embodiments, the doping ions include, but are not limited to, carbon, nitrogen, boron, phosphorus, arsenic, and the like.

[0112] Continue to see Figure 3i , performing step S400 , etching the gate material layer 600 based on the barrier layer 720 , wherein the gate material layer 600 located on the sidewall of the first trench 200 and covered by the barrier layer 720 is partially retained to form a gate layer 610 .

[0113] For example, a wet etching process can be used to etch the gate material layer. Specifically, the etching solution used in the wet etching process first removes the exposed gate material layer 600 located on the surface of the substrate 1000 and the bottom of the first trench 200, so that the upper end surface and the lower end surface of the gate material layer 600 located on the side wall of the first trench are exposed. Afterwards, the gate material layer 600 located on the side wall of the first trench is etched from the upper end and the lower end at the same time by utilizing the isotropic characteristics of the etching solution, so that the upper part and the lower part of the gate material layer 600 located on the side wall of the first trench are removed, and the remaining middle part of the gate material layer 600 located on the side wall of the first trench forms the gate layer 610.

[0114] like Figure 3h and Figure 3i As shown, the upper part, the middle part and the lower part are arranged in sequence along the vertical direction, the upper part is opposite to the first source and drain region 121, the middle part is opposite to the channel region 122, the lower part is opposite to the second source and drain region 123, and the lower part is closer to the bottom of the first trench 200. In this step, the upper part and the lower part of the gate material layer 600 located on the sidewall of the first trench are removed, and the middle part is retained to form a gate layer 610 arranged opposite to the channel region 122.

[0115] In some embodiments, the positions of the top surface and the bottom surface of the gate layer 610 can be accurately controlled by controlling the etching time, so that the gate layer 610 is disposed opposite to the channel region 122 .

[0116] like Figure 3i As shown, the remaining first sub-gate material layer forms a first sub-gate layer 611, and the remaining second sub-gate material layer forms a second sub-gate layer 612. The gate layer 610 includes the first sub-gate layer 611 and the second sub-gate layer 612 sequentially stacked along the second direction (X direction).

[0117] See also Figure 3j , remove the barrier layer to reveal the gate layer 610. The gate layer 610 extends in the vertical direction (Z direction). The gate layer 610 has a top and a bottom that are arranged opposite to each other in the vertical direction, and the first dimension of the top of the gate layer in the second direction (X direction) is equal to the second dimension of the bottom of the gate layer in the second direction. That is, the gate layer is "I" shaped, the dimensions of the gate layer along the second direction are substantially equal, and the film thickness of the gate layer is uniform.

[0118] For example, the barrier layer may be removed by using a dry etching process or a wet etching process.

[0119] See also Figure 3k and Figure 3l , a first isolation structure 810 is formed in the first trench 200 .

[0120] Specifically, Figure 3k As shown, the first isolation material is filled in the first trench 200 until the first isolation material covers the surface of the substrate to form a first isolation material layer 800; Figure 3l As shown, the first isolation material layer is processed by a planarization process until the gate dielectric material layer is exposed; the first isolation material layer and the gate dielectric material layer are continuously planarized until the stop layer 400 is exposed, at which time, the top surfaces of the remaining first isolation material layer and the remaining gate dielectric material layer are flush with the top surface of the stop layer 400. The remaining first isolation material layer forms the first isolation structure 810, and the remaining gate dielectric material layer forms the gate dielectric layer 510.

[0121] For example, the planarization process includes a chemical mechanical polishing (CMP) process.

[0122] The material of the first isolation structure 810 may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide or other low-k materials. For example, after forming the gate layer, only the first isolation material is filled in the first trench, so that the first isolation structure 810 is formed of a single material.

[0123] In some embodiments, Figure 3l As shown, the first isolation structure includes an air gap 811. The air gap is formed when the first isolation materials located at the sidewalls of the first trenches contact each other during the deposition of the first isolation material in the first trench 200, and the first isolation material located at the bottom of the first trench has not grown up, forming a closed unfilled area, which is the air gap 811.

[0124] Figure 3k In the embodiment, the presence of the gate layer 610 makes the distance between the sidewalls of the middle section of the first trench 200 smaller than that of the lower section (the section near the bottom), and the first isolation material is easy to seal the middle section of the first trench 200 first, so that an air gap is formed in the lower section of the first trench 200. Figure 3k As shown, the air gap 811 is located on one side of the gate layer close to the bottom of the first trench 200. The dielectric constant of air is smaller than that of commonly used dielectric materials, so forming an air gap in the first isolation structure can further improve the isolation effect of the first isolation structure.

[0125] Figure 3m A schematic cross-sectional view of a semiconductor structure along an XY plane after forming a first isolation structure according to an embodiment of the present disclosure is shown in FIG. Figure 3m As shown, the substrate includes a plurality of semiconductor pillars 120 arranged in an array along an intersecting first direction (Y direction) and a second direction (X direction), wherein a second isolation structure 310 is provided between adjacent semiconductor pillars 120 in the first direction (Y direction), and the second isolation structure 310 and the semiconductor pillar 120 have the same size in the second direction (X direction). The gate layer 610 extends along the first direction and is located on the sidewalls of the semiconductor pillar 120 and the second isolation structure 310 parallel to the first direction, and the gate layer 610 is arranged opposite to the channel region through the gate dielectric layer.

[0126] A gate layer 610, a first isolation structure 810 and another gate layer 610 arranged side by side along the second direction are provided between adjacent semiconductor pillars 120 in the second direction. The two gate layers 610 are respectively located on opposite side walls of adjacent semiconductor pillars 120. The first isolation structure 810 is used to isolate the two gate layers 610, and is also used to isolate two adjacent semiconductor pillars 120 in the first direction.

[0127] In the manufacturing method of the semiconductor device provided in this embodiment, a gate material layer is first formed on the substrate surface, the sidewall and the bottom of the first trench, and then a barrier layer is formed on the surface of the gate material layer located on the sidewall of the first trench, and then the gate material layer is wet-etched. During the etching process, the exposed gate material layer located on the substrate surface and the bottom of the first trench is etched first, so that the upper end and the lower end of the gate material layer located between the sidewall of the first trench and the barrier layer are exposed, and then the gate material layer located before the sidewall of the first trench and the barrier layer is partially etched from the upper and lower ends, and the remaining gate material layer located between the sidewall of the first trench and the barrier layer forms a gate layer. After the gate layer is formed, the barrier layer is removed, and a first isolation structure is formed in the first trench.

[0128] In the manufacturing method provided in this embodiment, only one etching step is required to form the gate layer, and the top and bottom positions of the gate layer can be controlled by controlling the etching time. Figures 1a to 1k The manufacturing method of the gate layer shown in the present embodiment does not require multiple depositions of silicon oxide and back etching of silicon oxide to determine the top and bottom positions of the gate layer, and does not require multiple etchings of the gate material layer. That is, in the entire gate layer formation process, the process steps are few and the process is relatively simple, which can shorten the process cycle and reduce costs.

[0129] In some embodiments, Figure 3n and Figure 3o As shown, the substrate includes a first surface and a second surface arranged opposite to each other in a vertical direction, and the stop layer 400 is located on the first surface of the substrate. The method for manufacturing the semiconductor device also includes: thinning the second surface of the substrate until the first isolation structure 810 and the second isolation structure are exposed, at which time, the plurality of semiconductor pillars 120 are isolated from each other, and each semiconductor pillar 120 is used to form a transistor.

[0130] Afterwards, a plurality of bit lines 910 arranged side by side along the first direction (Y direction) are formed on the second surface of the thinned substrate, each bit line 910 extends along the second direction (X direction) and is connected to the second source and drain regions 123 of the plurality of semiconductor pillars 120 arranged at intervals along the second direction. In some embodiments, the bit line 910 may be directly contacted and connected to the second source and drain regions 123. In another embodiment, a bit line contact plug 920 may be further provided between the bit line 910 and the second source and drain region 123, and the bit line 910 and the second source and drain region 123 are electrically connected through the bit line contact plug 920.

[0131] In some embodiments, the manufacturing method of the semiconductor device also includes: forming a capacitor array on the first surface of the substrate, the capacitor array includes a plurality of capacitors arranged in an array, each capacitor is connected to a first source and drain region 121 of a semiconductor column 120, and each capacitor and the corresponding transistor constitute a storage unit.

[0132] The present disclosure also provides a semiconductor device, such as Figure 3n and Figure 3o As shown, the semiconductor body device includes:

[0133] The semiconductor layer includes a plurality of semiconductor columns 120 arranged in an array along a first direction (Y direction) and a second direction (X direction) intersecting each other, and the semiconductor columns 120 include a first source and drain region 121, a channel region 122, and a second source and drain region 123 sequentially arranged along a vertical direction (Z direction);

[0134] A gate layer 610 extending along the first direction and located on a sidewall of the semiconductor pillar 120 parallel to the first direction, the gate layer 610 being disposed opposite to the channel region 122;

[0135] The first isolation structure 810 is located between the semiconductor pillars 120 adjacent to each other in the second direction, wherein the first isolation structure 810 includes an air gap 811 .

[0136] In this embodiment, an air gap is provided in the first isolation structure. Since the dielectric constant of the air gap is smaller than the dielectric constant of a commonly used dielectric material, forming the air gap in the first isolation structure can enhance the isolation effect.

[0137] In some embodiments, the air gap 811 is located on one side of the gate layer 610 along the vertical direction.

[0138] In some embodiments, the gate layer 610 has a top and a bottom that are arranged opposite to each other in the vertical direction; wherein the first dimension of the top of the gate layer 610 in the first direction is equal to the second dimension of the bottom of the gate layer in the first direction. In this embodiment, the gate layer extends in the vertical direction and is in an "I" shape. The film thickness of the gate layer is uniform at all locations. The spacing between two adjacent gate layers in the second direction is equal everywhere. There is no protrusion that leads to enhanced coupling between adjacent gate layers, thus facilitating improved device performance.

[0139] In some embodiments, the first isolation structure 810 is made of a single material, including silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide or other low dielectric constant materials.

[0140] The above-mentioned semiconductor device has been described in detail in the manufacturing method of the semiconductor device, so it will not be repeated here.

[0141] In some embodiments, the semiconductor device may be a memory, and the memory may be, for example, a DRAM.

[0142] Figure 4 A schematic diagram of a memory structure provided by an embodiment of the present disclosure is shown in FIG. Figure 4As shown, in some embodiments, the memory includes: a first wafer W1 and a second wafer W2 connected to each other.

[0143] The first wafer W1 includes a memory cell array, which includes a semiconductor column array (i.e., a transistor array) as described in any of the above embodiments, and a capacitor array 930 located on one side of the semiconductor column array. The lower electrode plate of each capacitor in the capacitor array 930 is electrically connected to the first source and drain region of a semiconductor column 120, and the upper electrode plates of the capacitors are connected to each other, and can also be considered to be connected to a common wire 931.

[0144] The first wafer W1 further includes: a bit line 910 located on a side of the semiconductor pillar array away from the capacitor array 930, a conductive plug 940 leading out a common wire, an interconnection layer 950 and a first bonding layer 930. The interconnection layer 950 connects the bit line 910, the gate layer 610 and the conductive plug 940, and the interconnection layer 950 may include a metal wiring layer and a conductive hole. The first bonding layer 815 connects the interconnection layer 950 and includes a first pad exposed on the surface of the first wafer.

[0145] The second wafer W2 includes a peripheral circuit, which includes a MOS transistor 970, which may include a PMOS transistor and an NMOS transistor. Multiple MOS transistors 970 can form devices in peripheral circuits such as buffers, sense amplifiers, and word line drivers. The second wafer W2 also includes multiple peripheral contact plugs 980 that lead out the source, drain, and gate of the MOS transistor, a peripheral interconnect layer 990 that connects the multiple peripheral contact plugs, and a second bonding layer that connects the peripheral interconnect layer 990 and includes a second pad exposed on the surface of the second wafer.

[0146] For example, the first pad of the first wafer W1 and the second pad of the second wafer W2 are bonded to bond the first wafer and the second wafer to achieve circuit connection, and the peripheral circuit of the second wafer can control the memory cell array in the first wafer to access data.

[0147] The present disclosure also provides a memory system. Figure 5 As shown, the memory system 1 includes:

[0148] One or more semiconductor devices according to any one of the above embodiments;

[0149] The memory controller 2 is coupled to the semiconductor device and is configured to control the semiconductor device.

[0150] By way of example, the semiconductor device is a memory 3 .

[0151] The memory controller 2 may be coupled to the memory 3 and the host, and used to control the memory 3. Exemplarily, the memory controller 2 may be designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 31 may also be designed to operate in a high duty cycle environment, such as an SSD or an embedded Multi-Media Card (eMMC), and the SSD or eMMC may be used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc., as well as an enterprise storage array.

[0152] In some embodiments, the memory controller 2 and one or more memories 3 can be integrated into various types of storage devices, for example, included in the same package (for example, a Universal Flash Storage (UFS) package or an eMMC package). For example, the memory controller 2 and multiple memories 3 can be integrated in an SSD. The SSD may also include a non-volatile memory, which may include but is not limited to NAND Flash Memory, 3D NAND Flash Memory, NOR Flash Memory, Dynamic Random Access Memory (DRAM), Ferroelectric Random Access Memory (FRAM), Magnetic Random Access Memory (MRAM), Phase Change Random Access Memory (PCRAM), Resistive Random Access Memory (RRAM), Nano Random Access Memory (NRAM), etc.

[0153] The methods disclosed in the several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The above description is only a specific implementation method of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, which should be covered by the protection scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: A substrate is provided; wherein the substrate comprises a plurality of semiconductor pillars arranged at intervals, a first groove extending along a first direction is formed in the substrate, and the first groove is located between adjacent semiconductor pillars; and the first direction is parallel to the surface of the substrate; forming a gate material layer on the sidewall and bottom of the first trench; forming a barrier layer on a surface of the gate material layer located on a sidewall of the first trench; The gate material layer is etched based on the barrier layer; wherein the gate material layer located on the sidewall of the first trench and covered by the barrier layer is partially retained to form a gate layer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The forming of a barrier layer on the surface of the gate material layer located on the sidewall of the first trench comprises: forming a barrier material layer covering the gate material layer; Injecting doping ions into the barrier material layer located on the surface of the substrate and the bottom of the first trench to form a doping region; wherein the doping region has a first etching rate, and the region located on the sidewall of the first trench where the doping ions are not injected has a second etching rate, and the first etching rate is greater than the second etching rate; The barrier material layer is etched to remove the doped region, and the remaining barrier material layer located on the sidewall of the first trench forms the barrier layer.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The step of implanting doping ions into the barrier material layer located on the surface of the substrate and the bottom of the first trench comprises: The doping ion beam is implanted into the barrier material layer along a direction perpendicular to the surface of the substrate.

4. The method for manufacturing a semiconductor device according to claim 2, wherein: The barrier material layer has a crystalline structure; In the step of injecting doping ions into the barrier material layer located on the surface of the substrate and the bottom of the first trench, the doping region is transformed from the crystalline structure to the amorphous structure, and the doping region having the amorphous structure has the first etching rate.

5. The method for manufacturing a semiconductor device according to claim 4, wherein: The material of the barrier material layer includes aluminum oxide.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The thickness of the barrier material layer is greater than or equal to 1.5 nm.

7. The method for manufacturing a semiconductor device according to claim 2, wherein: The etching of the gate material layer based on the barrier layer comprises: The gate material layer is etched using an etching solution, the gate material layer located on the substrate surface and the bottom of the first trench is removed, and the upper and lower parts of the gate material layer located on the sidewalls of the first trench are removed, and the remaining middle part of the gate material layer located on the sidewalls of the first trench forms the gate layer; wherein the upper part, the middle part and the lower part are arranged in sequence along a direction perpendicular to the substrate surface.

8. The method for manufacturing a semiconductor device according to claim 1 or 7, characterized in that: The semiconductor column comprises a first source-drain region, a channel region, and a second source-drain region sequentially arranged in a direction perpendicular to the surface of the substrate; In the step of forming the gate layer, the gate layer and the channel region are arranged opposite to each other.

9. The method for manufacturing a semiconductor device according to claim 1, wherein: The manufacturing method further comprises: removing the barrier layer; A first isolation structure is formed in the first trench; wherein the first isolation structure includes an air gap.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The base comprises a substrate and a stop layer located on the surface of the substrate, the substrate comprises the semiconductor pillars, and the first trench penetrates the stop layer and extends between adjacent semiconductor pillars; The manufacturing method further comprises: Forming a gate dielectric material layer covering the stop layer, the sidewalls and the bottom of the first trench; wherein the gate material layer covers the surface of the gate dielectric material layer; The gate dielectric material layer is processed by a planarization process until the stop layer is exposed; and the remaining gate dielectric material layer forms a gate dielectric layer.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: The providing of a substrate comprises: providing a substrate; A second trench extending along a second direction is formed in the substrate, and a plurality of the second trenches are arranged side by side along the first direction; wherein adjacent second trenches define an active area in the substrate; and the second direction intersects the first direction; filling the second trench to form a second isolation material layer; The first trench extending along the first direction is formed in the substrate; wherein the first trench passes through the active area and the second isolation material layer, and the remaining active area forms the plurality of semiconductor pillars.

12. A semiconductor device, characterized in that: include: A semiconductor layer, comprising a plurality of semiconductor columns arranged in an array along a first direction and a second direction intersecting each other, wherein the semiconductor columns comprise a first source and drain region, a channel region, and a second source and drain region sequentially arranged along a vertical direction; the first direction and the second direction are parallel to the semiconductor layer, and the vertical direction is perpendicular to the semiconductor layer; a gate layer extending along the first direction and located on a side wall of the semiconductor column parallel to the first direction, the gate layer being arranged opposite to the channel region; A first isolation structure is located between the semiconductor pillars adjacent to each other in the second direction, wherein the first isolation structure includes an air gap.

13. The semiconductor device according to claim 12, characterized in that The gate layer has a top and a bottom that are arranged opposite to each other along the vertical direction; Wherein, a first dimension of the top of the gate layer in the first direction is equal to a second dimension of the bottom of the gate layer in the first direction.

14. The semiconductor device according to claim 12, wherein: The first isolation structure is made of a single material.

15. The semiconductor device according to claim 14, characterized in that The material of the first isolation structure is one of silicon oxide, silicon nitride, silicon oxynitride and silicon oxycarbide.

16. The semiconductor device according to claim 12, wherein: The air gap is located at one side of the gate layer along the vertical direction.

17. A memory system, characterized in that: The memory system comprises: A semiconductor device as claimed in any one of claims 12 to 16; A controller is coupled to the semiconductor device and is configured to control the semiconductor device.

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