Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and electronic equipment. The semiconductor device comprises a first fin structure, an isolation dielectric layer, an interlayer dielectric layer, a first electrode and a power supply through hole. The first electrode is electrically connected with the channel region of the first fin structure, the interlayer dielectric layer is located on one side of the first surface of the isolation dielectric layer, one part of the power supply through hole is located in the isolation dielectric layer, and the other part of the power supply through hole is located in the interlayer dielectric layer; the first end of the power supply through hole is electrically connected with the first electrode, and the second end is electrically connected with a back-side power distribution network. The power supply through hole comprises a first power supply through hole and a second power supply through hole which are connected with each other, the first power supply through hole is located on one side, deviating from the second surface of the isolation dielectric layer, of the second power supply through hole, and the aperture of the second power supply through hole is larger than that of the first power supply through hole. The size of the power supply through hole can be locally increased through the second power supply through hole, the overall resistance of the power supply through hole is reduced, the voltage drop of a power supply signal is reduced, and the performance of the semiconductor device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device, a manufacturing method thereof, and an electronic device. Background Art

[0002] With the continuous development of semiconductor technology, semiconductor devices are gradually developing towards higher device density, higher device performance, and lower manufacturing cost, so that semiconductor devices are gradually developing towards a three-dimensional structure. For example, semiconductor devices may include: fin field effect transistors (Fin FET) or all-around gate (GAA) transistors and other transistors with a three-dimensional structure.

[0003] The related art proposes a scheme of setting up a backside power delivery network (BSPDN) in an electronic device, in which the transistors in the semiconductor device are connected to the backside power delivery network on the back side through a buried power rail through hole (via to buried power rail, VBPR), thereby reducing the area of ​​the logic unit of the semiconductor device and improving the performance of the semiconductor device.

[0004] However, due to the small size of the buried power rail through hole, the resistance of the buried power rail through hole is large, which makes the voltage drop (IR drop) of the power signal large, affecting the performance of the semiconductor device. Summary of the invention

[0005] The embodiments of the present application provide a semiconductor device, a manufacturing method thereof, and an electronic device, which are used to reduce the overall resistance of a power via and improve the performance of the semiconductor device.

[0006] In the first aspect, an embodiment of the present application provides a semiconductor device. The semiconductor device in the embodiment of the present application may include: one or more fin structures, for example, the semiconductor device may include: a first fin structure and a second fin structure, and the number of fin structures in the semiconductor device may be set according to actual needs, which is not limited here. The semiconductor device in the embodiment of the present application may also include: an isolation dielectric layer and an interlayer dielectric layer, and the interlayer dielectric layer is located on one side of the first surface of the isolation dielectric layer. The isolation dielectric layer includes a first surface and a second surface arranged opposite to each other in the thickness direction. Each fin structure penetrates the isolation dielectric layer in the thickness direction, and the surface of one side of the fin structure is flush with the second surface of the isolation dielectric layer, and the other side protrudes from the first surface of the isolation dielectric layer. The isolation dielectric layer can play a supporting and insulating role. When the semiconductor device includes multiple fin structures, the isolation dielectric layer can also play a role in separating adjacent fin structures. The semiconductor device in the embodiment of the present application may include one or more transistors, and the number of transistors in the semiconductor device may be set according to actual needs, which is not limited here. Each transistor may include: a fin structure, a source and a drain electrically connected to the channel region of the fin structure, and a gate covering the channel region of the fin structure. By applying a gate voltage to the gate, the conduction or cutoff of the transistor can be controlled.

[0007] In a possible implementation, the channel region of the first fin structure has a first end face and a second end face arranged oppositely in a first direction (the first direction is parallel to the first surface of the isolation dielectric layer), the first electrode is in contact with the first end face, and the third electrode is in contact with the second end face. The first fin structure may include: a sub-fin portion and a device portion, the sub-fin portion is located inside the isolation dielectric layer, the device portion is located on the side of the sub-fin portion away from the isolation dielectric layer, and the channel region of the first fin structure is located in the device portion. The two end faces of the device portion arranged oppositely in the first direction may be the above-mentioned first end face and second end face, and the first electrode and the third electrode are specifically in contact with the end faces of the device portion. The sub-fin portion may play a role in supporting the device portion, so as to facilitate the gate to surround the device portion to realize a transistor with a three-dimensional structure. The sub-fin portion may include semiconductor materials such as Si and Ge. In some cases, in order to avoid short-circuiting the sub-fin portion with other conductive components, the sub-fin portion may also be set as an insulating material. The material of the sub-fin portion may be selected according to actual needs, and is not limited here. The specific structure of the second fin structure or other fin structures may be implemented with reference to the specific structure of the first fin structure, and the repeated parts will not be repeated.

[0008] In some embodiments of the present application, the semiconductor device may include a gate-all-around (GAA) transistor. Specifically, the device portion may include: a plurality of channel layers stacked together. For example, the device portion may include three channel layers, and the number of channel layers may be set according to actual needs. The semiconductor device may also include: a gate dielectric layer, the gate surrounds each channel layer through the gate dielectric layer, and the area of ​​each channel layer surrounded by the gate is the channel region of the fin structure. In this way, a three-dimensional structure in which the gate surrounds the channel layer can be formed, and the coverage area of ​​the channel region of the gate and the fin structure is large, which can increase the gate's control ability over the transistor and improve the performance of the semiconductor device. Exemplarily, the channel layer may be a nanosheet or a nanowire.

[0009] In some other embodiments of the present application, the semiconductor device may include a fin field effect transistor (Fin FET), specifically, the semiconductor device may further include: a gate dielectric layer, a gate surrounding the top surface of the device portion and two side surfaces connected to the top surface through the gate dielectric layer, the top surface being the surface of the device portion on the side of the back ion fin portion, and the area of ​​the device portion covered by the gate being the channel region of the fin structure. In this way, a three-dimensional structure in which the gate surrounds the channel region on three sides can be formed, and the coverage area of ​​the gate and the channel region of the fin structure is large, which can increase the gate's control ability over the transistor and improve the performance of the semiconductor device.

[0010] The semiconductor device provided in the embodiment of the present application can be powered by a backside power distribution network, and the semiconductor device in the embodiment of the present application can also include: a power supply through hole. A portion of the power supply through hole is located in the isolation dielectric layer, and the other portion is located in the interlayer dielectric layer. The first end of the power supply through hole is electrically connected to the first electrode, and the second end is used to be electrically connected to the backside power distribution network. The power supply through hole includes: a first power supply through hole and a second power supply through hole connected to each other, the first power supply through hole is located on the side of the second power supply through hole away from the second surface of the isolation dielectric layer, and the aperture of the second power supply through hole is larger than the aperture of the first power supply through hole. In the embodiment of the present application, the power supply through hole is formed by an etching process in the isolation dielectric layer and the interlayer dielectric layer, and a conductive material is filled in the through hole by a deposition process, that is, the power supply through hole includes a conductive material, which can play the role of electrical connection. The power supply through hole can include a metal material, and of course, the power supply through hole can also include other conductive materials, which are not limited here.

[0011] In the related art, the transistor in the semiconductor device is connected to the back side power distribution network on the back side through a buried power rail via (VBPR). Due to the limitations of the internal space and manufacturing process of the semiconductor device, the size of the buried power rail via is relatively small, resulting in a large resistance of the buried power rail via, which makes the voltage drop (IR drop) of the power signal relatively large, affecting the performance of the semiconductor device. In the semiconductor device provided in the embodiment of the present application, the transistor in the semiconductor device is connected to the back side power distribution network on the back side through a power via, and the power via includes a first power via and a second power via, and the aperture of the second power via is larger than the aperture of the first power via. Compared with the buried power rail via in the related art, in the embodiment of the present application, by setting the second power via, the size of the power via can be partially increased, the overall resistance of the power via can be reduced, and then the voltage drop of the power signal can be reduced, thereby improving the performance of the semiconductor device.

[0012] In a possible implementation, the first power via is located in the interlayer dielectric layer, a portion of the second power via is located in the isolation dielectric layer, and another portion is located in the interlayer dielectric layer. Alternatively, the first power via is located in the interlayer dielectric layer, and the second power via is located in the isolation dielectric layer. Alternatively, a portion of the first power via is located in the interlayer dielectric layer, another portion is located in the isolation dielectric layer, and the second power via is located in the isolation dielectric layer.

[0013] Further, the power supply via in the embodiment of the present application may be located between the first fin structure and the second fin structure, so that it is convenient to connect the power supply via to the back side power distribution network on the back side of the semiconductor device. The semiconductor device in the embodiment of the present application may also include: a first conductive connection portion and a second conductive connection portion. The first conductive connection portion is located on the side of the first electrode away from the isolation dielectric layer, and in the thickness direction of the isolation dielectric layer, the first conductive connection portion at least partially overlaps with the first electrode, and the first conductive connection portion at least partially overlaps with the power supply via. The power supply via is electrically connected to the first electrode through the first conductive connection portion. In the thickness direction of the isolation dielectric layer, the power supply via and the first electrode do not overlap each other, and the power supply via and the first electrode are both located on the side of the first conductive connection portion close to the isolation dielectric layer. The electrical connection between the power supply via and the first electrode can be achieved by setting the first conductive connection portion. In a specific implementation, the power supply via and the first conductive connection portion may include the same conductive material, for example, the power supply via and the first conductive connection portion may include the same conductive material, for example, both may include metal material or other conductive materials. In some cases, the power supply via and the first conductive connection portion may also include different conductive materials, which is not limited here.

[0014] The second conductive connection part is located on the side of the second electrode away from the isolation dielectric layer, and in the thickness direction of the isolation dielectric layer, the second conductive connection part overlaps with the second electrode at least partially, and the second conductive connection part is electrically connected to the second electrode, and the second electrode can be led out through the second conductive connection part. In a specific implementation, the first conductive connection part and the second conductive connection part may include the same conductive material, for example, both may include metal materials or other conductive materials. In some cases, the first conductive connection part and the second conductive connection part may also include different conductive materials, which are not limited here. The first conductive connection part and the second conductive connection part are insulated, that is, the second conductive connection part and the power supply through hole are also insulated. Specifically, an insulating spacer may be provided between the first conductive connection part and the second conductive connection part to prevent the first conductive connection part from short-circuiting with the second conductive connection part. The insulating spacer may be located on the side of the first power supply through hole close to the second conductive connection part, and the insulating spacer may be located on the side of the second power supply through hole close to the first conductive connection part, that is, the first power supply through hole and the insulating spacer are both located on the side of the second power supply through hole close to the first conductive connection part. This arrangement facilitates the separation of the second conductive connection part from the first conductive connection part and the power supply through hole.

[0015] In a possible implementation, the edge of the first power through hole close to the second conductive connection part is flush with the edge of the first conductive connection part close to the second conductive connection part. In this way, the aperture of the first power through hole can be made larger while ensuring the insulation between the first power through hole and the second conductive connection part, and in the manufacturing process, the first conductive connection part and the first power through hole can be formed by the same patterning process, so that the manufacturing process is simpler.

[0016] In practical applications, the semiconductor device may further include: an insulating layer covering a portion of the first electrode and a portion of the second electrode, the insulating layer being provided with openings at positions corresponding to the first electrode and the second electrode, so that the first electrode is connected to the first conductive connection portion, and the second electrode is connected to the second conductive connection portion. Before making the first conductive connection portion and the second conductive connection portion, the insulating layer covers the surfaces of the first electrode and the second electrode, so that the insulating layer can protect the first electrode and the second electrode and prevent the first electrode and the second electrode from being damaged during the manufacturing process such as etching. When making the first conductive connection portion and the second conductive connection portion, the insulating layer may be patterned so that at least a portion of the first electrode and at least a portion of the second electrode are exposed, so that the first conductive connection portion formed subsequently can be connected to the first electrode, and the second conductive connection portion can be connected to the second electrode.

[0017] In a specific implementation, an interconnection layer (not shown in the figure) may be further provided on the side of the first conductive connection portion away from the isolation dielectric layer, and the interconnection layer may include a plurality of conductive film layers and a plurality of insulating film layers. The transistor in the semiconductor device may lead the signal out from the front through the interconnection layer. In the embodiment of the present application, the transistor is connected to the back side power distribution network through the power via, and the power supply network does not need to occupy the space of the front interconnection layer, which can reduce the area of ​​the logic unit of the semiconductor device and improve the density of the semiconductor device. Moreover, the power via in the embodiment of the present application has a small resistance, which can reduce the voltage drop of the power signal and improve the performance of the semiconductor device.

[0018] In the embodiment of the present application, the power through hole can satisfy the following relationship:

[0019]

[0020] Among them, H1 is the distance between the edge of the second power through hole and the second conductive connection part in the direction from the first fin structure to the second fin structure, and H2 is the distance between the first conductive connection part and the second conductive connection part in the direction from the first fin structure to the second fin structure.

[0021] In the embodiment of the present application, the distance H1 is set to be smaller than the spacing H2, so that the aperture of the second power through hole is larger than the aperture of the first power through hole. The distance H1 is set to be greater than or equal to half of the spacing H2, so that a certain distance can be ensured between the second power through hole and the second conductive connection portion to prevent the second power through hole and the second conductive connection portion from being short-circuited. Of course, in the case where the insulation between the second power through hole and the second conductive connection portion can be ensured, the distance H1 can also be set to be smaller than half of the spacing H2. For example, the distance H1 can also be set to be approximately one-third or one-quarter of H2, etc., and can be set according to the internal space in the semiconductor device.

[0022] In some embodiments of the present application, the semiconductor device may further include: a semiconductor layer and a buried power rail (BPR), and the buried power rail may be arranged between the first fin structure and the second fin structure. The semiconductor layer is located on the second surface side of the isolation dielectric layer, the buried power rail is electrically connected to the power via, a portion of the buried power rail is located in the semiconductor layer, and another portion is located in the isolation dielectric layer, and the power via is electrically connected to the back-side power distribution network through the buried power rail, thereby connecting the transistor to the back-side power distribution network, and realizing power supply to the transistor from the back of the semiconductor device. In order to avoid short circuit between the buried power rail and the semiconductor layer, an insulating dielectric layer may be arranged between the buried power rail and the semiconductor layer.

[0023] In some embodiments of the present application, the semiconductor device may include: a substrate, which may include semiconductor materials such as Si and Ge. An etching barrier layer may be provided between the substrate and the semiconductor layer, and the etching barrier layer may include materials such as SiGe and SiO2. During the manufacturing process, each film layer in the semiconductor device may be manufactured on the substrate. After the film layers in the semiconductor device are manufactured, the front side of the semiconductor device may be fixed on a carrier. After that, the semiconductor device is turned over and the substrate is removed by a grinding process. That is to say, the semiconductor device in the embodiment of the present application may not be provided with a substrate. After removing the substrate, the back side of the semiconductor device may continue to be ground to remove the semiconductor layer and the embedded power rail on the second surface side of the isolation dielectric layer (or the semiconductor device itself is not provided with an embedded power rail). That is to say, the semiconductor device in the embodiment of the present application may not be provided with structures such as a substrate, a semiconductor layer and an embedded power rail.

[0024] In a second aspect, an embodiment of the present application further provides an electronic device, and the electronic device in the embodiment of the present application may include: any of the above-mentioned semiconductor devices and a back-side power distribution network, and the semiconductor device is electrically connected to the back-side power distribution network through a power through hole. Since the resistance of the power through hole in the above-mentioned semiconductor device is relatively small, the voltage drop of the power signal can be reduced, thereby making the performance of the semiconductor device better, and thus the performance of the electronic device including the above-mentioned semiconductor device is also better.

[0025] In a third aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device provided by an embodiment of the present application may include:

[0026] Step 1, provide a substrate, which may include semiconductor materials such as Si and Ge. A fin structure, an isolation dielectric layer, an interlayer dielectric layer and a source-drain electrode (i.e., a source or drain, such as a first electrode) are provided on the substrate. One or more fin structures may be provided on the substrate. For example, a first fin structure and a second fin structure may be provided on the substrate. The fin structure penetrates the isolation dielectric layer in the thickness direction and protrudes from the first surface of the isolation dielectric layer. The first surface is the surface of the isolation dielectric layer facing away from the substrate. The first electrode is electrically connected to the channel region of the first fin structure, and the interlayer dielectric layer is located on one side of the first surface of the isolation dielectric layer. Optionally, the isolation dielectric layer may include one or more of SiO2, SiON, and SiNx. The first electrode may include polysilicon material, or the first electrode may also include other conductive materials.

[0027] In a possible implementation, a semiconductor layer and an embedded power rail may be provided on the substrate, and the semiconductor layer is located between the substrate and the isolation dielectric layer. A portion of the embedded power rail is located in the semiconductor layer, and another portion is located in the isolation dielectric layer. The embedded power rail is used to be electrically connected to the backside power distribution network, so that the transistor is connected to the backside power distribution network to realize power supply to the transistor from the back side of the semiconductor device. In order to avoid short circuit between the embedded power rail and the semiconductor layer, an insulating dielectric layer may be provided between the embedded power rail and the semiconductor layer.

[0028] In a specific implementation, an etch barrier layer may be provided between the substrate and the semiconductor layer, the etch barrier layer may include materials such as SiGe, SiO2, etc., and the semiconductor layer may include semiconductor materials such as Si, Ge, SiGe or other III-V materials. In some cases, other composite layers may be included on the semiconductor layer, and the composite layers may include materials such as Si and SiGe.

[0029] In addition, an insulating layer may be provided on the substrate, and the insulating layer covers the surface of the source and drain electrodes (i.e., the source or drain, such as the first electrode), and the insulating layer may protect the source and drain electrodes and prevent the source and drain electrodes from being damaged during the manufacturing process such as etching. Similarly, in order to protect the embedded power rail, an insulating layer may also be provided on the surface of the embedded power rail.

[0030] Step 2: patterning the interlayer dielectric layer and the isolation dielectric layer to obtain a first through hole and a second through hole that are interconnected, wherein the first through hole is located in the interlayer dielectric layer, a portion of the second through hole is located in the interlayer dielectric layer, and another portion is located in the isolation dielectric layer, and the aperture of the first through hole is larger than the aperture of the second through hole.

[0031] In a possible implementation, the above step 2 may specifically include:

[0032] The interlayer dielectric layer is patterned to obtain a first through hole located in the interlayer dielectric layer. The position of the first through hole corresponds to the position of the first conductive connection portion to be formed. When the semiconductor device includes a first fin structure and a second fin structure, the position of the first through hole corresponds to the position of the first conductive connection portion and the second conductive connection portion to be formed. In the process of patterning the interlayer dielectric layer, for example, an etching process can be used, and the insulating layer can protect the first electrode and the second electrode to prevent the etching process from damaging the first electrode and the second electrode.

[0033] The interlayer dielectric layer and the isolation dielectric layer are patterned to obtain a second through hole, a portion of which is located in the isolation dielectric layer, and another portion of which is located in the interlayer dielectric layer. The position of the second through hole corresponds to the position of the power through hole to be formed, and the aperture of the second through hole is substantially consistent with the aperture of the second power through hole to be formed. When the semiconductor device includes a first fin structure and a second fin structure, the obtained second through hole is located between the first fin structure and the second fin structure. In the process of patterning the interlayer dielectric layer and the isolation dielectric layer, for example, an etching process can be used, and the insulating layer can protect the buried power rail to prevent the etching process from damaging the buried power rail.

[0034] Then, the insulating layer is patterned to expose at least part of the surface of the buried power rail, the first electrode and the second electrode, so as to facilitate the connection of the subsequently formed first conductive connection portion with the first electrode, the subsequently formed second conductive connection portion with the second electrode, and the subsequently formed power through hole with the buried power rail.

[0035] Step 3: Fill the first through hole and the second through hole with conductive material, and remove part of the conductive material in the first through hole and the second through hole to obtain a first conductive connection portion in the first through hole and a power through hole in the second through hole. The power through hole is electrically connected to the first electrode through the first conductive connection portion, and the power through hole includes: a first power through hole and a second power through hole connected to each other, the first power through hole is located on a side of the second power through hole away from the second surface of the isolation dielectric layer, and the aperture of the second power through hole is larger than the aperture of the first power through hole.

[0036] In a possible implementation, the above step three may specifically include:

[0037] Conductive material is filled in the first through hole and the second through hole, and the conductive material is patterned to obtain a third through hole. In a direction perpendicular to the surface of the substrate, the third through hole penetrates the first through hole and part of the second through hole, and the conductive material is divided into two parts by the third through hole, one part of which is the first conductive connection part and the power supply through hole connected to each other, and the other part is the second conductive connection part, and the second conductive connection part is electrically connected to the second electrode.

[0038] Afterwards, an insulating material is filled in the third through hole to insulate the first conductive connection portion from the second conductive connection portion.

[0039] After the film layers on the front side of the semiconductor device are made, the front side of the semiconductor device can be fixed on the carrier, and then the semiconductor device is turned over and the substrate is removed by a grinding process. That is to say, the semiconductor device in the embodiment of the present application may not be provided with a substrate. After removing the substrate, the back side of the semiconductor device may continue to be ground to remove the semiconductor layer and the embedded power rail on the second surface side of the isolation dielectric layer (or the semiconductor device itself is not provided with an embedded power rail). That is to say, the semiconductor device in the embodiment of the present application may not be provided with structures such as a substrate, a semiconductor layer, and an embedded power rail.

[0040] In the manufacturing method provided in the embodiment of the present application, the interlayer dielectric layer and the isolation dielectric layer are patterned to obtain a first through hole and a second through hole that are interconnected, and conductive material is filled in the first through hole and the second through hole, and part of the conductive material in the first through hole and the second through hole is removed, so that a power through hole with a larger local aperture can be obtained, thereby obtaining a power through hole with a smaller overall resistance, thereby reducing the voltage drop of the power signal and improving the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A schematic diagram of a top view of a semiconductor device provided in an embodiment of the present application;

[0042] Figure 2 for Figure 1 Schematic diagram of the cross section at the middle dashed line AA';

[0043] Figure 3 for Figure 1 Schematic diagram of the cross section at the middle dotted line BB';

[0044] Figure 4 for Figure 1 A schematic cross-sectional view at the middle dashed line CC';

[0045] Figure 5 for Figure 1 Another cross-sectional view at the middle dashed line CC';

[0046] Figure 6 for Figure 1 Another schematic cross-sectional view at the middle dashed line AA';

[0047] Figure 7 for Figure 1 Another schematic cross-sectional view at the middle dashed line AA';

[0048] Figure 8 for Figure 1 Another schematic cross-sectional view at the middle dashed line AA';

[0049] Fig. 9 for Figure 1Another schematic cross-sectional view at the middle dashed line AA';

[0050] Fig.10 for Figure 1 Another schematic cross-sectional view at the middle dashed line AA';

[0051] Fig.11 A flowchart of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0052] Figures 12 to 17 It is a structural schematic diagram corresponding to each step of the manufacturing method in the embodiment of the present application.

[0053] Reference numerals:

[0054] 10-substrate; 11-first fin structure; 111-sub-fin; 112-device; 12-second fin structure; 13-isolation dielectric layer; 14-interlayer dielectric layer; 15-gate; 16-power via; 17-semiconductor layer; 18-buried power rail; 19-insulating layer; 20-etching barrier; 21-first conductive connection; 22-second conductive connection; 23-insulating spacer; 31-gate dielectric layer; 32-inner sidewall; 33-bottom electrical isolation layer; 34-conductive material; M1-first surface; M2-second surface; V1-first power via; V2-second power via; S1-first electrode; S2-second electrode; D1-third electrode; D2-fourth electrode; Q1-first end surface; Q2-second end surface; T1-first via; T2-second via; T3-third via. DETAILED DESCRIPTION

[0055] In the backside power distribution network solution of the related art, the transistors in the semiconductor device are connected to the backside power distribution network on the back side through a buried power rail via (via to buried power rail, VBPR), so as to reduce the area of ​​the logic unit of the semiconductor device and improve the performance of the semiconductor device. However, due to the small size of the buried power rail via, the resistance of the buried power rail via is large, which makes the voltage drop (IR drop) of the power signal large, affecting the performance of the semiconductor device.

[0056] Based on this, in order to solve the problem in the related art that the voltage drop of the power signal is large due to the small size of the buried power rail through hole, which affects the performance of the semiconductor device, the embodiment of the present application provides a semiconductor device, a manufacturing method thereof and an electronic device. The semiconductor device in the embodiment of the present application may include a transistor with a three-dimensional structure, for example, the semiconductor device may include a fin field effect transistor (FinFET) or a gate-all-around (GAA) transistor, etc. The semiconductor device in the embodiment of the present application can be widely used in various electronic devices. For example, the semiconductor device in the embodiment of the present application can be applied to electronic devices such as smart phones, smart TVs, smart TV set-top boxes, smart watches, personal computers (PCs), wearable devices, and smart broadband. In some cases, the semiconductor device in the embodiment of the present application can also be applied to other electronic devices, which will not be listed one by one here.

[0057] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings.

[0058] It should be noted that the same reference numerals in the drawings of this application represent the same or similar structures, and thus their repeated description will be omitted. The words expressing positions and directions described in this application are all explained using the drawings as examples, but they can be changed as needed, and the changes are included in the protection scope of this application. The drawings of this application are only used to illustrate the relative position relationship and do not represent the true proportion.

[0059] Figure 1 A schematic diagram of a top view of a semiconductor device provided in an embodiment of the present application is shown in FIG. Figure 2 for Figure 1 Schematic diagram of the cross section at the dotted line AA', Figure 3 for Figure 1 Schematic diagram of the cross section at the dotted line BB', Figure 4 for Figure 1 The cross-sectional view at the middle dashed line CC', combined with Figures 1 to 4The semiconductor device in the embodiment of the present application may include: one or more fin structures, for example, the semiconductor device may include: a first fin structure 11 and a second fin structure 12, and the number of fin structures in the semiconductor device may be set according to actual needs, which is not limited here. The semiconductor device in the embodiment of the present application may also include: an isolation dielectric layer 13 and an interlayer dielectric layer 14, and the interlayer dielectric layer 14 is located on one side of the first surface M1 of the isolation dielectric layer 13. The isolation dielectric layer 13 includes a first surface M1 and a second surface M2 that are arranged opposite to each other in the thickness direction (such as the z direction in the figure). Each fin structure (such as the first fin structure 11 or the second fin structure 12) penetrates the isolation dielectric layer 13 in the thickness direction, and the surface of one side of the fin structure is flush with the second surface M2 of the isolation dielectric layer 13, and the other side protrudes from the first surface M1 of the isolation dielectric layer 13. The isolation dielectric layer 13 can play a supporting and insulating role. When the semiconductor device includes multiple fin structures, the isolation dielectric layer 13 can also play a role in separating adjacent fin structures.

[0060] The semiconductor device in the embodiment of the present application may include one or more transistors, for example Figure 1 In the example, a semiconductor device including two transistors is used for illustration, namely Figure 1 The left half is a transistor, and the right half is a transistor. The number of transistors in the semiconductor device can be set according to actual needs, and is not limited here. The semiconductor device in the embodiment of the present application may also include: a gate 15, and the conduction or cutoff of the transistor can be controlled by applying a gate voltage to the gate 15. Each transistor may include: a fin structure, a source and a drain electrically connected to the channel region of the fin structure, and a gate covering the channel region of the fin structure. For example, Figure 1 The transistor in the right half may include: a first fin structure 11, a first electrode S1, a third electrode D1 and a gate 15, wherein the first electrode S1 and the third electrode D1 are electrically connected to the channel region of the first fin structure 11. The first electrode S1 is the source of the transistor, and the third electrode D1 is the drain of the transistor; or, the first electrode S1 is the drain of the transistor, and the third electrode D1 is the source of the transistor. The first electrode S1 and the third electrode D1 may include polysilicon material or other conductive materials. Figure 1 In the example, the first electrode S1 (or the third electrode D1) is connected to the channel regions of two adjacent first fin structures 11. In a specific implementation, the first electrode S1 (or the third electrode D1) may also be connected to the channel regions of one, three or more first fin structures 11, which may be set according to actual needs. Figure 1The transistor in the left half may include: a second fin structure 12, a second electrode S2, a fourth electrode D2 and a gate 15, wherein the second electrode S2 and the fourth electrode D2 are electrically connected to the channel region of the second fin structure 12. The second electrode S2 is the source of the transistor, and the fourth electrode D2 is the drain of the transistor; or, the second electrode S2 is the drain of the transistor, and the fourth electrode D2 is the source of the transistor. The second electrode S2 and the fourth electrode D2 may include polysilicon material or other conductive materials. Figure 1 The example in which the second electrode S2 (or the fourth electrode D2) connects the channel regions of two adjacent second fin structures 12 is used for illustration. In a specific implementation, the second electrode S2 (or the fourth electrode D2) may also connect the channel regions of one, three or more second fin structures 12, which may be set according to actual needs.

[0061] Reference Figure 3 and Figure 4 , the channel region of the first fin structure 11 has a first end surface Q1 and a second end surface Q2 that are oppositely arranged in the y direction, the first electrode S1 is in contact with the first end surface Q1, and the third electrode D1 is in contact with the second end surface Q2. The first fin structure 11 may include: a sub-fin portion 111 and a device portion 112, the sub-fin portion 111 is located inside the isolation dielectric layer 13, the device portion 112 is located on the side of the sub-fin portion 111 away from the isolation dielectric layer 13, and the channel region of the first fin structure 11 is located in the device portion 112. The two end surfaces of the device portion 112 that are oppositely arranged in the y direction may be the first end surface Q1 and the second end surface Q2, and the first electrode S1 and the third electrode D1 are specifically in contact with the end surfaces of the device portion 112. The sub-fin portion 111 may play a role in supporting the device portion 112, so that the gate 15 surrounds the device portion 112 to realize a transistor with a three-dimensional structure. The sub-fin 111 may include semiconductor materials such as Si and Ge. In some cases, in order to avoid short circuit between the sub-fin 111 and other conductive components, the sub-fin 111 may also be set to an insulating material. The material of the sub-fin 111 may be selected according to actual needs and is not limited here. The specific structure of the second fin structure 12 or other fin structures may be implemented with reference to the specific structure of the first fin structure 11, and the repeated parts will not be repeated.

[0062] like Figure 3 As shown, in some embodiments of the present application, the semiconductor device may include a gate-all-around (GAA) transistor. Specifically, the device portion 112 may include: a plurality of channel layers W stacked together, Figure 3In the figure, the device part 112 includes three layers of channel layers W as an example for illustration, and the number of layers of the channel layer W can be set according to actual needs. The semiconductor device may also include: a gate dielectric layer 31, the gate 15 surrounds each channel layer W through the gate dielectric layer 31, and the area of ​​each channel layer W surrounded by the gate 15 is the channel region of the fin structure. In this way, a three-dimensional structure in which the gate 15 surrounds the channel layer W can be formed, and the coverage area of ​​the gate 15 and the channel region of the fin structure is large, which can increase the control ability of the gate 15 over the transistor and improve the performance of the semiconductor device. Exemplarily, the channel layer W can be a nanosheet or a nanowire. In a specific implementation, the above-mentioned semiconductor device may also include: an inner spacer 32, the inner spacer 32 may be located between adjacent channel layers W, or the inner spacer 32 may also be located between the first or last channel layer W and other film layers, and the inner spacer 32 may isolate the gate 15 from the source (or drain) to prevent the gate 15 from being short-circuited with the source (or drain). In addition, in order to improve the performance of the semiconductor device, a bottom dielectric isolation layer (BDI) 33 may be provided between the device portion 112 and the sub-fin portion 111. In a thickness direction perpendicular to the isolation dielectric layer 13, the gate 15 (or the device portion 112) and the bottom dielectric isolation layer 33 have an overlapping region. In this way, the leakage current of the transistor may be reduced by the isolation effect of the bottom dielectric isolation layer 33. The bottom dielectric isolation layer 33 may include materials such as SiO2, SiCN, SiON, and SiN.

[0063] Figure 5 for Figure 1 Another cross-sectional diagram at the dotted line CC' is shown in FIG. Figure 5 As shown, in some other embodiments of the present application, the semiconductor device may include a fin field effect transistor (Fin FET), specifically, the semiconductor device may further include: a gate dielectric layer 31, a gate 15 surrounding the top surface of the device portion 112 and two side surfaces connected to the top surface through the gate dielectric layer 31, the top surface is the surface of the device portion 112 on the side of the back ion fin portion 111, and the area of ​​the device portion 112 covered by the gate 15 is the channel region of the fin structure. In this way, a three-dimensional structure in which the gate 15 surrounds the channel region on three sides can be formed, and the coverage area of ​​the gate 15 and the channel region of the fin structure is large, which can increase the control ability of the gate 15 on the transistor and improve the performance of the semiconductor device.

[0064] The semiconductor device provided in the embodiment of the present application can be powered by a backside power distribution network, such as Figure 1 and Figure 2As shown, the semiconductor device in the embodiment of the present application may also include: a power supply through hole 16. A portion of the power supply through hole 16 is located in the isolation dielectric layer 13, and another portion is located in the interlayer dielectric layer 14. The first end of the power supply through hole 16 is electrically connected to the first electrode S1, and the second end is used to be electrically connected to the back side power distribution network. The power supply through hole 16 includes: a first power supply through hole V1 and a second power supply through hole V2 connected to each other, the first power supply through hole V1 is located on the side of the second power supply through hole V2 away from the second surface M2 of the isolation dielectric layer 13, and the aperture of the second power supply through hole V2 is larger than the aperture of the first power supply through hole V1. In the embodiment of the present application, the power supply through hole 16 is formed by an etching process in the isolation dielectric layer 13 and the interlayer dielectric layer 14, and a conductive material is filled in the through hole by a deposition process, that is, the power supply through hole 16 includes a conductive material, which can play the role of electrical connection. The power supply through hole 16 may include a metal material, and of course, the power supply through hole 16 may also include other conductive materials, which are not limited here.

[0065] In the related art, the transistor in the semiconductor device is connected to the back side power distribution network on the back side through the buried power rail via (VBPR). Due to the limitation of the internal space and manufacturing process of the semiconductor device, the size of the buried power rail via is small, resulting in a large resistance of the buried power rail via, which makes the voltage drop (IR drop) of the power signal large, affecting the performance of the semiconductor device. In the semiconductor device provided in the embodiment of the present application, the transistor in the semiconductor device is connected to the back side power distribution network on the back side through the power via 16, and the power via 16 includes a first power via V1 and a second power via V2, and the aperture of the second power via V2 is larger than the aperture of the first power via V1. Compared with the buried power rail via in the related art, in the embodiment of the present application, by setting the second power via V2, the size of the power via 16 can be partially increased, the overall resistance of the power via is reduced, and then the voltage drop of the power signal is reduced, thereby improving the performance of the semiconductor device.

[0066] like Figure 2 As shown, in a possible implementation, the first power via V1 is located in the interlayer dielectric layer 14, a portion of the second power via V2 is located in the isolation dielectric layer 13, and another portion is located in the interlayer dielectric layer 14. Alternatively, referring to Figure 6 , Figure 6 for Figure 1 Another cross-sectional schematic diagram at the dotted line AA', in another possible implementation, the first power via V1 is located in the interlayer dielectric layer 14, and the second power via V2 is located in the isolation dielectric layer 13. Alternatively, refer to Figure 7 , Figure 7 for Figure 1Another cross-sectional schematic diagram at the middle dotted line AA′, in another possible implementation, a portion of the first power via V1 is located in the interlayer dielectric layer 14 , another portion is located in the isolation dielectric layer 13 , and the second power via V2 is located in the isolation dielectric layer 13 .

[0067] Furthermore, if Figure 2 As shown, the power supply via 16 in the embodiment of the present application can be located between the first fin structure 11 and the second fin structure 12, so that it is convenient to connect the power supply via 16 to the back side power distribution network on the back side of the semiconductor device. The semiconductor device in the embodiment of the present application may also include: a first conductive connection portion 21 and a second conductive connection portion 22. The first conductive connection portion 21 is located on the side of the first electrode S1 away from the isolation dielectric layer 13, and in the thickness direction of the isolation dielectric layer 13, the first conductive connection portion 21 at least partially overlaps with the first electrode S1, and the first conductive connection portion 21 at least partially overlaps with the power supply via 16. The power supply via 16 is electrically connected to the first electrode S1 through the first conductive connection portion 21. In the thickness direction of the isolation dielectric layer 13, the power supply via 16 and the first electrode S1 do not overlap each other, and the power supply via 16 and the first electrode S1 are both located on the side of the first conductive connection portion 21 close to the isolation dielectric layer 13. The electrical connection between the power supply via 16 and the first electrode S1 can be achieved by providing the first conductive connection portion 21. In a specific implementation, the power through hole 16 and the first conductive connection part 21 may include the same conductive material. For example, the power through hole 16 and the first conductive connection part 21 may include the same conductive material, for example, both may include metal material or other conductive materials. In some cases, the power through hole 16 and the first conductive connection part 21 may also include different conductive materials, which is not limited here.

[0068] The second conductive connection part 22 is located on the side of the second electrode S2 away from the isolation dielectric layer 13, and in the thickness direction of the isolation dielectric layer 13, the second conductive connection part 22 at least partially overlaps with the second electrode S2, and the second conductive connection part 22 is electrically connected to the second electrode S2, and the second electrode S2 can be led out through the second conductive connection part 22. In a specific implementation, the first conductive connection part 21 and the second conductive connection part 22 may include the same conductive material, for example, both may include metal materials or other conductive materials. In some cases, the first conductive connection part 21 and the second conductive connection part 22 may also include different conductive materials, which is not limited here. The first conductive connection part 21 and the second conductive connection part 22 are insulated, that is, the second conductive connection part 22 and the power supply through hole 16 are also insulated. Specifically, an insulating spacer 23 may be provided between the first conductive connection part 21 and the second conductive connection part 22 to prevent the first conductive connection part 21 and the second conductive connection part 22 from short-circuiting. The insulating spacer 23 may be located on a side of the first power via V1 close to the second conductive connection portion 22, and the insulating spacer 23 may be located on a side of the second power via V2 close to the first conductive connection portion 21, that is, the first power via V1 and the insulating spacer 23 are both located on a side of the second power via V2 close to the first conductive connection portion 21. This arrangement facilitates separating the second conductive connection portion 22 from the first conductive connection portion 21 and the power via 16.

[0069] Continue to refer to Figure 2 In a possible implementation, the edge of the first power through hole V1 close to the second conductive connection part 22 is flush with the edge of the first conductive connection part 21 close to the second conductive connection part 22. In this way, the aperture of the first power through hole V1 can be made larger while ensuring the insulation between the first power through hole V1 and the second conductive connection part 22. In addition, during the manufacturing process, the first conductive connection part 21 and the first power through hole V1 can be formed by the same patterning process, so that the manufacturing process is simpler.

[0070] In practical applications, the semiconductor device may further include: an insulating layer 19 covering a portion of the first electrode S1 and a portion of the second electrode S2, wherein the insulating layer 19 is provided with openings at positions corresponding to the first electrode S1 and the second electrode S2, so that the first electrode S1 is connected to the first conductive connection portion 21, and the second electrode S2 is connected to the second conductive connection portion 22. Before the first conductive connection portion 21 and the second conductive connection portion 22 are manufactured, the insulating layer 19 covers the surfaces of the first electrode S1 and the second electrode S2, so that the insulating layer 19 can protect the first electrode S1 and the second electrode S2, and prevent the first electrode S1 and the second electrode S2 from being damaged during the manufacturing process such as etching. When manufacturing the first conductive connection portion 21 and the second conductive connection portion 22, the insulating layer 19 may be patterned so that at least a portion of the first electrode S1 and at least a portion of the second electrode S2 are exposed, so that the first conductive connection portion 21 formed subsequently can be connected to the first electrode S1, and the second conductive connection portion 22 can be connected to the second electrode S2.

[0071] In a specific implementation, an interconnection layer (not shown in the figure) may also be provided on the side of the first conductive connection portion 21 away from the isolation dielectric layer 13, and the interconnection layer may include a plurality of conductive film layers and a plurality of insulating film layers. The transistor in the semiconductor device may lead the signal from the front through the interconnection layer. In the embodiment of the present application, the transistor is connected to the back side power distribution network through the power via 16, and the power supply network does not need to occupy the space of the front interconnection layer, which can reduce the area of ​​the logic unit of the semiconductor device and improve the density of the semiconductor device. In addition, the power via in the embodiment of the present application has a small resistance, which can reduce the voltage drop of the power signal and improve the performance of the semiconductor device.

[0072] Figure 8 for Figure 1 Another cross-sectional diagram at the dotted line AA' is shown in FIG. Figure 8 As shown, in the embodiment of the present application, the power through hole 16 can satisfy the following relationship:

[0073]

[0074] Among them, H1 is the distance between the edge of the second power through hole V2 and the second conductive connection part 22 in the direction from the first fin structure 11 to the second fin structure 12 (the opposite direction of x in the figure), and H2 is the distance between the first conductive connection part 21 and the second conductive connection part 22 in the direction from the first fin structure to the second fin structure.

[0075] In the embodiment of the present application, the distance H1 is set to be smaller than the spacing H2, so that the aperture of the second power through hole V2 can be larger than the aperture of the first power through hole V1. The distance H1 is set to be greater than or equal to half of the spacing H2, so that a certain distance can be ensured between the second power through hole V2 and the second conductive connection part 22, so as to prevent the second power through hole V2 from being short-circuited with the second conductive connection part 22. Of course, in the case where the insulation between the second power through hole V2 and the second conductive connection part 22 can be ensured, the distance H1 can also be set to be smaller than half of the spacing H2, for example, the distance H1 can also be set to be about one third or one quarter of H2, etc., which can be set according to the internal space in the semiconductor device.

[0076] like Figure 2 As shown, in some embodiments of the present application, the semiconductor device may further include: a semiconductor layer 17 and a buried power rail (BPR) 18, and the buried power rail 18 may be disposed between the first fin structure 11 and the second fin structure 12. The semiconductor layer 17 is located on the second surface M2 side of the isolation dielectric layer 13, the buried power rail 18 is electrically connected to the power via 16, a portion of the buried power rail 18 is located in the semiconductor layer 17, and another portion is located in the isolation dielectric layer 13, and the power via 16 is electrically connected to the back-side power distribution network through the buried power rail 18, thereby connecting the transistor to the back-side power distribution network, and realizing power supply to the transistor from the back of the semiconductor device. In order to avoid short circuit between the buried power rail 18 and the semiconductor layer 17, an insulating dielectric layer may be disposed between the buried power rail 18 and the semiconductor layer 17.

[0077] Fig. 9 for Figure 1 Another cross-sectional diagram at the dotted line AA' is shown in FIG. Fig. 9 As shown, in some embodiments of the present application, the semiconductor device may include: a substrate 10, and the substrate 10 may include semiconductor materials such as Si and Ge. An etching stopper layer 20 may be provided between the substrate 10 and the semiconductor layer 17, and the etching stopper layer 20 may include materials such as SiGe and SiO2. During the manufacturing process, each film layer in the semiconductor device may be manufactured on the substrate 10. After the film layers in the semiconductor device are manufactured, the front side of the semiconductor device may be fixed on a carrier. After that, the semiconductor device may be turned over and the substrate 10 may be removed by a grinding process. That is to say, Figure 2 As shown, the semiconductor device in the embodiment of the present application may not be provided with the substrate 10. Fig.10 , Fig.10 for Figure 1Another cross-sectional schematic diagram at the middle dotted line AA' shows that after removing the substrate, the back side of the semiconductor device can continue to be ground to remove the semiconductor layer and the embedded power rail on the side of the second surface M2 of the isolation dielectric layer 13 (or the semiconductor device itself is not provided with an embedded power rail). In other words, the semiconductor device in the embodiment of the present application may not be provided with structures such as a substrate, a semiconductor layer and an embedded power rail.

[0078] Based on the same technical concept, an embodiment of the present application also provides an electronic device, and the electronic device in the embodiment of the present application may include: any of the above-mentioned semiconductor devices and a back-side power distribution network, and the semiconductor device is electrically connected to the back-side power distribution network through a power through hole. Since the resistance of the power through hole in the above-mentioned semiconductor device is relatively small, the voltage drop of the power signal can be reduced, thereby making the performance of the semiconductor device better, and thus the performance of the electronic device including the above-mentioned semiconductor device is also better.

[0079] Based on the same technical concept, an embodiment of the present application provides a method for manufacturing a semiconductor device. Fig.11 A flowchart of a method for manufacturing a semiconductor device provided in an embodiment of the present application, Figures 12 to 17 It is a structural schematic diagram corresponding to each step of the manufacturing method in the embodiment of the present application.

[0080] Combination Figures 11 to 17 , the method for manufacturing a semiconductor device provided in an embodiment of the present application may include:

[0081] S101, reference Fig.12 , a substrate 10 is provided, and the substrate 10 may include semiconductor materials such as Si and Ge. A fin structure, an isolation dielectric layer 13, an interlayer dielectric layer 14 and a source-drain electrode (i.e., a source or a drain, such as a first electrode S1) are provided on the substrate 10. One or more fin structures may be provided on the substrate 10, for example, a first fin structure 11 and a second fin structure 12 may be provided on the substrate 10, and the fin structure penetrates the isolation dielectric layer 13 in the thickness direction and protrudes from the first surface M1 of the isolation dielectric layer 13, and the first surface M1 is the surface of the isolation dielectric layer 13 facing away from the substrate 10. The first electrode S1 is electrically connected to the channel region of the first fin structure 11, and the interlayer dielectric layer 14 is located on one side of the first surface M1 of the isolation dielectric layer 13. Optionally, the isolation dielectric layer 13 may include one or more of SiO2, SiON, and SiNx. The first electrode S1 may include a polysilicon material, or the first electrode S1 may also include other conductive materials.

[0082] In a possible implementation, a semiconductor layer 17 and an embedded power rail 18 may be further provided on the substrate 10, and the semiconductor layer 17 is located between the substrate 10 and the isolation dielectric layer 13. A portion of the embedded power rail 18 is located in the semiconductor layer 17, and another portion is located in the isolation dielectric layer 13. The embedded power rail 18 is used to be electrically connected to the backside power distribution network, so that the transistor is connected to the backside power distribution network to realize power supply to the transistor from the back side of the semiconductor device. In order to avoid short circuit between the embedded power rail 18 and the semiconductor layer 17, an insulating dielectric layer may be provided between the embedded power rail 18 and the semiconductor layer 17.

[0083] In a specific implementation, an etch stop layer 20 may be provided between the substrate 10 and the semiconductor layer 17. The etch stop layer 20 may include materials such as SiGe and SiO2. The semiconductor layer 17 may include semiconductor materials such as Si, Ge, SiGe or other III-V materials. In some cases, other composite layers (not shown in the figure) may be included on the semiconductor layer 17. The composite layers may include materials such as Si and SiGe.

[0084] In addition, an insulating layer 19 may be provided on the substrate 10, and the insulating layer 19 covers the surface of the source and drain electrodes (i.e., the source or drain, such as the first electrode S1), and the insulating layer 19 may protect the source and drain electrodes and prevent the source and drain electrodes from being damaged during the manufacturing process such as etching. Similarly, in order to protect the embedded power rail 18, an insulating layer 19 may also be provided on the surface of the embedded power rail 18.

[0085] S102. Reference Fig.13 and Fig.14 , the interlayer dielectric layer 14 and the isolation dielectric layer 13 are patterned to obtain a first through hole T1 and a second through hole T2 that are interconnected. The first through hole T1 is located in the interlayer dielectric layer 14, a portion of the second through hole T2 is located in the interlayer dielectric layer 14, and the other portion is located in the isolation dielectric layer 13, and the aperture of the first through hole T1 is larger than the aperture of the second through hole T2.

[0086] Reference Fig.13 , the interlayer dielectric layer 14 is patterned to obtain a first through hole T1 located in the interlayer dielectric layer 14. The position of the first through hole T1 corresponds to the position of the first conductive connection portion 21 to be formed. When the semiconductor device includes the first fin structure 11 and the second fin structure 12, the position of the first through hole T1 corresponds to the position of the first conductive connection portion 21 and the second conductive connection portion 22 to be formed. In the process of patterning the interlayer dielectric layer 14, for example, an etching process can be used, and the insulating layer 19 can protect the first electrode S1 and the second electrode S2 to prevent the etching process from damaging the first electrode S1 and the second electrode S2.

[0087] Reference Fig.14 , the interlayer dielectric layer 14 and the isolation dielectric layer 13 are patterned to obtain a second through hole T2, a portion of the second through hole T2 is located in the isolation dielectric layer 13, and the other portion is located in the interlayer dielectric layer 14. The position of the second through hole T2 corresponds to the position of the power through hole to be formed, and the aperture of the second through hole T2 is substantially consistent with the aperture of the second power through hole to be formed. When the semiconductor device includes a first fin structure 11 and a second fin structure 12, the obtained second through hole T2 is located between the first fin structure 11 and the second fin structure 12. In the process of patterning the interlayer dielectric layer 14 and the isolation dielectric layer 13, for example, an etching process can be used, and the insulating layer 19 can protect the buried power rail 18 to prevent the etching process from damaging the buried power rail 18.

[0088] Reference Fig.15 The insulating layer 19 is patterned to expose at least part of the surface of the buried power rail 18, the first electrode S1 and the second electrode S2, so as to facilitate the connection of the subsequently formed first conductive connection portion with the first electrode S1, the subsequently formed second conductive connection portion with the second electrode S2, and the subsequently formed power through hole with the buried power rail.

[0089] S103. Reference Fig.16 and Fig.17 , fill the first through hole T1 and the second through hole T2 with a conductive material 34, and remove part of the conductive material 34 in the first through hole T1 and the second through hole T2 to obtain Fig. 9 The structure shown in FIG. 1 is a first conductive connection portion 21 located in the first through hole T1 and a power through hole 16 located in the second through hole T2. The power through hole 16 is electrically connected to the first electrode S1 through the first conductive connection portion 21, and the power through hole 16 includes: a first power through hole V1 and a second power through hole V2 connected to each other, the first power through hole V1 is located on the side of the second power through hole V2 away from the second surface M2 of the isolation dielectric layer 13, and the aperture of the second power through hole V2 is larger than the aperture of the first power through hole V1.

[0090] Specifically, the above step S203 may specifically include:

[0091] Reference Fig.16 , the conductive material 34 is filled in the first through hole T1 and the second through hole T2. Fig.17, the conductive material 34 is patterned to obtain a third through hole T3. In a direction perpendicular to the surface of the substrate 10 (i.e., the z direction in the figure), the third through hole T3 penetrates the first through hole T1 and part of the second through hole T2, and the conductive material 34 is divided into two parts by the third through hole T3, one part (such as the right part of the conductive material 34 in the figure) is the first conductive connection part and the power through hole connected to each other, and the other part (such as the left part of the conductive material 34 in the figure) is the second conductive connection part, and the second conductive connection part is electrically connected to the second electrode.

[0092] Then, the third through hole T3 is filled with insulating material to obtain Fig. 9 Materials shown.

[0093] After the film layers on the front of the semiconductor device are completed, the front of the semiconductor device can be fixed on the carrier, and then the semiconductor device is turned over and the substrate is removed by a grinding process to obtain Figure 2 The structure shown in FIG. 1 is a semiconductor device in an embodiment of the present application that may not be provided with a substrate. After removing the substrate, the back side of the semiconductor device may be ground to remove the semiconductor layer and the embedded power rail on the second surface M2 side of the isolation dielectric layer 13 (or the semiconductor device itself is not provided with an embedded power rail) to obtain Fig.10 The structure shown, that is, the semiconductor device in the embodiment of the present application may not be provided with structures such as a substrate, a semiconductor layer and an embedded power rail.

[0094] In the manufacturing method provided in the embodiment of the present application, the interlayer dielectric layer and the isolation dielectric layer are patterned to obtain a first through hole and a second through hole that are interconnected, and conductive material is filled in the first through hole and the second through hole, and part of the conductive material in the first through hole and the second through hole is removed, so that a power through hole with a larger local aperture can be obtained, thereby obtaining a power through hole with a smaller overall resistance, thereby reducing the voltage drop of the power signal and improving the performance of the semiconductor device.

[0095] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0096] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A semiconductor device, characterized in that: include: A first fin structure, an isolation dielectric layer, an interlayer dielectric layer, a first electrode, and a power via; The isolation dielectric layer comprises a first surface and a second surface which are arranged opposite to each other in the thickness direction; the first fin structure penetrates the isolation dielectric layer in the thickness direction, and a surface on one side of the first fin structure is flush with the second surface of the isolation dielectric layer, and the other side protrudes from the first surface of the isolation dielectric layer; The first electrode is electrically connected to a channel region of the first fin structure; The interlayer dielectric layer is located on one side of the first surface of the isolation dielectric layer, a portion of the power through hole is located in the isolation dielectric layer, and another portion is located in the interlayer dielectric layer; a first end of the power through hole is electrically connected to the first electrode, and a second end is used to be electrically connected to a back-side power distribution network; The power through hole comprises: a first power through hole and a second power through hole connected to each other, the first power through hole is located on a side of the second power through hole away from the second surface of the isolation dielectric layer, and the aperture of the second power through hole is larger than that of the first power through hole.

2. The semiconductor device according to claim 1, wherein The first power supply via is located in the interlayer dielectric layer, a portion of the second power supply via is located in the isolation dielectric layer, and another portion of the second power supply via is located in the interlayer dielectric layer; Alternatively, the first power via is located in the interlayer dielectric layer, and the second power via is located in the isolation dielectric layer; Alternatively, a portion of the first power via is located in the interlayer dielectric layer, another portion is located in the isolation dielectric layer, and the second power via is located in the isolation dielectric layer.

3. The semiconductor device according to claim 1, wherein Also included: semiconductor layers and buried power rails; The semiconductor layer is located on one side of the second surface of the isolation dielectric layer, and the embedded power rail is electrically connected to the power through hole; A portion of the buried power rail is located in the semiconductor layer, and another portion is located in the isolation dielectric layer; The power via is electrically connected to the backside power distribution network through the embedded power rail.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that: Also includes: a second fin structure, a second electrode, a first conductive connection portion, and a second conductive connection portion; The second fin structure penetrates the isolation dielectric layer in the thickness direction, and a surface on one side of the second fin structure is flush with the second surface of the isolation dielectric layer, and the other side protrudes from the first surface of the isolation dielectric layer; The second electrode is electrically connected to the channel region of the second fin structure; The power through hole is located between the first fin structure and the second fin structure; The first conductive connection portion is located at a side of the first electrode away from the isolation dielectric layer, and in the thickness direction of the isolation dielectric layer, the first conductive connection portion at least partially overlaps with the first electrode, and the first conductive connection portion at least partially overlaps with the power through hole; the power through hole is electrically connected to the first electrode through the first conductive connection portion; The second conductive connection portion is located at a side of the second electrode away from the isolation dielectric layer, and in a thickness direction of the isolation dielectric layer, the second conductive connection portion at least partially overlaps with the second electrode, and the second conductive connection portion is electrically connected to the second electrode; The first conductive connection portion is insulated from the second conductive connection portion.

5. The semiconductor device according to claim 4, wherein: The power through hole satisfies the following relationship: Among them, H1 is the distance between the edge of the second power through hole and the second conductive connection part in the direction from the first fin structure to the second fin structure, and H2 is the distance between the first conductive connection part and the second conductive connection part in the direction from the first fin structure to the second fin structure.

6. The semiconductor device according to claim 4 or 5, characterized in that An edge of the first power through hole close to a side of the second conductive connecting portion is flush with an edge of the first conductive connecting portion close to a side of the second conductive connecting portion.

7. An electronic device, characterized in that: include: The semiconductor device and backside power distribution network according to any one of claims 1 to 6, wherein the semiconductor device is electrically connected to the backside power distribution network through a power through hole.

8. A method for manufacturing a semiconductor device, characterized in that: include: A substrate is provided; a first fin structure, an isolation dielectric layer, an interlayer dielectric layer and a first electrode are arranged on the substrate; The first fin structure penetrates the isolation dielectric layer in the thickness direction and protrudes from a first surface of the isolation dielectric layer; the first surface is a surface of the isolation dielectric layer facing away from the substrate; The first electrode is electrically connected to the channel region of the first fin structure, and the interlayer dielectric layer is located on one side of the first surface of the isolation dielectric layer; The interlayer dielectric layer and the isolation dielectric layer are patterned to obtain a first through hole and a second through hole that are interconnected; wherein the first through hole is located in the interlayer dielectric layer, a portion of the second through hole is located in the interlayer dielectric layer, and another portion is located in the isolation dielectric layer; and the aperture of the first through hole is larger than the aperture of the second through hole; Conductive material is filled in the first through hole and the second through hole, and part of the conductive material in the first through hole and the second through hole is removed to obtain a first conductive connection portion located in the first through hole and a power through hole located in the second through hole; the power through hole is electrically connected to the first electrode through the first conductive connection portion, and the power through hole includes: a first power through hole and a second power through hole connected to each other, the first power through hole is located on a side of the second power through hole away from the second surface of the isolation dielectric layer, and the aperture of the second power through hole is larger than the aperture of the first power through hole.

9. The method of claim 8, wherein: A second fin structure and a second electrode are also provided on the substrate; the second fin structure penetrates the isolation dielectric layer in the thickness direction and protrudes from the first surface of the isolation dielectric layer; the second electrode is electrically connected to the channel region of the second fin structure; The interlayer dielectric layer and the isolation dielectric layer are patterned, so that the second through hole obtained is located between the first fin structure and the second fin structure; The step of filling the first through hole and the second through hole with a conductive material, and removing a portion of the conductive material in the first through hole and the second through hole, specifically includes: Conductive material is filled in the first through hole and the second through hole, and the conductive material is patterned to obtain a third through hole; in a direction perpendicular to the surface of the substrate, the third through hole passes through the first through hole and part of the second through hole; the conductive material is divided into two parts by the third through hole, one part of which is the first conductive connection part and the power through hole connected to each other, and the other part is the second conductive connection part, and the second conductive connection part is electrically connected to the second electrode.

10. The production method according to claim 8 or 9, characterized in that: A semiconductor layer and an embedded power rail are also provided on the substrate; the semiconductor layer is located between the substrate and the isolation dielectric layer; a portion of the embedded power rail is located in the semiconductor layer, and another portion is located in the isolation dielectric layer; an insulating layer is provided on the surface of the embedded power rail, the first electrode and the second electrode facing away from the substrate; After patterning the interlayer dielectric layer and the isolation dielectric layer to obtain the first through hole and the second through hole that are interconnected, and before filling the first through hole and the second through hole with a conductive material, the method further includes: The insulating layer is patterned to expose at least portions of surfaces of the buried power rail, the first electrode, and the second electrode.

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