N-type TOPCon battery and preparation method thereof

Abstract

The invention provides an N-type TOPCon battery and a preparation method thereof. The method comprises the following steps: depositing a tunneling oxide layer and a Poly layer on the surface of a silicon wafer; performing phosphorus diffusion on the silicon wafer on which the tunneling oxide layer and the Poly layer are deposited, so that a phosphorus-doped Poly layer is formed on the back surface of the silicon wafer; and carrying out laser processing on the phosphorus-doped Poly layer in a non-grid line area on the back surface of the silicon wafer so as to remove the phosphorus-doped Poly layer in the non-grid line area. According to the preparation method of the N-type TOPCon battery provided by the invention, the phosphorus-doped polycrystalline silicon in the non-grid line region on the back surface of the silicon wafer is subjected to laser treatment, so that on one hand, the phosphorus-doped polycrystalline silicon in the non-grid line region on the back surface of the silicon wafer is removed, the light absorption efficiency of a long wave band is enhanced, and the conversion efficiency of the battery is improved; and on the other hand, through laser treatment, the phosphorus-doped polycrystalline silicon in the grid line region on the back surface of the silicon wafer is changed from disorder to order, so that the series resistance of the battery is reduced, and the short-circuit current of the battery is improved.

Description

Technical Field

[0001] The present invention relates to the field of solar cells, and in particular to an N-type TOPCon cell and a preparation method thereof. Background Art

[0002] The two development directions of crystalline silicon solar cells are to reduce costs and improve efficiency. The photovoltaic industry is highly competitive, and it is very difficult to continue to reduce costs, but there is still a lot of room for improving efficiency. TOPCon (Tunnel Oxide Passivated Contact) cells use a composite structure of back oxide layer + doped silicon to form a good passivation contact, which can improve the performance of the cell.

[0003] However, the performance of the N-type TOPCon battery prepared by the current preparation method still needs to be improved. Summary of the invention

[0004] The invention provides an N-type TOPCon battery and a preparation method thereof, and the method can improve the conversion efficiency of the TOPCon battery.

[0005] A method for preparing an N-type TOPCon battery, comprising:

[0006] S110: depositing a tunneling oxide layer and a Poly layer on the surface of the silicon wafer;

[0007] S120: diffusing phosphorus on the silicon wafer on which the tunnel oxide layer and the Poly layer are deposited, so that a phosphorus-doped Poly layer is formed on the back side of the silicon wafer;

[0008] S130: performing laser processing on the phosphorus-doped Poly layer in the non-gate line area on the back side of the silicon wafer to remove the phosphorus-doped Poly layer in the non-gate line area.

[0009] Specifically, in the process of laser processing the phosphorus-doped Poly layer in the non-gate line area on the back side of the silicon wafer, on the one hand, the phosphorus-doped polysilicon in the non-gate line area on the back side of the silicon wafer is removed, thereby enhancing the light absorption efficiency in the long-wave band and improving the conversion efficiency of the battery; on the other hand, in the process of laser processing, due to a certain temperature during laser processing, the polysilicon in the non-laser area will crystallize, so that part of the phosphorus element doped in the non-laser area will enter the polysilicon in the gate line area, so that the phosphorus-doped polysilicon in the gate line area will be more uniform and orderly than before laser processing, thereby reducing the series resistance of the battery and improving the short-circuit current of the battery.

[0010] Furthermore, in the method for preparing the N-type TOPCon battery as described above, the conditions for the laser treatment are: the laser wavelength is 500-600nm; the laser energy density is 250-350mJ / cm 2 .

[0011] Specifically, when the laser wavelength and energy density are too high, the poly structure will be destroyed, resulting in a decrease in the battery's electrical performance; when the laser wavelength and energy density are too low, the back PSG laser will not be removed cleanly, causing a decrease in the short-circuit current and a decrease in the battery's electrical performance.

[0012] Furthermore, the method for preparing the N-type TOPCon battery as described above, after S130, further includes:

[0013] S140: removing the PSG layer and the Poly layer on the front side of the silicon wafer;

[0014] S150: depositing an AlOx layer and an anti-reflection layer on the front side of the silicon wafer, and depositing an anti-reflection layer on the back side;

[0015] S160: Printing gate line electrodes on the surface of the silicon wafer by using steel plate printing.

[0016] Specifically, since it is difficult to reduce the width of the battery cells printed by the existing screen printing, if the screen line width becomes narrower (<10um), broken grids are likely to occur. However, the steel plate is different. It has the same screen parameters as the ordinary screen, but the battery cells produced have a better aspect ratio, a lower shading area, and a better short-circuit current.

[0017] Furthermore, the method for preparing the N-type TOPCon battery as described above, before step S110, further includes:

[0018] S101: Select an N-type single crystal silicon wafer as a substrate, perform double-sided texturing on the substrate, and form a pyramid-shaped anti-reflection texturing structure;

[0019] S102: Diffusing boron on the double-sided textured silicon wafer to form a boron-doped single crystal silicon layer;

[0020] S103: removing the boron-doped single crystal silicon layer and the BSG layer that are extended around the back and side surfaces of the N-type single crystal silicon wafer.

[0021] Furthermore, in the method for preparing the N-type TOPCon battery as described above, in S101, the double-sided texturing process includes:

[0022] The N-type monocrystalline silicon wafer is sequentially pre-cleaned, washed, texturized, washed, post-alkali washed, washed, pickled, washed, slowly pulled, and dried;

[0023] Among them, pre-cleaning pre-cleaning time: 100-200s, pre-cleaning temperature: 60-75℃;

[0024] Post-alkali washing time: 100-200s, post-alkali washing temperature: 60-75℃;

[0025] Pickling time is 100-200s;

[0026] Drying time: 600-700s, drying temperature: 90-100℃.

[0027] Further, in the method for preparing the N-type TOPCon battery as described above, in S102, the boron diffusion includes three steps: diffusion / deposition, anaerobic advancement, and aerobic advancement;

[0028] Among them, the diffusion / deposition temperature is 800-850°C; the anaerobic advancement temperature is 920-960°C; and the aerobic advancement temperature is 1000-1050°C.

[0029] Further, in the method for preparing the N-type TOPCon battery as described above, the S103 comprises:

[0030] The silicon wafers after boron diffusion are sequentially pre-cleaned, washed, alkaline polished, washed, post-alkaline washed, washed, acid washed, washed, slowly pulled, and dried;

[0031] Among them, pre-cleaning pre-cleaning time: 100-200s, pre-cleaning temperature: 60-70℃;

[0032] Alkali polishing time: 200-250s, alkali polishing temperature: 60-70℃;

[0033] Post-alkali washing time is 100-200s; post-alkali washing temperature is: 60-70℃;

[0034] Pickling time is 80-100s;

[0035] Drying time: 650-750s, drying temperature: 90-100℃;

[0036] In the S110, the thickness of the oxide layer is 1-2 nm, and the thickness of the poly layer is 115-125 nm.

[0037] Furthermore, in the method for preparing the N-type TOPCon battery as described above, in S120, the gas used for phosphorus diffusion is POCl 3 , O 2 、N 2 , POCl 3 , the gas flow rate is 2300sccm, the phosphorus doping temperature is 800-900℃, and the phosphorus doped polysilicon square resistance is 45-60Ω / □.

[0038] Further, in the method for preparing the N-type TOPCon battery as described above, in the S140, the silicon wafer after the laser treatment is sequentially subjected to the following steps: alkaline etching, water washing, alkaline washing I, water washing, acid washing I, water washing, alkaline washing II, water washing, acid washing II, water washing, slow pulling, and drying;

[0039] Among them, the alkali etching time is: 300-400s; the alkali etching temperature is: 60-70℃; the alkali washing I time is: 80-100s, and the alkali washing I temperature is: 60-70℃; the acid washing I time is: 110-230s; the alkali washing II time is: 80-100s, and the temperature is: 60-70℃; the acid washing II time is: 100-120s; the drying time is: 650-750s, and the drying temperature is: 90-100℃.

[0040] Specifically, the alkali etching time should not be too long or too short. This is because if the alkali etching time is too short, a crescent mark will be produced that cannot be effectively removed, resulting in failure of the cell photoluminescence test PL; and if the alkali etching time is too long, it will cause excessive corrosion of the silicon substrate, and the silicon substrate will become thinner, resulting in reduced absorption of light in the long-wave band and reduced electrical performance of the battery.

[0041] The present invention provides a method for preparing an N-type TOPCon battery, comprising the following steps:

[0042] S1: Select an N-type single crystal silicon wafer as a substrate, perform double-sided texturing on it, and form a pyramid-shaped anti-reflection textured surface structure;

[0043] S2: Diffusing boron on the double-sided textured silicon wafer to form a boron-doped single crystal silicon layer;

[0044] S3: removing the boron-doped single crystal silicon layer and the BSG layer that are extended around the back and side surfaces of the N-type single crystal silicon wafer;

[0045] S4: depositing a tunneling oxide layer and a Poly layer on the surface of the silicon wafer;

[0046] S5: diffusing phosphorus on the silicon wafer on which the tunnel oxide layer and the Poly layer are deposited, so that a phosphorus-doped Poly layer is formed on the back side of the silicon wafer;

[0047] S6: performing laser treatment on the phosphorus-doped Poly layer in the non-gate line area on the back side of the silicon wafer to remove the phosphorus-doped Poly layer in the non-gate line area;

[0048] S7: removing the PSG layer and the Poly layer on the front side of the silicon wafer;

[0049] S8: depositing an AlOx layer and an anti-reflection layer on the front side of the silicon wafer, and depositing an anti-reflection layer on the back side;

[0050] S9: Print the gate electrode on the surface of the silicon wafer by using steel plate printing.

[0051] The present invention also provides an N-type TOPCon battery prepared by any of the above methods.

[0052] The preparation method of the N-type TOPCon battery provided by the present invention performs laser processing on the phosphorus-doped polycrystalline silicon in the non-gate line area on the back side of the silicon wafer. On the one hand, the phosphorus-doped polycrystalline silicon in the non-gate line area on the back side of the silicon wafer is removed, thereby enhancing the light absorption efficiency in the long-wave band and improving the conversion efficiency of the battery; on the other hand, through the laser processing, the phosphorus-doped polycrystalline silicon in the gate line area on the back side of the silicon wafer is changed from disordered to ordered, thereby reducing the series resistance of the battery and improving the short-circuit current of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 The figure is a process flow chart of the preparation of the N-type TOPCon battery of the present invention;

[0054] Figure 2 This is a flow chart of the existing N-type TOPCon battery preparation process. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0056] The complete back Poly of TOPCon cells can block minority carriers from passing through, allow majority carriers to pass through, form an extremely high carrier concentration barrier, and enhance passivation and contact effects. However, the presence of phosphorus-doped polysilicon in the back non-grid area affects the light absorption in the long-wave band, thereby reducing the conversion efficiency of the cell. In order to improve the conversion efficiency of the cell, the present invention performs laser treatment on the silicon wafer that has been diffused with phosphorus, effectively improving the conversion efficiency and short-circuit current of the cell, while reducing the series resistance of the cell.

[0057] Embodiment 1:

[0058] This embodiment provides a preparation process of an N-type TOPCon battery. Figure 1 As shown, the following steps are included:

[0059] S1: Select an N-type single crystal silicon wafer as a substrate, and perform pre-cleaning, water washing, texturing, water washing, post-alkali washing, water washing, acid washing, water washing, slow pulling, and drying on the N-type single crystal silicon wafer in sequence; the specific cleaning process is shown in Table 1:

[0060]

[0061] S2: Boron diffusion is performed on the double-sided textured silicon wafer to form a boron-doped single crystal silicon layer

[0062] S3: Remove the boron-doped single crystal silicon layer and BSG layer on the back and side of the N-type single crystal silicon wafer; remove the BSG on the back by HF of the chain machine, and then use the trough type for alkaline polishing; the specific cleaning process is shown in Table 2:

[0063] Table 2

[0064]

[0065] S4: depositing a tunneling oxide layer and a Poly layer (intrinsic polysilicon layer) on the front and back sides of the silicon wafer;

[0066] S5: placing the silicon wafer into a phosphorus expansion tube, diffusing phosphorus on the back of the silicon wafer and annealing the back to form a phosphorus-doped Poly layer;

[0067] S6: laser treatment is performed on the phosphorus-doped Poly layer in the non-gate line area on the back of the silicon wafer to remove the phosphorus-doped Poly layer in the non-gate line area, wherein the laser wavelength is 550nm and the laser energy density is 300mJ / cm 2 ;

[0068] S7: Use a chain machine to perform single-sided HF cleaning on the silicon wafer to remove the PSG layer on the front side of the silicon wafer, and use a water film to protect the back side of the silicon wafer; then use a tank machine to perform alkali cleaning on the silicon wafer to remove the Poly layer on the front side;

[0069] The specific cleaning process is shown in Table 3:

[0070] Table 3

[0071]

[0072] The alkaline etching uses NaOH+ADD to remove excess poly on the front and edge of the silicon wafer;

[0073] Alkali cleaning I uses bubbling alkali cleaning to neutralize ADD; acid cleaning I uses HF to remove BSG and PSG on the surface of silicon wafers; alkaline cleaning II uses bubbling alkali cleaning to neutralize acid residues and remove organic matter; acid cleaning II is used to remove SiO 2 layer to form Si-H passivation bonds, making the silicon wafer hydrophobic and neutralizing alkali.

[0074] S8: depositing an AlOx layer on the front side of the silicon wafer;

[0075] S9: depositing an anti-reflection layer, i.e., a SiNx layer, on the front side of the silicon wafer;

[0076] S10: depositing an anti-reflection layer, i.e., a SiNx layer, on the back side of the silicon wafer;

[0077] 11: Screen-printing gate electrodes on the surface of the silicon wafer;

[0078] S12: Light-assisted micro-guiding of the front silver paddle.

[0079] Embodiment 2:

[0080] The difference between this embodiment and embodiment 1 is that:

[0081] In step S11, a gate electrode is printed on the surface of the silicon wafer by using a steel plate printing method.

[0082] Comparative Example 1:

[0083] The difference between this comparative example and Example 1 is that after step S5, the PSG layer and the Poly layer on the front side of the silicon wafer are directly removed without laser treatment. The specific preparation process flow is shown in Figure 2 .

[0084] Comparative Example 2:

[0085] The difference between this comparative example and comparative example 1 is that in step S11, a gate line electrode is printed on the surface of the silicon wafer by using a steel plate printing method.

[0086] When the gate electrode is printed on the surface of the silicon wafer in Embodiment 1 and Embodiment 2, the height-to-width ratio of the battery auxiliary grid is as shown in Table 4:

[0087] Table 4

[0088] high Width Aspect Ratio Example 1 8.51 16.67 51.05％ Example 2 10.57 15.58 67.84％

[0089] Embodiment 3:

[0090] The difference between this embodiment and embodiment 1 is that:

[0091] In step S6, the laser wavelength is 600nm; the laser energy density is 350mJ / cm 2 ;

[0092] In step S7, the alkali etching time is 300 s and the alkali etching temperature is 60°C.

[0093] Embodiment 4:

[0094] The difference between this embodiment and embodiment 1 is that:

[0095] In step S6, the laser wavelength is 500nm; the laser energy density is 250mJ / cm 2 ;

[0096] In step S7, the alkali etching time is 400 s and the alkali etching temperature is 60°C.

[0097] Embodiment 5:

[0098] The difference between this embodiment and embodiment 1 is that the laser wavelength is 610nm; the energy density of the laser is 360mJ / cm 2 .

[0099] Embodiment 6:

[0100] The difference between this embodiment and embodiment 1 is that the laser wavelength is 490nm; the energy density of the laser is 240mJ / cm 2 .

[0101] Embodiment 7:

[0102] The difference between this embodiment and embodiment 1 is that:

[0103] In step S7, the alkali etching time is 290 seconds and the alkali etching temperature is 60°C.

[0104] Embodiment 8:

[0105] The difference between this embodiment and embodiment 1 is that:

[0106] In step S7, the alkali etching time is 410 s and the alkali etching temperature is 60°C.

[0107] Experimental Example 1:

[0108] The N-type TOPCon batteries prepared in Example 1-2 and Comparative Example 1-2 were tested, and the test results are shown in Table 5:

[0109] Table 5 Battery performance parameters

[0110] Eta Uoc Isc FF RsDf RshuntDf Example 1 26.15 0.7314 14.046 85.20 0.001228 1923 Example 2 26.26 0.7303 14.011 85.90 0.001057 2840 Comparative Example 1 26.02 0.7312 13.988 85.14 0.001321 2902 Comparative Example 2 26.13 0.7322 13.989 85.40 0.001128 2125

[0111] It can be seen from Table 5 that the phosphorus-doped Poly layer in the non-gate line area on the back of the silicon wafer is laser-treated, so that the conversion efficiency of the battery is increased from 26.02% to 26.15%, an increase of 0.13%; the short-circuit current is increased from 13.988 to 14.046, an increase of 0.058; the series resistance of the battery is reduced from 0.001321 to 0.001228, a decrease of 0.000093. This is because through laser treatment, on the one hand, the phosphorus-doped polysilicon in the non-gate line area on the back of the silicon wafer is removed, thereby enhancing the light absorption efficiency in the long-wave band and improving the conversion efficiency of the battery; on the other hand, during the laser treatment process, due to a certain temperature during the laser treatment, the polysilicon in the non-laser area will crystallize, so that the phosphorus doped in the non-laser area will partially enter the polysilicon in the gate line area, so that the phosphorus-doped polysilicon in the gate line area will be more uniform and orderly than before the laser treatment, thereby reducing the series resistance of the battery and increasing the short-circuit current of the battery.

[0112] It can also be seen from Table 1 that the embodiment of the present invention uses steel plate printing to print the grid line electrode on the surface of the silicon wafer, so that the conversion efficiency of the battery is increased from 26.15% to 26.26%, an increase of 0.11%; the series resistance of the battery is reduced from 0.001228 to 0.001057, a decrease of 0.0001771. This is because the width of the battery cell printed by the existing screen is difficult to reduce. If the screen line width becomes narrower (<10um), it is easy to break the grid. However, the steel plate is different. With the same screen parameters as the ordinary screen, the battery cell produced has a better aspect ratio, a lower shading area, and a better short-circuit current.

[0113] Experimental Example 2:

[0114] The N-type TOPCon batteries prepared in Example 1, Example 3, Example 4, Example 5, and Example 6 were tested, and the test results are shown in Table 6:

[0115] Table 6 Battery performance parameters

[0116] Eta Uoc Isc FF RsDf IRev2 Example 1 26.151 0.7314 14.046 85.2 0.001228 0.02990 Example 3 26.145 0.7314 14.042 85.2 0.001200 0.06050 Example 4 26.148 0.7312 14.010 85.4 0.001230 0.08010 Example 5 26.141 0.7311 14.046 85.2 0.001240 0.07630 Example 6 26.146 0.7315 13.999 85.5 0.001069 0.02947

[0117] As can be seen from Table 2, by comparing Example 3 with Example 5, it is found that when the laser wavelength exceeds 600nm and the laser energy density exceeds 350mJ / cm 2 When the laser wavelength is less than 500nm and the laser energy density is less than 250mJ / cm 2 Therefore, only when the laser treatment conditions are controlled at: laser wavelength of 500-600nm; laser energy density of 250-350mJ / cm 2 This is because when the laser wavelength and energy density are too high, the poly structure will be destroyed, resulting in a decrease in the battery's electrical performance; and when the laser wavelength and energy density are too low, the PSG laser on the back side will not be removed cleanly, causing a decrease in the short-circuit current and a decrease in the battery's electrical performance.

[0118] Experimental Example 3:

[0119] The N-type TOPCon batteries prepared in Example 1, Example 3, Example 7, and Example 8 were tested, and the test results are shown in Table 7:

[0120] Table 7 Battery performance parameters

[0121] Eta Uoc Isc FF RsDf IRev2 Example 1 26.151 0.7314 14.046 85.2 0.001228 0.02990 Example 3 26.145 0.7314 14.042 85.2 0.001200 0.06050 Example 7 26.150 0.7312 14.015 85.4 0.001112 0.03817 Example 8 26.149 0.7303 13.983 85.7 0.001072 0.05382

[0122] As can be seen from Table 7, by comparing Example 3 with Example 7, it is found that reducing the alkali etching time from 350s to 300s has little effect on the battery electrical performance. X There is a problem of too thin expansion, which causes a crescent mark. If the alkali etching time is too short, the crescent mark cannot be eliminated, resulting in the inability to effectively test the battery cell later. Comparing Example 3 with Example 8, it is found that after increasing the alkali etching time from 350s to 410s, the Uoc and Isc of the battery are both reduced. This is because too long a time will cause excessive corrosion of the silicon substrate, and the silicon substrate will become thinner, resulting in reduced absorption of light in the long-wave band and reduced battery electrical performance.

[0123] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing an N-type TOPCon battery, characterized in that: include: S110: depositing a tunneling oxide layer and a Poly layer on the surface of the silicon wafer; S120: diffusing phosphorus on the silicon wafer on which the tunnel oxide layer and the Poly layer are deposited, so that a phosphorus-doped Poly layer is formed on the back side of the silicon wafer; S130: performing laser processing on the phosphorus-doped Poly layer in the non-gate line area on the back side of the silicon wafer to remove the phosphorus-doped Poly layer in the non-gate line area.

2. The method for preparing an N-type TOPCon battery according to claim 1, characterized in that: The laser treatment conditions are: laser wavelength is 500-600nm; laser energy density is 250-350mJ / cm 2 .

3. The method for preparing an N-type TOPCon battery according to claim 1 or 2, characterized in that: After S130, the method further includes: S140: removing the PSG layer and the Poly layer on the front side of the silicon wafer; S150: depositing an AlOx layer and an anti-reflection layer on the front side of the silicon wafer, and depositing an anti-reflection layer on the back side; S160: Printing gate line electrodes on the surface of the silicon wafer by using steel plate printing.

4. The method for preparing an N-type TOPCon battery according to claim 3, characterized in that: Before step S110, the method further includes: S101: Select an N-type single crystal silicon wafer as a substrate, perform double-sided texturing on the substrate, and form a pyramid-shaped anti-reflection texturing structure; S102: Diffusing boron on the double-sided textured silicon wafer to form a boron-doped single crystal silicon layer; S103: removing the boron-doped single crystal silicon layer and the BSG layer that are extended around the back and side surfaces of the N-type single crystal silicon wafer.

5. The method for preparing an N-type TOPCon battery according to claim 4, characterized in that: In S101, the double-sided texturing process includes: The N-type monocrystalline silicon wafer is sequentially pre-cleaned, washed, texturized, washed, post-alkali washed, washed, pickled, washed, slowly pulled, and dried; Among them, pre-cleaning time: 100-200s, pre-cleaning temperature: 60-75℃; Post-alkali washing time: 100-200s, post-alkali washing temperature: 60-75℃; Pickling time is 100-200s; Drying time: 600-700s, drying temperature: 90-100℃.

6. The method for preparing an N-type TOPCon battery according to claim 4, characterized in that: In S102, the boron diffusion includes three steps: diffusion / deposition, anaerobic advancement, and aerobic advancement; Among them, the diffusion / deposition temperature is 800-850°C; the anaerobic advancement temperature is 920-960°C; and the aerobic advancement temperature is 1000-1050°C.

7. The method for preparing an N-type TOPCon battery according to claim 4, characterized in that: The S103 includes: The silicon wafers after boron diffusion are sequentially pre-cleaned, washed, alkaline polished, washed, post-alkaline washed, washed, acid washed, washed, slowly pulled, and dried; Among them, pre-cleaning time: 100-200s, pre-cleaning temperature: 60-70℃; Alkali polishing time: 200-250s, alkali polishing temperature: 60-70℃; Post-alkali washing time is 100-200s; post-alkali washing temperature is: 60-70℃; Pickling time is 80-100s; Drying time: 650-750s, drying temperature: 90-100℃; In the S110, the thickness of the oxide layer is 1-2 nm, and the thickness of the poly layer is 115-125 nm.

8. The method for preparing an N-type TOPCon battery according to claim 4, characterized in that: In the S120, the gases used for phosphorus diffusion are POCl3, O2, N2, and POCl3, the gas flow rate is 2300 sccm, the phosphorus doping temperature is 800-900°C, and the sheet resistance of phosphorus-doped polysilicon is 45-60Ω / □.

9. The method for preparing an N-type TOPCon battery according to claim 4, characterized in that: In the S140, the silicon wafer after laser treatment is sequentially subjected to the following steps: alkali etching, water washing, alkali washing I, water washing, acid washing I, water washing, alkali washing II, water washing, acid washing II, water washing, slow pulling, and drying; Among them, the alkali etching time is: 300-400s; the alkali etching temperature is: 60-70℃; the alkali washing I time is: 80-100s, and the alkali washing I temperature is: 60-70℃; the acid washing I time is: 110-230s; the alkali washing II time is: 80-100s, and the temperature is: 60-70℃; the acid washing II time is: 100-120s; the drying time is: 650-750s, and the drying temperature is: 90-100℃.

10. An N-type TOPCon battery prepared by the method according to any one of claims 1 to 9.

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