Manufacturing method of standard wafer with sparse scattering defect

Abstract

The invention discloses a manufacturing method of a standard wafer with sparse scattering defects. The manufacturing method comprises the following steps: step 1, determining preset defect parameters; step 2, according to preset defect parameters, generating a defect graph formed by bulges or pits of which position coordinates are randomly arranged in the defect area, designing the defect graph into a standard sample plate structure layout, and manufacturing a target mask plate according to the standard sample plate structure layout; obtaining a target wafer through a thermal oxidation process; step 3, transferring the pattern on the target mask plate to the target wafer by using a photoetching process; and etching the target wafer by adopting an etching process to obtain a standard wafer. According to the manufacturing method of the standard wafer with the sparse scattering defects, the manufactured standard wafer has the controllable defect number and defect diameter, and the wafer can be cleaned and has the longer service life. And the distribution area, size and quantity parameters of the defects are all controllably generated, so that the requirements of different types of detection equipment can be met.

Description

Technical Field

[0001] The present invention relates to the field of measurement technology, and more specifically, to a method for manufacturing a standard wafer with sparse scattering defects. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, the size of nanostructures on chips is gradually decreasing, and the integration level is increasing exponentially. During the chip manufacturing process, particle contamination on the surface of semiconductor wafers will cause defects, affect subsequent processes, and produce defects such as short lines or bridges, causing device failure and reducing the yield rate of integrated circuit manufacturing.

[0003] The ever-shrinking device size places higher and higher demands on the accuracy of defect detection. Nanoscale defects or particles on the wafer surface require defect detection technology with higher sensitivity and accuracy to ensure the yield rate of integrated circuit manufacturing.

[0004] Integrated circuit manufacturing starts with blank wafers. The size and number of particle defects on blank wafers are mostly detected based on surface scanning technology. The increase in the number of particles before and after detection can be measured to characterize the pollution sources in the manufacturing process, and can also be used to monitor the effect of wafer surface cleaning. The measurement of semiconductor wafer surface particle size detection equipment is based on optical methods. When optical imaging technology detects defects at the scale of hundreds of nanometers, the image is affected by light diffraction. Due to the optical diffraction limit, it is impossible to obtain a defect image of boundary cleaning; light scattering detection technology is based on the relationship between scattered light intensity and defect diameter. By measuring the intensity of scattered light, the size of the particle defect causing the scattering can be inferred. This technology requires a calibration wafer with particles of standard diameter as a standard to calibrate the equipment to ensure accurate detection results.

[0005] In order to calibrate the relationship between the scattered signal detected by the equipment and the particle diameter, particles of different diameters are needed. At present, the international community generally uses dispersed particles of different diameters deposited on the surface of the wafer, such as polystyrene, silica and other particles, as standard wafers for such equipment. For example, the contaminant standard wafers of VLSI Corporation in the United States are widely used in the industry. However, particles are prone to aggregation during the deposition stage, and the particles are easily affected by the external environment and fall off, or cannot be cleaned after being contaminated by other sources, and have a short lifespan. At the same time, the existing particle deposition standard wafers can only simulate protrusion defects, and cannot solve the size calibration in pit defect detection.

[0006] Therefore, the problems existing in the prior art need to be further improved and developed. Summary of the invention

[0007] (I) Purpose of the invention: In order to solve the problems existing in the above-mentioned prior art, the purpose of the present invention is to provide a method for manufacturing a standard wafer with sparse scattering defects, wherein the manufactured standard wafer has the characteristics of long service life and cleanability, and the defects with random spatial distribution eliminate the interference effect between the scattered light of particles.

[0008] (II) Technical solution: In order to solve the above technical problems, the present technical solution provides a method for manufacturing a standard wafer with sparse scattering defects, comprising the following steps; Step 1: preset defect pattern parameters, wherein the defect pattern parameters include area parameters and defect parameters; the area parameters include the number of defect areas and the distribution position of each defect area; the defect parameters include the size of each defect in the defect area and the number of defect particles in each defect area, that is, the defect parameters include the defect size and the number of defects; the number of defect areas refers to the number of defect areas divided on a single wafer.

[0009] Step 2: According to preset defect graphic parameters, a defect pattern consisting of protrusions or pits randomly arranged in the dot position coordinates in the defect area is generated, the defect pattern is designed as a standard template structure layout, and a target mask is produced according to the standard template structure layout; a layer of silicon dioxide film is grown on the surface of a silicon wafer using a thermal oxidation process to obtain a target wafer, or a silicon oxide film is grown on the surface of a silicon carbide wafer using a chemical vapor deposition (CVD) process to obtain a target wafer.

[0010] Step three: Use a photolithography process to manufacture defect patterns on the target wafer, and transfer the defect pattern on the target mask to the target wafer; use an etching process to etch the target wafer to obtain a standard wafer; use a scanning electron microscope to measure the defect diameter, and measure the defect size and number of the manufactured standard wafer.

[0011] Furthermore, the number of defect regions is a positive integer greater than or equal to 1, and each defect region includes a defect pattern.

[0012] Furthermore, in the standard template structure layout, the defect size parameters in each defect pattern are different; the defect size in the defect pattern is a single size, or the defect size is distributed in an interval.

[0013] Furthermore, the single size means that the defective particles in the area have a single identical diameter; the defect size interval distribution means that within a single defect area, the average diameter of the defective particles is a numerical value, and the defect size is randomly distributed within a diameter range.

[0014] Furthermore, the defect pattern is a dot matrix arrangement of defect particles in the defect region, and the dot matrix arrangement of all defect particles in each defect region is a defect array.

[0015] Furthermore, by dividing each independent defect area into grids of equal size using a uniform grid division method, there is a 50% to 80% probability of generating defective particles at each grid point, thereby achieving a random distribution of the positions of defective particles in the defect area, and forming a sparse random defect array with a lattice arrangement.

[0016] Furthermore, in a single defect region, the distance between randomly occurring defect particles is greater than the spot diameter of the inspection device to be calibrated.

[0017] Further, the shape of the defect area is a rectangle or other shapes; the shape and size of the defect area are determined according to the size of the standard wafer and the number of the defect areas; All the defect areas do not intersect with each other, and all the defect areas are evenly distributed on the standard wafer around the center point of the standard wafer.

[0018] Furthermore, a thin film of silicon dioxide is grown on top of the highly polished wafer using a thermal oxidation process; A target mask is manufactured according to the standard template structure layout, and the pattern on the target mask is transferred to the photoresist by using an exposure process; and the pattern on the target mask is transferred to a target wafer by using a development process.

[0019] Further, a laser marking machine is used to mark the standard wafer to obtain an information area, wherein the information area is a circular dot matrix in the form of a two-dimensional code, with a diameter greater than 1 micron, and the information area does not intersect with all the defect areas and is arranged near the edge of the standard wafer; The two-dimensional code includes the region parameter information set on the standard wafer, the defect parameter information and the defect pattern information corresponding to each defect region.

[0020] (III) Beneficial effects: The present invention provides a method for manufacturing a standard wafer with sparse scattering defects, which can prepare a standard wafer with multiple defect areas and multiple defect sizes to meet the detection needs of the detection equipment to be calibrated. During the calibration process, the frequency of replacing the standard wafer is reduced, and it has extremely high compatibility and practicality. Moreover, in subsequent use, the standard wafer can be purged and cleaned, and has longer stability than the wafer made of particles in the prior art, which increases the service life of the sample. The random and sparse defect distribution avoids the optical interference of scattered light between multiple defect points within the spot illumination area, which affects the accuracy of detection. At the same time, the standard wafer has a controllable number of defects and defect size, and the standard value of the defect size is traceable by measuring the scanning electron microscope, which is used to calibrate the surface scanning equipment, greatly improving the calibration efficiency. Moreover, the regional parameters and defect parameters of the defects are controllably generated, which can better meet the needs of different types of detection equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a schematic diagram of the steps of a method for manufacturing a standard wafer with sparse scattering defects according to the present invention; Figure 2 It is a standard template structure layout with four defect areas provided by the present invention; Figure 3 It is a standard sample structure layout with defects of different diameters in three defect areas provided by the present invention; Figure 4 is a distribution diagram of a defect array of a fifth defect area provided by the present invention; Figure 5 is a schematic diagram of a standard wafer with an information area provided by the present invention; Figure Number: 1-first defect area, 2-second defect area, 3-third defect area, 4-fourth defect area, 5-fifth defect area, 6-sixth defect area, 7-seventh defect area, 8-eighth defect area, 9-ninth defect area, 10-tenth defect area, 11-information area. DETAILED DESCRIPTION

[0022] The present invention is further described in detail below in conjunction with preferred embodiments. More details are elaborated in the following description to facilitate a full understanding of the present invention. However, the present invention can obviously be implemented in a variety of other ways different from the description. Those skilled in the art can make similar generalizations and deductions based on actual application situations without violating the connotation of the present invention. Therefore, the protection scope of the present invention should not be limited by the content of this specific embodiment.

[0023] The accompanying drawings are schematic diagrams of embodiments of the present invention. It should be noted that the drawings are only examples and are not drawn to scale, and should not be used to limit the actual protection scope of the present invention.

[0024] The present invention provides a method for manufacturing a standard wafer with sparse scattering defects, such as Figure 1 As shown, the following steps are included: Step 1: Preset defect pattern parameters according to the detection equipment that needs to be calibrated, wherein the defect pattern parameters include area parameters and defect parameters; the area parameters include the number of defect areas and the distribution position of each defect area; the defect parameters include the size of each defect in the defect area and the number of defects in each defect area, that is, the defect parameters include the defect size and the number of defects; the number of defect areas refers to the number of defect areas divided on a single wafer; Step 2: Generate a defect pattern consisting of protrusions or pits randomly arranged in the dot position coordinates in the defect area according to the preset defect pattern parameters, design the defect pattern into a standard template structure layout, and produce a target mask according to the standard template structure layout; use a thermal oxidation process to grow a layer of silicon dioxide film on the surface of a silicon wafer to obtain a target wafer, or use a chemical vapor deposition (CVD) process to grow a silicon oxide film on the surface of a silicon carbide wafer to obtain a target wafer; Step three: Use a photolithography process to manufacture and process the defect pattern on the target wafer, and transfer the defect pattern on the target mask to the target wafer; use an etching process to etch the target wafer to obtain a standard wafer; use a scanning electron microscope to measure the defect diameter, and measure the defect size and number of the manufactured standard wafer.

[0025] Preferably, the number of defective regions of the regional parameters can be determined according to the needs of the detection equipment to be calibrated, the number of defective regions is a positive integer, and each defective region includes a defect pattern. According to the determined number of defective regions, all the defective regions are evenly distributed around the center point of the standard wafer on the standard wafer to obtain the distribution position of the defective regions.

[0026] The uniform distribution setting specifically means that the distance from the center of each defect area to the center of the wafer is equal. It should be noted that the distance between different defect areas is greater than 1CM to avoid multiple defect areas being scanned by the detection equipment to be calibrated at the same time, which affects the calibration result.

[0027] Preferably, the shape of the defect area can be a rectangle or other shapes, and the shapes of different defect areas can be the same or different. The shape and size of the defect area are determined according to the size of the wafer and the number of defect areas, and all defect areas set on the wafer do not intersect each other.

[0028] In a specific embodiment of the present invention, Figure 2 As shown, there are four defect areas evenly distributed on the standard wafer: a first defect area 1, a second defect area 2, a third defect area 3, and a fourth defect area 4. The first defect area 1 is a square, the second defect area 2 is a circle, the third defect area 3 is a circle, and the fourth defect area 4 is a rectangle. The second defect area 2 and the third defect area 3 have the same shape and area, and the first defect area 1, the second defect area 2, and the fourth defect area 4 have different shapes and areas, and the first defect area 1, the second defect area 2, the third defect area 3, and the fourth defect area 4 do not intersect with each other on the standard wafer.

[0029] Preferably, in the present invention, defect parameters are set inside the obtained defect region, and the defect parameters include the size of each defect particle in the defect region and the number of defect particles in each defect region, that is, the defect parameters include the defect size and the defect number.

[0030] Specifically, the defect size within a single defect region is a single size, or the defect size is a range distribution. The single size means that the defect particles within the region have a single identical diameter, such as 100nm, 200nm, 500nm, etc.; the defect size range distribution means that within a single defect region, the average diameter of the defect particles is a value, such as 200nm, and the size of the defect is a random distribution that varies within a diameter range. The diameter of the defect particles within different defect regions can be determined based on the size detection capability range of the detection equipment used for calibration. The diameter of the defect on the wafer is measured by a calibrated scanning electron microscope after production is completed.

[0031] In a wafer prepared by the method for manufacturing a standard wafer with sparse scattering defects of the present invention, the average diameter of the defects set inside the defect area is 200nm, and the number is 1000. The diameters of the 1000 defects inside the defect area obey a Gaussian random distribution, and the statistical variance of the distribution of the diameters is 20nm.

[0032] Specifically, the sizes of defective particles are different in different defective regions, that is, the defective particles have different defect sizes in different defective regions.

[0033] The number of defects refers to the number of each defect size, which can be 1000, 5000, 10000. The specific number of defects can be set as needed, and is not required in the present invention. In different defect areas, the number of defects can be set to the same or different, which can be set according to the detection equipment that needs to be calibrated.

[0034] In a specific embodiment of the present invention, in the step 2, when generating a defect pattern consisting of protrusions or pits with randomly arranged dot position coordinates in the defect area according to preset defect graphic parameters, the defect pattern can be generated by a Niagara particle system.

[0035] The Niagara particle system includes a control unit, an emission unit, a particle generation unit, and a material unit. The control unit can be a system component, responsible for the global management and control of the particle system, including the creation, initialization, update of the particle system, and interaction with other components or systems, allowing users to control and adjust the particle effects as a whole. The emission unit includes multiple emitters, each of which corresponds to a defect area. The emitter can independently control one or more particle effects, such as the position, quantity, frequency, etc. of the particles. The particle generation unit includes modules and parameters. The module is the basic level of the Niagara particle system, which encapsulates the behavior of particle generation and update. By combining different modules, the generation method, size and other properties of the particles can be defined. The parameters are used to control the specific values ​​in these modules, such as the initial size, speed, life cycle, etc. of the particles. The particle generation process is realized by the modules and the parameters.

[0036] The control unit creates and initializes a particle system according to preset defect graphic parameters, the particle generation unit defines a particle generation method and generates particles, and the emission unit emits the particles generated by the particle generation unit to the material unit for rendering and coloring, thereby generating a defect pattern consisting of protrusions or pits randomly arranged in the dot matrix position coordinates in the defect area.

[0037] In another specific embodiment of the present invention, in the step 2, when a defect pattern consisting of protrusions or pits randomly arranged in dot matrix position coordinates within the defect area is generated according to preset defect graphic parameters, the defect pattern is randomly arranged according to a certain dot matrix within the defect area, and a defect pattern is generated in each defect area at a defect coverage rate of 50%, and the defect sizes of different defect areas are different.

[0038] The lattice arrangement of all defective particles in each defective region is a defect array. Optionally, the defective region can be divided into grids of equal size by uniformly dividing each independent defective region, and there is a 50% to 80% probability of defective particles appearing at each grid point. Generate a random number P between 0 and 1. If P is greater than 0.5, a defect occurs at the grid point position, otherwise no defect occurs at this position, and the same applies to the remaining grid points. This method is used to achieve the random distribution of defective particle positions in the defective region, forming a sparse random defect array with a certain lattice arrangement.

[0039] like Figure 3 As shown, there are three defect regions distributed on the standard wafer: the fifth defect region 5, the sixth defect region 6, and the seventh defect region 7. Defect arrays are designed in the fifth defect region 5, the sixth defect region 6, and the seventh defect region 7. The defects in each region have different average defect diameters. For example, the average defect diameter in the fifth defect region 5 is 200nm, the average defect diameter in the sixth defect region 6 is 500nm, and the average defect diameter in the seventh defect region 7 is 100nm.

[0040] It should be noted that for a single defect area, the distance between randomly appearing defect particles needs to be greater than the diameter of the light spot of the measuring scanning detection equipment, that is, greater than the image resolution of the inspection equipment to be calibrated. This ensures that only one defect or a few defects on the wafer are scanned each time, avoiding the phenomenon that multiple defects cannot be distinguished by the detection equipment. In the prior art, the calibration wafer used by the existing detection equipment during calibration has the characteristic of dense defect distribution, and the detection parameter is the roughness of the wafer, rather than the limitation of the size of each defect. Therefore, the defects in the present invention have the characteristics of a fixed diameter, sparse position, and long-term stable structure within a single defect area.

[0041] Specifically, Figure 4 As shown, it shows Figure 5 A partial schematic diagram of the distribution of the defect array in the fifth defect region 5. The fifth defect region 5 is taken as an example for detailed description. The shape of the fifth defect region 5 is designed to be The fifth defect area 5 is divided into a grid of equal size, with a total of 100×100 grid points, and a protrusion with a defect size of 200nm in diameter is set in the fifth defect area 5. The position coordinates of the defect size in the fifth defect area 5 are distributed on grid points with a spacing of 100 microns. On the 100×100 grid points, the defects on each grid point appear randomly, and the number of defects generated on the 100×100 grid points is N, so the probability of randomly generating defects on each grid point is N / 10000. The N defect diameters inside each defect area obey Gaussian random statistical distribution, and the statistical variance of the diameter distribution is 20nm. It can be seen from this that the distance between the defect particles in a single defect area on the standard wafer designed by the present invention is large, so the detection equipment to be calibrated can only scan one defect or a few defects on the standard wafer. Different from other defects that scan a part of the area, the standard wafer designed by the present invention can achieve a more accurate calibration effect.

[0042] A standard template structure layout is designed based on the defect area parameters, defect parameters and defect pattern, that is, the standard template structure layout includes at least one defect area, and each defect area includes a defect pattern. The defect size in each defect pattern is different, and the number of defects in the defect patterns corresponding to any two different defect areas is the same or different. Figure 2 The standard template structure layout including four defect areas is shown. Then, a target mask is made according to the standard template structure layout. A layer of silicon dioxide film is grown on the surface of the wafer using a thermal oxidation process to obtain a target wafer.

[0043] Wherein, in the step three, photoresist is evenly applied on the target wafer obtained, and the pattern on the target mask is transferred to the photoresist by exposure using a photolithography process. Then the pattern on the target mask is transferred to the target wafer by a development process. That is, the standard template structure is transferred to the target wafer. Finally, the target wafer is etched by an etching process to obtain a standard wafer. It is conceivable that by using the method for manufacturing a standard wafer with sparse scattering defects of the present invention, a pit structure can also be manufactured on the target wafer, or a standard wafer with both protrusions and pits can be manufactured on the target wafer. Different from the polystyrene particle standard film used in the prior art, the defects formed by silicon dioxide etching are not easy to fall off, can be cleaned, and can be reused.

[0044] Specifically, an information area is also provided on the standard wafer. Figure 5As shown, an eighth defect area 8, a ninth defect area 9, a tenth defect area 10 and an information area 11 are distributed on the standard wafer, and the information area 11 does not intersect with the eighth defect area 8, the ninth defect area 9, and the tenth defect area 10, and is set near the edge of the standard wafer. The information area 11 is a circular dot matrix in the form of a two-dimensional code, with a diameter greater than 1 micron, which can be obtained by marking on the standard wafer by a laser marker. The two-dimensional code contains the regional parameter information, the defect parameter information and the defect pattern information corresponding to each defect area set on the standard wafer. The image of the information area 11 can be photographed by a microscope to obtain a two-dimensional code picture. The diameter information of the defect on the wafer is measured by a calibrated scanning electron microscope after the production is completed. More specifically, the two-dimensional code can also contain manufacturer information for later maintenance.

[0045] The manufacturing method of a standard wafer with sparse scattering defects of the present invention can prepare a standard wafer with multiple defect areas and multiple defect sizes, which meets the detection needs of the detection equipment to be calibrated. During the calibration process, the frequency of replacing the standard wafer is reduced, and it has extremely high compatibility and practicality. Moreover, in subsequent use, the standard wafer can be purged and cleaned, and has longer stability than the wafer made of particles in the prior art, which increases the service life of the sample. At the same time, the standard wafer has a controllable number of defects and defect diameter, which is used to calibrate surface scanning equipment, greatly improving the calibration efficiency. Moreover, the regional parameters and defect parameters of the defect pattern are controllably generated, which can better meet the needs of different types of detection equipment.

[0046] The above content is an explanation of the preferred embodiments of the present invention, which can help those skilled in the art to more fully understand the technical solution of the present invention. However, these embodiments are merely illustrative, and it cannot be determined that the specific implementation methods of the present invention are limited to the description of these embodiments. For ordinary technicians in the technical field to which the present invention belongs, without departing from the concept of the present invention, several simple deductions and transformations can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims

1. A method for manufacturing a standard wafer with sparse scattering defects, characterized in that: The steps include: Step 1: preset defect pattern parameters, wherein the defect pattern parameters include region parameters and defect parameters; the region parameters include the number of defect regions and the distribution position of each defect region; the defect parameters include the size of each defect in the defect region and the number of defect particles in each defect region, that is, the defect parameters include the defect size and the number of defects; the number of defect regions refers to the number of defect regions divided on a single wafer; Step 2: Generate a defect pattern consisting of protrusions or pits randomly arranged in the dot position coordinates in the defect area according to the preset defect pattern parameters, design the defect pattern into a standard template structure layout, and produce a target mask according to the standard template structure layout; grow a layer of silicon dioxide film on the surface of the wafer by a thermal oxidation process to obtain a target wafer, or grow a silicon oxide film on the surface of a silicon carbide wafer by a chemical vapor deposition process to obtain a target wafer; Step three: Use a photolithography process to manufacture defect patterns on the target wafer, and transfer the defect pattern on the target mask to the target wafer; use an etching process to etch the target wafer to obtain a standard wafer; use a scanning electron microscope to measure the defect diameter, and measure the defect size and number of the manufactured standard wafer.

2. The method for manufacturing a standard wafer with sparse scattering defects according to claim 1, characterized in that: The number of defect regions is a positive integer, and each defect region includes a defect pattern.

3. The method for manufacturing a standard wafer with sparse scattering defects according to claim 1, characterized in that: In the standard template structure layout, the defect size parameters in each defect pattern are different; the defect size in the defect pattern is a single size, or the defect size is distributed in an interval.

4. The method for manufacturing a standard wafer with sparse scattering defects according to claim 3, characterized in that: The single size means that the defective particles in the area have a single identical diameter; the defect size interval distribution means that within a single defect area, the average diameter of the defective particles is a numerical value, and the defect size is randomly distributed within a diameter range.

5. The method for manufacturing a standard wafer with sparse scattering defects according to claim 3, characterized in that: The defect pattern is a random arrangement of defect particles in a lattice in the defect region, and the lattice arrangement of all defect particles in each defect region is a defect array.

6. The method for manufacturing a standard wafer with sparse scattering defects according to claim 3, characterized in that: By dividing each independent defect area into grids of equal size using a uniform grid division method, there is a 50% to 80% probability of generating defective particles at each grid point, thereby achieving a random distribution of the positions of defective particles in the defect area, forming a sparse random defect array with a lattice arrangement.

7. The method for manufacturing a standard wafer with sparse scattering defects according to claim 6, characterized in that: In a single defect area, the distance between randomly occurring defect particles is greater than the spot diameter of the inspection device to be calibrated.

8. The method for manufacturing a standard wafer with sparse scattering defects according to claim 1, characterized in that: The shape of the defect area is a rectangle or other shapes; the shape and size of the defect area are determined according to the size of the standard wafer and the number of the defect areas; All the defect areas do not intersect with each other, and all the defect areas are evenly distributed on the standard wafer around the center point of the standard wafer.

9. The method for manufacturing a standard wafer with sparse scattering defects according to claim 1, characterized in that: A thin film of silicon dioxide is grown on top of a highly polished wafer using a thermal oxidation process; Making a target mask plate according to the standard template structure layout, and transferring the pattern on the target mask plate to the photoresist by using an exposure process; The pattern on the target mask is then transferred to a target wafer using a development process.

10. The method for manufacturing a standard wafer with sparse scattering defects according to claim 1, characterized in that: Marking the standard wafer with a laser marker to obtain an information area, wherein the information area is a circular dot matrix in the form of a two-dimensional code with a diameter greater than 1 micron, the information area does not intersect with all the defect areas, and is set near the edge of the standard wafer; The two-dimensional code includes the region parameter information set on the standard wafer, the defect parameter information and the defect pattern information corresponding to each defect region.

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