Multi-channel chip packaging test method and system

Abstract

The invention discloses a multi-channel chip packaging test method. Comprising the following specific steps: establishing a data set; acquiring operation data of the same type of multi-channel chip in different circuits; preprocessing the data; carrying out data cleaning and normalization processing on the collected original operation data; performing data statistics and analysis; carrying out statistical analysis on the preprocessed data; establishing a prediction model; establishing a feature recognition model based on a convolutional neural network (CNN); an optimal model is obtained through iterative training; verifying the model; the model of a chip and the type of a circuit where the chip is located serve as input, and a prediction model is used for outputting a predicted pseudo-random test vector algorithm and a predicted seed value; performing self-testing by using a predicted pseudo-random test vector algorithm and a seed value; summarizing test results to verify the prediction accuracy of the model; by using the scheme, the self-testing accuracy and the testing efficiency can be greatly improved, and flaws and potential flaws of the chip can be found as early as possible.

Description

Technical Field

[0001] The present invention relates to the technical field of multi-channel chip testing, and in particular to a multi-channel chip packaging testing method and system. Background Art

[0002] A multichannel chip is an integrated circuit chip with multiple independent channels, which is used to process and transmit multiple signals or data streams; each channel of a multichannel chip can independently process signals and data; common multichannel chips include A / D conversion chips, multi-channel RFID chips, multi-channel microcontrollers MCU, etc.; the application range of multichannel chips is also very wide. In the field of communication, multi-channel RFID chips can realize simultaneous identification and data processing of multiple tags in the Internet of Things communication to improve the communication rate and capacity. In the field of audio and video processing, multichannel voltage gain chips can process multiple audio and video signals at the same time, increase the voltage level of audio signals, enhance the anti-interference ability of signals, and improve the signal-to-noise ratio of the system; realize the synchronization and encoding of audio and video signals; in medical instruments, multichannel chips are used to collect and process physiological signals, such as electrocardiograms and electroencephalograms. These chips can provide high-precision, low-noise signal amplification and conversion, which helps doctors make accurate diagnoses. In the field of industrial automation, multichannel chips are used to monitor and control multiple sensors and actuators to achieve stable operation of automated production lines. For example, a multi-channel half-bridge driver chip can drive multiple DC motors, relays and other actuators to achieve precise control of automation equipment.

[0003] After the chip is packaged, it needs to be tested. Some chips need to be tested or retested at the system level or circuit board level. Some chips need to be tested at any time throughout their life cycle, such as chips related to autonomous driving and medical fields, such as pacemaker chips. To meet the needs of full-cycle testing of the above chips, the LogicBIST module is usually embedded in the chip during research and development and design for testing. LogicBIST is based on the Scan-based structure. It inserts BIST logic inside the chip to generate pseudo-random test vectors, and then uses these pseudo-random test vectors to perform self-test. The function of its hardware circuit structure is to generate test data, input it to the circuit under test, collect output responses, and verify whether the output results are correct. This workflow is controlled by the built-in self-test controller. Similar to the ATPG (automatic test vector generation) process, fault coverage can be used to evaluate the effectiveness of built-in self-test.

[0004] Another function of LogicBIST is to detect potential defects. For example, a metal line connecting two through holes in a chip has a gap during the etching process. There will be no failure in the early use process, and the chip can pass the ATE test when it leaves the factory. However, as the use time increases, the metal line breaks after a period of electromigration. At this time, the chip will have a failure in operation, and this defect is a potential defect. In the prior art, LogicBIST is classified according to the test time: on-lineBIST and off-lineBIST; here on-line and off-line mean offline and online. Offline test: refers to the BIST test when the chip is not working, which is suitable for the situation where the entire test process time is short. Online test: refers to the BIST test when the chip is still working; therefore, on-line BIST allows operation in the tested circuit, and it is necessary to find time gaps to test the chip, which leads to a long test cycle; and for some chips that do not stop, such as the aforementioned pacemaker chip, how to ensure the accuracy of the test results while improving the efficiency of online testing is conducive to earlier discovery of potential defects in the chip and less power consumption. Summary of the invention

[0005] In view of the above-mentioned background problems, the present invention proposes a multi-channel chip packaging test method and system.

[0006] Therefore, the problem to be solved by the present invention is how to improve the efficiency of online testing and discover potential defects in chips earlier.

[0007] In order to solve the above technical problems, the present invention provides the following technical solutions: A first aspect of the present invention provides a multi-channel chip packaging test method, comprising the following specific steps: S1, establish a data set; obtain the operating data of the same model multi-channel chip in different circuits; In step S1, a data set is established based on the model of the multi-channel chip, and the operation data of the chips of the same model are saved in the same data set; the data set is separated into multiple subsets according to the application of the chip in different circuits; the multi-channel chips collected include normal chips and faulty chips; while collecting the operation data, the chip data sheet information is also collected, including the chip model, pin interface information, electrical characteristic parameters, timing control diagram, and packaging information.

[0008] The chip operation data collected in step S1 includes the input rated current, rated voltage, frequency of the input signal, common fault types of this type of chip and the fault code corresponding to the fault, production batch information, pseudo-random test vector algorithm used when detecting the fault, and seed value.

[0009] S2, data preprocessing: data cleaning and normalization of the collected original operation data; The collected raw operating data first needs to remove outliers and duplicates, and then process the data in the same unit; in addition, the raw data can be converted into standard scores or Z scores by calculating statistics such as the mean and standard deviation of the data.

[0010] S3, data statistics and analysis: statistical analysis is performed on the preprocessed data, and data subsets are established for the data that passed the test and the data that failed the test; In step S3, the preprocessed data is classified; Establish data subsets for the test-passed data and the test-failed data respectively; re-divide the data in the test-passed subset and the test-failed subset according to normal chips and faulty chips; and generate new data subsets; S4, data labeling: label the data in the test passing data subset and the test failing data subset respectively; In step S4, feature annotation is performed on the faulty chip subset in the test-passing subset and the test-failed chip subset by manual annotation.

[0011] S5, establishment of prediction model; establishment of feature recognition model based on convolutional neural network CNN; setting training parameters: setting initial learning rate, using learning rate decay algorithm; obtaining optimal model through iterative training; using labeled data set as model input in step S5 to train feature recognition model of convolutional neural network CNN; the architecture of CNN model in step S5 includes input layer, convolution layer, pooling layer and fully connected layer; using predicted pseudo-random test vector algorithm and seed value to perform self-test using LogicBIST; summarizing test results to verify prediction accuracy of the model. In training parameters, the initial learning rate is set to 0.01; using exponential decay algorithm to iteratively optimize the model.

[0012] S6, verification of the model; using the chip model and the type of circuit it is in as input, using the prediction model to output the predicted pseudo-random test vector algorithm and the predicted seed value. The model outputs the following results: the predicted pseudo-random test vector algorithm and the predicted seed value; using the predicted pseudo-random test vector algorithm and seed value, using a random chip, and performing self-testing through the chip's built-in LogicBIST; verifying whether the chip fault can be identified through the test results; calculating the pass rate, and repeating steps S5-S6 until the pass rate meets expectations.

[0013] The second invention of the present invention provides a multi-channel chip packaging test system, which uses the above method to test the chip, including a data acquisition module, a data processing module, a human-computer interaction module and a chip test platform; The data acquisition module is used to collect the operating data required for chip testing; including the chip model, the circuit platform on which it is running, the input rated current, rated voltage, frequency of the input signal, common fault types of this type of chip and the fault code corresponding to the fault, the pseudo-random test vector algorithm used when the fault is detected, and seed value information; The data processing module is used to pre-process, perform statistical analysis and calculate the established model on the data collected by the data acquisition module; The human-computer interaction module includes a data display interface, a manual annotation module and a modification module; the data display interface displays the preprocessed data in the form of a chart; the manual annotation module is used to annotate the data; the modification module is used to modify the parameters of the prediction model; The chip test platform is used to provide a designated circuit system as a self-testing environment for the chip.

[0014] Preferably, the chip testing platform is provided with several testing stations to test multiple chips simultaneously.

[0015] A third aspect of the present invention provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above-mentioned multi-channel chip packaging test method when executing the computer program.

[0016] A fourth aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the steps of the above-mentioned multi-channel chip packaging test method when executed by a processor.

[0017] The beneficial effects of the present invention are as follows: the present invention collects a certain amount of chip operation data to systematically classify the chips first; determines normal chips and faulty chips by manual labeling, and then uses conventional pseudo-random test vectors to perform self-testing; extracts characteristic values ​​by analyzing the test results; selects pseudo-random test vectors with high judgment accuracy and corresponding seed values ​​as preferred test contents for testing; for chips of the same model and the same batch, there is a high possibility that the same defects exist, so for some common chips that can only be tested online during operation, the use of this solution can greatly improve the accuracy and test efficiency of self-testing, which is conducive to the early discovery of chip defects and potential defects. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 Flowchart of multi-channel chip packaging test method.

[0020] Figure 2 This is the structural diagram of the multi-channel chip packaging test system. DETAILED DESCRIPTION

[0021] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the accompanying drawings.

[0022] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0023] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The term "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive with other embodiments.

[0024] Example 1 This embodiment provides a multi-channel chip packaging test method, including the following specific steps: S1, establish a data set; obtain the operating data of the same model multi-channel chip in different circuits; In step S1, a data set is established based on the model of the multi-channel chip, and the operation data of the chips of the same model are saved in the same data set; the data set is separated into multiple subsets according to the application of the chip in different circuits; the multi-channel chips collected include normal chips and faulty chips; while collecting the operation data, the chip data sheet information is also collected, including the chip model, pin interface information, electrical characteristic parameters, timing control diagram, and packaging information.

[0025] The chip operation data collected in step S1 includes the input rated current, rated voltage, frequency of the input signal, common fault types of this type of chip and the fault code corresponding to the fault, production batch information, pseudo-random test vector algorithm used when detecting the fault, and seed value.

[0026] S2, data preprocessing: data cleaning and normalization of the collected original operation data; The collected raw operating data first needs to remove outliers and duplicates, and then process the data in the same unit; in addition, the raw data can be converted into standard scores or Z scores by calculating statistics such as the mean and standard deviation of the data.

[0027] S3, data statistics and analysis: statistical analysis is performed on the preprocessed data, and data subsets are established for the data that passed the test and the data that failed the test; In step S3, the preprocessed data is classified; Establish data subsets for the test-passed data and the test-failed data respectively; re-divide the data in the test-passed subset and the test-failed subset according to normal chips and faulty chips; and generate new data subsets; S4, data labeling: label the data in the test passing data subset and the test failing data subset respectively; In step S4, feature annotation is performed on the faulty chip subset in the test-passing subset and the test-failed chip subset by manual annotation.

[0028] S5, establishment of prediction model; establishment of feature recognition model based on convolutional neural network CNN; setting training parameters: setting initial learning rate, using learning rate decay algorithm; obtaining optimal model through iterative training; in step S5, using labeled data set as model input to train feature recognition model of convolutional neural network CNN; in step S5, the architecture of CNN model includes input layer, convolution layer, pooling layer and fully connected layer.

[0029] S6, verification of the model; using the chip model and the type of circuit it is in as input, use the prediction model to output the predicted pseudo-random test vector algorithm and the predicted seed value; use the predicted pseudo-random test vector algorithm and seed value to perform self-test using LogicBIST; summarize the test results to verify the prediction accuracy of the model. In the training parameters, the initial learning rate is set to 0.01; the model is iteratively optimized using an exponential decay algorithm. In step S6, the model outputs the following results: the predicted pseudo-random test vector algorithm and the predicted seed value; using the predicted pseudo-random test vector algorithm and seed value, using a random chip, and performing self-testing through the chip's built-in LogicBIST; verifying whether the chip fault can be identified through the test results; counting the pass rate, and repeating steps S5-S6 until the pass rate meets expectations.

[0030] The following uses a specific case to introduce the steps of this solution in detail: The ADS1113 chip is a high-precision, low-power 16-bit analog-to-digital converter (ADC) chip; its basic information is as follows: Resolution: 16 bits, providing high-precision analog-to-digital conversion.

[0031] Power consumption: In continuous conversion mode, the power consumption is only 150μA; in one-shot mode, the device automatically powers down after a single conversion, significantly reducing power consumption during idle periods.

[0032] Package: Available in ultra-small leadless QFN-10 or MSOP-10 packages measuring 2mm x 1.5mm x 0.4mm for space-constrained applications.

[0033] Working power supply: wide power supply voltage range, from 2.0V to 5.5V, adapt to different power supply environments.

[0034] Data Rate: Programmable data rate from 8SPS (samples per second) to 860SPS, which can be adjusted according to application needs.

[0035] On-board Reference and Oscillator: An internal low-drift voltage reference and an oscillator provide stable analog-to-digital conversion without external components.

[0036] I2C interface: compatible with I2C serial interface, supports 4 I2C slave address selections, and facilitates communication with microcontrollers and other main control chips.

[0037] Single-ended / differential input: Although the specific input configuration of ADS1113 may vary depending on the model or package, this type of chip generally supports single-ended or differential input to accommodate different signal acquisition requirements.

[0038] Application areas: ADS1113 chips are widely used in portable instruments, consumer goods, battery monitoring, temperature measurement, factory automation and process control, especially in medical equipment, where its high precision and low power consumption make it an ideal choice.

[0039] Advantages and features: Ultra-small package, wide power supply range, low current consumption, programmable data rate, and internal reference and oscillator make the ADS1113 chip perform well in power-constrained and space-constrained sensor measurement applications.

[0040] Based on the above advantages, the ADS1113 chip can also be used in common devices such as ventilators and pacemakers. During the operation of the equipment, the chip needs to be tested online for safety reasons. The traditional solution is to use the pseudo-random test vector generation capability of LogicBIST to generate independent test vectors for each channel. These test vectors should cover all possible inputs and states of the channel to ensure the comprehensiveness of the test. Pseudo-random test vectors are generally generated by specific algorithms or circuits, including linear feedback shift registers (LFSRs), pseudo-random number generators (PRGs), and pseudo-random number generators combined with memory. Among them, LFSR is a simple and efficient pseudo-random number generation algorithm, which generates a pseudo-random number sequence through a feedback loop composed of a shift register and an XOR gate.

[0041] Specifically: define a shift register whose length determines the period of the pseudo-random number sequence.

[0042] According to a specific feedback function, some bits of the shift register are XORed and the result is used as a new input bit. In each clock cycle, the value of the shift register is shifted to the left by one bit, and the new input bit is added to the lowest bit, which can generate a longer pseudo-random number sequence with less hardware overhead; PRG is a more complex random number generation algorithm that uses more logic gates and state variables to implement it.

[0043] Specific: Define a state variable to store the current state.

[0044] At each clock cycle, the values ​​of the state variables are updated according to a specific algorithm.

[0045] Output the value of the state variable as a pseudo-random number.

[0046] This article takes the pseudo-random number generator combined with a memory as an example to introduce; unlike the aforementioned PRG, after combining with a memory, the memory can be used to store the seed of the pseudo-random generator; the phase shift or control of the pseudo-random test sequence is achieved through the control unit, and the generation of the pseudo-random test sequence can be flexibly controlled, making it suitable for application scenarios that require complex test sequences.

[0047] The specific steps are as follows: S1, establish a data set; obtain the operation data of the ADS1113 chip in different circuits; according to the different functions of the ADC chip in different circuits, preset several basic circuit models, including the bridge circuit model, the amplifier circuit model, the interface circuit model, the current-voltage conversion model and the filter circuit model; among them, the bridge circuit is used to convert the changes in the resistance, capacitance and inductance of the sensor into changes in voltage or current, so as to facilitate the capture of analog signals through the ADC chip; such as resistive sensors (thermistors, potentiometers), capacitive sensors and inductive sensors; The amplifier circuit is used to amplify the output signal of the sensor, thereby improving the measurement accuracy and sensitivity; the amplifier circuit is also a common application scenario.

[0048] The interface circuit is used to convert the sensor output to low impedance when it is high impedance, so that the detection circuit can accurately obtain the sensor signal.

[0049] The current-to-voltage conversion model is also a common application scenario, which is mainly used to convert certain sensors that output current signals into voltage signals for output.

[0050] The filter circuit model is used to remove noise and interference components in the sensor output signal to improve the signal purity and measurement accuracy. The above section only gives an exemplary case. The specific model type can be further refined according to the application scenario. For example, the amplifier circuit can be set to a differential amplifier circuit or other high-frequency amplifier circuit.

[0051] Create a data set X based on the chip model i , i is the number of chips of the same model; X i {X 1 , X 2 ...X n}; Data set concentration: According to the application of the chip in different circuits, the data set is separated into multiple subsets; i {X i,1 , X i,2 ...X i,n}; For example, if 10 ADS1113 chips are actually tested, the data set corresponding to chip No. 1 is recorded as X 1 ,The dataset corresponding to chip No. 10 is named X 10 , and the corresponding subset is recorded as X 10,n ; n is the number of different types of circuit models; then, the bridge circuit model X of chip No. 10 10,1 , Amplifier circuit model X 10,2 、Interface circuit model X 10,3 , current-voltage conversion model X 10,4、Filter circuit model X 10,5 ; The multi-channel chips collected include normal chips and faulty chips; while collecting operation data, the chip data sheet information is also collected, including the chip model, pin interface information, electrical characteristic parameters, timing control diagram, and packaging information. The collected chip operation data includes the input rated current, rated voltage, frequency of the input signal, common fault types of this type of chip and the fault code corresponding to the fault, the pseudo-random test vector algorithm used when detecting the fault, and the seed value; two separate vectors are generated for the collected data sheet information and chip operation data, respectively recorded as A and B; each collected data is written into the vector in a fixed order and finally synthesized into two high-dimensional vectors: A(a 1 , a 2 ……a m ) B(b 1 ,b 2 ,……b k ) In the above formula, A is the data manual vector, a 1 , a 2 ……a m are the parameters in the data sheet, m is the number of parameters; B is the chip operation vector, b 1 ,b 2 ,……b k are the parameters of the chip operation data, and k is the number of parameters.

[0052] S2, data preprocessing: data cleaning and normalization of the collected original operation data; The collected raw operating data first needs to remove outliers and duplicates, and then process the data in the same unit; in addition, the raw data can be converted into standard scores or Z scores by calculating statistics such as the mean and standard deviation of the data.

[0053] S3, data statistics and analysis: statistical analysis is performed on the preprocessed data, and data subsets are established for the data that passed the test and the data that failed the test; In step S3, the preprocessed data is classified; The data that passed the test and the data that failed the test are respectively used to create data subsets; among them, T t is the test pass data subset, T f The test failed data subset is obtained; the data in the test passed subset and the test failed subset are re-divided into normal chips and faulty chips; and a new data subset is generated.

[0054] Among the pre-prepared chips, some are normal chips that have passed the ATE test and some are defective chips that have failed the test; select as many chips with various fault causes as possible to obtain the operating data of the chips under different fault conditions; after testing the chips, divide them according to the good and bad functions; among them, T t,t represents the normal chip data subset in the test-passed data subset, T t,f represents the failed chip data subset in the test passed data subset; T f,t represents the normal chip data subset in the test failure data subset, T f,f Represents the faulty chip data subset in the test failure data subset.

[0055] S4, data annotation; for the test data subset T t And the test failure data subset T f The data in the test pass subset are annotated respectively; the faulty chip subset T in the test pass subset is annotated manually. t,f and the test failure subset T t Perform feature labeling; by analyzing and processing the test data obtained in steps S3 and S4, the influence of different pseudo-random test vector algorithms and seed values ​​on the test results can be obtained; a. The subset of faulty chips in the test passing subset T t,f If there is a fault in the chip, but the algorithm and seed value used for self-testing do not find any problems, then the algorithm and the corresponding seed value are flawed and this error should be eliminated in subsequent processing; b. For the test failure subset T t When labeling, the normal chip data subset T in the test failure data subset f,t , it is because the algorithm and seed value have problems and the normal chip is judged as faulty. For such cases, the test weight of the algorithm and the corresponding seed value should be reduced; c. For the faulty chip data subset T in the test failure data subset f,f In the above, the corresponding algorithm and seed value should be given weight and saved in the memory; when testing, this type of algorithm and seed value should be used first to improve test efficiency and reduce power consumption; the sum of the total weights set in cases b and c is 1.

[0056] S5, establishment of prediction model; establishment of feature recognition model based on convolutional neural network CNN; setting training parameters: setting initial learning rate, using learning rate decay algorithm; obtaining optimal model through iterative training; using labeled data set as model input in step S5 to train feature recognition model of convolutional neural network CNN; the architecture of CNN model in step S5 includes input layer, convolution layer, pooling layer and fully connected layer. Self-testing is performed using LogicBIST using predicted pseudo-random test vector algorithm and seed value; summarizing test results to verify prediction accuracy of the model. In training parameters, the initial learning rate is set to 0.01; using exponential decay algorithm to iteratively optimize the model.

[0057] For the same pseudo-random test vector algorithm, the test vector is randomly generated, and in the present embodiment further, the starting value and seed value of the pseudo-random test vector algorithm used for detecting the fault can be preferably used as input for testing; without changing the calculation rules of the pseudo-random test vector algorithm, the self-test efficiency and fault detection rate can be improved for the same type of fault of the same model chip.

[0058] S6, verification of the model; using the chip model and the type of circuit in which it is located as input, using the prediction model to output the predicted pseudo-random test vector algorithm and the predicted seed value; The results of the model output are: a predicted pseudo-random test vector algorithm and a predicted seed value; using the predicted pseudo-random test vector algorithm and seed value, using a random chip, and performing self-testing through the chip's built-in LogicBIST; verifying whether the chip fault can be identified through the test results; calculating the pass rate, and repeating steps S5-S6 until the pass rate meets expectations.

[0059] In this embodiment, the same batch of chips uses the same processing technology and processing steps. When a chip has a specific defect, the probability of the other chips having the same defect is relatively high; therefore, in practical applications, it can be considered to store the type, seed value and starting value of the pseudo-random test vector algorithm used for self-testing of the faulty chip in the memory; self-testing is given priority to reduce the amount of detection and improve detection efficiency. In general multi-channel chips, different channels work independently. When testing several channels with the same function, when the test result is qualified, another test vector and seed value are replaced to test the remaining channels with the same function; if the test result is unqualified, the same test vector and seed value are used to test the remaining channels with the same function. For example, D1, D2, D3, and D4 are parallel channels with the same function on the chip; when the first test vector and the first seed value are used to detect D1 and the test result is qualified, the second test vector and the seed value are used to detect D2, and so on, more test vectors and seed values ​​are used for testing to find possible defects as soon as possible; and when the first test vector and the first seed value are used to detect D1 and the test result is unqualified, the first test vector and the first seed value are used to test D2, D3, and D4 to find possible defects as soon as possible.

[0060] Example 2 This embodiment provides a multi-channel chip packaging test system, which uses the method in Embodiment 1 to test the chip, including a data acquisition module, a data processing module, a human-computer interaction module and a chip test platform; The data acquisition module is used to collect the operating data required for chip testing; including the chip model, the circuit platform on which it is running, the input rated current, rated voltage, frequency of the input signal, common fault types of this type of chip and the fault code corresponding to the fault, the pseudo-random test vector algorithm used when the fault is detected, and seed value information; The data processing module is used to pre-process, perform statistical analysis and calculate the established model on the data collected by the data acquisition module; The human-computer interaction module includes a data display interface, a manual annotation module and a modification module; the data display interface displays the preprocessed data in the form of a chart; the manual annotation module is used to annotate the data; the modification module is used to modify the parameters of the prediction model; The chip test platform is used to provide a designated circuit system for the chip to carry out self-testing. The chip test platform is equipped with several test stations to test multiple chips at the same time. In this embodiment, the chip test platform can pre-set common models including bridge circuit models, amplifier circuit models, interface circuit models, current-voltage conversion models, and filter circuit models; and provide multiple test stations; so that the chip can be quickly tested at the system level or circuit board level; as a further solution, the chip test platform meets the ATE test requirements.

[0061] In this embodiment, data is obtained by testing several chips to provide a data set and a verification set for the training of the prediction model; after the prediction model is trained, the predicted pseudo-random test vector and seed value can be output by the model, and written into the memory of the chip through the communication module. The chip preferentially uses the predicted pseudo-random test vector and seed value for self-testing during operation; accordingly, if a defect or fault is detected during the chip self-test, it can be uploaded to the test system through the communication module to facilitate subsequent processing.

[0062] Example 3 This embodiment also provides a computer device suitable for the steps of the multi-channel chip packaging test method, including a memory and a processor; the memory is used to store computer executable instructions, and the processor is used to execute computer executable instructions to implement the steps of the multi-channel chip packaging test method proposed in Example 1. The computer device may be a terminal, and the computer device includes a processor, a memory, a communication interface, a display screen and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be achieved through WIFI, an operator network, NFC (near field communication) or other technologies. The display screen of the computer device may be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device may be a touch layer covered on the display screen, or a key, trackball or touchpad provided on the housing of the computer device, or an external keyboard, touchpad or mouse, etc.

[0063] Example 4 This embodiment further provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the multi-channel chip packaging test method described in Embodiment 1 are implemented.

[0064] The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination of them, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable red-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, disk or optical disk.

[0065] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A multi-channel chip packaging test method, characterized in that: The specific steps include: S1, establish a data set; obtain the operating data of the same model multi-channel chip in different circuits; S2, data preprocessing: data cleaning and normalization of the collected original operation data; S3, data statistics and analysis; Perform statistical analysis on the preprocessed data and create data subsets for the data that passed the test and the data that failed the test; S4, data labeling: label the data in the test passing data subset and the test failing data subset respectively; S5, establishment of prediction model; establishment of feature recognition model based on convolutional neural network CNN; Set training parameters: set the initial learning rate and use the learning rate decay algorithm; obtain the optimal model through iterative training; S6, verification of the model; using the chip model and the type of circuit it is in as input, use the prediction model to output the predicted pseudo-random test vector algorithm and the predicted seed value; use the predicted pseudo-random test vector algorithm and seed value to input LogicBIST for self-testing; summarize the test results to verify the prediction accuracy of the model.

2. A multi-channel chip packaging test method according to claim 1, characterized in that: In step S1, a data set is established based on the model of the multi-channel chip, and the operation data of the chips of the same model are stored in the same data set; the data set is separated into multiple subsets according to the application of the chip in different circuits; the collected multi-channel chips include normal chips and faulty chips.

3. A multi-channel chip packaging test method according to claim 1, characterized in that: The chip operation data collected in step S1 includes the input rated current, rated voltage, frequency of the input signal, common fault types of this type of chip and the fault code corresponding to the fault, the pseudo-random test vector algorithm used when detecting the fault, and the seed value.

4. A multi-channel chip packaging test method according to claim 1, characterized in that: In step S3, the preprocessed data is classified; The data of the test passing data and the test failing data are respectively established into data subsets; the data in the test passing subset and the test failing subset are re-divided into normal chips and faulty chips; Generate new subsets of data.

5. The multi-channel chip packaging test method according to claim 1, characterized in that: In step S4, feature annotation is performed on the faulty chip subset in the test-passing subset and the test-failed chip subset by manual annotation.

6. A multi-channel chip packaging test method according to claim 1, characterized in that: In step S5, the labeled data set is used as a model input to train a feature recognition model of a convolutional neural network (CNN).

7. A multi-channel chip packaging test method according to claim 6, characterized in that: The architecture of the CNN model in step S5 includes an input layer, a convolutional layer, a pooling layer, and a fully connected layer; In the training parameters, the initial learning rate is set to 0.01; the exponential decay algorithm is used to iteratively optimize the model.

8. A multi-channel chip packaging test method according to claim 1, characterized in that: In step S6, the results of the model output are: a predicted pseudo-random test vector algorithm and a predicted seed value; using the predicted pseudo-random test vector algorithm and seed value, using a random chip, and performing self-testing through the chip's built-in LogicBIST; verifying whether the chip fault can be identified through the test results; calculating the pass rate, and repeating steps S5-S6 until the pass rate meets expectations.

9. A multi-channel chip packaging test system, using the method according to any one of claims 1 to 8 to test the chip, characterized in that: Including data acquisition module, data processing module, human-computer interaction module and chip testing platform; The data acquisition module is used to collect the operating data required for chip testing; including the chip model, the circuit platform on which it is running, the input rated current, rated voltage, frequency of the input signal, common fault types of this type of chip and the fault code corresponding to the fault, the pseudo-random test vector algorithm used when the fault is detected, and seed value information; The data processing module is used to pre-process, perform statistical analysis and calculate the established model on the data collected by the data acquisition module; The human-computer interaction module includes a data display interface, a manual annotation module, and a modification module; the data display interface displays the pre-processed data in the form of charts; The manual labeling module is used to label the data; the modification module is used to modify the parameters of the prediction model; The chip test platform is used to provide a designated circuit system as a self-testing environment for the chip.

10. The multi-channel chip packaging test system according to claim 9, characterized in that: The chip testing platform is equipped with several testing stations to test multiple chips at the same time.

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