Implementation method for reading and writing any byte length in RapidIO memory

Abstract

The invention provides an implementation method for reading and writing any byte length in a RapidIO memory. The implementation method comprises the steps that a communication node and an FPGA node are connected with a RapidIO exchange chip through a RapidIO bus; and the FPGA node performs unpacking and complementing operation on a length field of memory write sending or memory read sending logically input by a user, so that the RapidIO memory can read and write any byte length. According to the method, the FPGA node performs unpacking and complementing operation on the length field of memory write sending or memory read sending logically input by a user, on one hand, for memory write sending, after all data are sent, the actual application data length is sent out, and the problem that any byte length is written in the memory is solved; on the other hand, according to memory read sending, data received by memory read response is discarded according to the length of the data to be read input by the user logic, and the problem that the memory reads any byte length is solved.

Description

Technical Field

[0001] The present invention relates to the field of integrated electronic information systems, and in particular to a method for realizing RapidIO memory reading and writing arbitrary byte lengths. Background Art

[0002] FPGA chips are programmable, highly flexible, have short development cycles, and have strong parallel processing capabilities, and are increasingly being used in integrated electronic information system hardware platforms.

[0003] As a bus interconnection standard in the embedded field, RapidIO bus is increasingly used for high-speed interconnection between chips and modules due to its high bandwidth, low latency, and high reliability. It is connected to the RapidIO switching network through RapidIO switching chips.

[0004] In FPGA nodes, RapidIO data transmission and reception is implemented by calling RapidIO IP Core. For situations with high bandwidth requirements for big data, memory read and write is used. Calling RapidIO IP Core is generally based on HELLOFormat; the length range (in bytes) of a single RapidIO data packet for memory read and write using HELLO Format is: 8, 16, 32, 64, 96 (memory read only), 128, 192 (memory read only), 224 (memory read only), 256. It can be seen that the length range of a single RapidIO memory read and write data packet is limited and is aligned to 8 bytes; in actual use, it is difficult to require all nodes to be aligned to 8 bytes. Summary of the invention

[0005] The present invention aims to provide a method for realizing RapidIO memory reading and writing of arbitrary byte length, and solves the problem that the RapidIO memory reading and writing mode in FPGA node cannot transmit arbitrary byte length without substantially increasing the system software cost.

[0006] The present invention provides a method for realizing RapidIO memory reading and writing arbitrary byte length, comprising:

[0007] Both the communication nodes and FPGA nodes are interconnected with the RapidIO switch chip through the RapidIO bus;

[0008] The FPGA node unpacks and pads the length field of the memory write or memory read sent by the user logic input to achieve RapidIO memory reading and writing of arbitrary byte length.

[0009] In some embodiments, the FPGA node internally includes a RapidIO IP core, a memory write send Send_nwrite control module, a memory read send Send_nread control module, a data send Send_data control module, a memory read response receive Recv_resp_nread control module, a memory write receive Recv_nwrite control module, a memory read receive Recv_nread control module and a memory read response send Send_resp_nread control module.

[0010] In some embodiments, the memory write send Send_nwrite control module, on the one hand, receives a memory write send start signal, memory write send data, memory write send length, and memory write send starting address input from a user; on the other hand, unpacks the input data according to the memory write send length, splits it into N integer data packets + 1 tail packet, and pads the tail packet; writes the unpacked and padded data packet data into the data FIFO; and when the integer data packet and the tail packet data packet are written, writes the length of the split data packet into the lower 32 bits of the length FIFO, and writes the starting address of the split data into the upper 32 bits.

[0011] In some embodiments, the memory read send Send_nread control module, on the one hand, receives a memory read send start signal, a memory read send length, and a memory read send start address input from a user; on the other hand, unpacks the input memory read send length, splits it into N integer data packets + 1 tail packet data packet, and pads the tail packet data packet; and writes each memory read send length after unpacking and padding into the lower 32 bits of the FIFO, and writes each memory read send start address into the upper 32 bits of the FIFO.

[0012] In some embodiments, the data sending Send_data control module receives, on the one hand, a memory write data packet sending FIFO empty signal, a memory write data packet sending data, a memory write data packet sending, a memory write data packet sending starting address, and a memory write data packet sending tail packet indication signal output by a memory write sending Send_nwrite control module; on the other hand, receives a memory read data packet sending FIFO empty signal, a memory read data packet sending, and a memory read data packet sending starting address output by a memory read sending Send_nread module; when either the memory write data packet sending FIFO empty signal or the memory read data packet sending FIFO empty signal is 0, starts an internal sending process; generates a memory write send RapidIO data packet or a memory read send RapidIO data packet, and sends it to the RapidIO switching network through the RapidIO IP core.

[0013] In some embodiments, the memory read receive Recv_nread control module receives data input from the RapidIO IPcore, extracts the memory read receive length and the memory read receive address by parsing the RapidIO data packet, and then generates a memory read receive start signal.

[0014] In some embodiments, the memory read response sending Send_resp_nread control module receives a memory read reception start signal output from a memory read reception Recv_nread control module, and sends the memory read response data from the user logic to the RapidIO switching network through the RapidIO IP core according to the memory read reception length and the memory read reception address.

[0015] In some embodiments, the memory write send Send_nwrite control module enters the initial state after the power-on reset is completed, and then determines whether the user logic starts the memory write. If the user logic starts the memory write, it determines whether the length of the data to be sent is greater than X bytes:

[0016] If the length of the data to be sent is greater than X bytes, X bytes of data are written to the data FIFO, and then the lower 32 bits of the length FIFO are written to X, and the upper 32 bits are written to the starting address of the data to be sent, and then the length of the data to be sent and the starting address of the data to be sent are updated, and then it is determined whether the length of the data to be sent is greater than X bytes, and the above process is repeated;

[0017] If the length of the data to be sent is not greater than X bytes, the length of the data to be sent will be padded with zeros according to 8 bytes, and then the data after alignment and padding will be written into the data FIFO. Then, the length of the data after alignment and padding will be written into the length FIFO in the lower 32 bits, and the starting address of the data to be sent will be written into the upper 32 bits. Finally, the system returns to the initial state.

[0018] In some embodiments, the memory read send_nread control module enters the initial state after the power-on reset is completed, and then determines whether the user logic starts the memory read. If the user logic starts the memory read, it determines whether the length of the data to be read is greater than X bytes:

[0019] If the length of the data to be read is greater than X bytes, the length X is written to the lower 32 bits of the FIFO, and the starting address status of the data to be read is written to the upper 32 bits. Then the length of the data to be read and the starting address status of the data to be read are updated, and then it is determined whether the length of the data to be read is greater than X bytes, and the above process is repeated;

[0020] If the length of the data to be read is not greater than X bytes, the length of the data to be read will be aligned and padded with zeros. Then, the lower 32 bits of the aligned and zero-padded data length X will be written to the FIFO, and the upper 32 bits will be written to the starting address of the data to be read, and then the initial state will be returned.

[0021] In some embodiments, the data sending Send_data control module enters the initial state after the power-on reset is completed, and then determines whether the memory read data packet sending FIFO empty signal is 0:

[0022] If the FIFO empty signal sent by the memory read data packet is 0, a memory read RapidIO data packet is generated, and then it is determined whether a memory read response is received. If a memory read response is received, the initial state is returned; otherwise, it is determined whether the memory read response has timed out. If so, the initial state is returned;

[0023] If the memory read data packet sends a FIFO empty signal that is not 0, then determine whether the memory write data packet sends a FIFO empty signal that is 0. If the memory write data packet sends a FIFO empty signal that is not 0, then return to the initial state; if the memory write data packet sends a FIFO empty signal that is 0, then determine whether the memory write data packet sends a tail packet indication identification signal that is 0. If the memory write data packet sends a tail packet indication identification signal that is 0, then generate a RapidIO data packet with a memory write length of X bytes, and then return to the initial state;

[0024] If the end packet indication identification signal of the memory write data packet is not 0, it is determined whether the length of the memory write data packet is equal to X. If the length of the memory write data packet is equal to X, a memory write end packet RapidIO data packet with a length of X bytes is generated, and then the memory write receiving data length is sent to the receiver in the form of memory write, and then a doorbell is sent to the receiver, and then it is determined whether a doorbell response is received. If a doorbell response is received, it returns to the initial state; if no doorbell response is received, it is determined whether the doorbell response is timed out. If it is timed out, it returns to the initial state;

[0025] If the memory write data packet sending length is not equal to X, the memory write data packet sending length is determined by half of the length each time until the shortest length is reached. Each time, a RapidIO data packet of the corresponding length is generated, and then the length of the data to be sent is updated. Then, the memory write receiving data length is sent to the receiver in the form of memory write, and then a doorbell is sent to the receiver. Then, it is determined whether a doorbell response is received. If a doorbell response is received, the system returns to the initial state. If no doorbell response is received, it is determined whether the doorbell response has timed out. If so, the system returns to the initial state.

[0026] In some embodiments, the memory read response receiving Recv_resp_nread control module enters an initial state after power-on reset is completed, and then determines whether the received RapidIO data packet is a memory read response. If the received RapidIO data packet is a memory read response, the received RapidIO data packet of the memory read response is written into the Recv_resp_nread data FIFO, and then determines whether all the RapidIO data packets of the current memory read response are written into the FIFO. If all the RapidIO data packets of the current memory read response are written into the FIFO, it is determined whether the data length written into the FIFO is greater than or equal to the memory read receiving and sending length:

[0027] If the data length written into FIFO is greater than or equal to the memory read receive send length, the data byte valid identification status is given according to the read FIFO, and then it is determined whether the FIFO is read empty. If the FIFO is read empty, the receive response data length count status is cleared, and then the initial state is returned;

[0028] If the length of the data written to the FIFO is less than the length of the memory read reception and transmission, the process returns to determine whether the received RapidIO data packet is a memory read response, and the above process is repeated.

[0029] In some embodiments, the memory write receiving Recv_nwrite control module enters the initial state after the power-on reset is completed, and then determines whether the received RapidIO data packet is a memory write:

[0030] If the received RapidIO data packet is a memory write, determine whether the received RapidIO data packet is a length data packet. If the received RapidIO data packet is a length data packet, record the actual length of the data sent by the sender, then read the FIFO according to the actual length of the data sent, give a valid data byte flag, and then return to the initial state;

[0031] If the received RapidIO data packet is not a memory write, the received data is written into the FIFO, and then the process returns to determine whether the received RapidIO data packet is a memory write, and the above process is repeated.

[0032] In some embodiments, the memory read receiving Recv_nread control module enters the initial state after power-on reset is completed, and then determines whether the received RapidIO data packet is a memory read. If the received RapidIO data packet is a memory read, it records the address to be read and the length to be read, and then returns to the initial state.

[0033] In some embodiments, the memory read response sending Send_resp_nread control module enters the initial state after the power-on reset is completed, and then determines whether Recv_resp_start is valid. If Recv_resp_start is valid, a memory read response packet is generated according to the address to be read and the length to be read, and then returns to the initial state.

[0034] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0035] In the present invention, the FPGA node performs unpacking and padding operations on the length field of the memory write transmission or memory read transmission input by the user logic. On the one hand, for memory write transmission, after all data are sent, the actual application data length is sent out to solve the problem of arbitrary byte length of memory write. On the other hand, for memory read transmission, according to the length of the data to be read input by the user logic, the data received by the memory read response is discarded to solve the problem of arbitrary byte length of memory read. In addition, the software implementation of the present invention is simple, and the driver and application can be decoupled. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a schematic diagram of a method for realizing the RapidIO memory reading and writing arbitrary byte lengths of the present invention.

[0037] Figure 2 yes Figure 1 Implementation schematic.

[0038] Figure 3 yes Figure 2 Memory write send Send_nwrite control module processing flow chart.

[0039] Figure 4 yes Figure 2 Memory read send Send_nread control module processing flow chart.

[0040] Figure 5 yes Figure 2 Data sending Send_data control module processing flow chart.

[0041] Figure 6 yes Figure 2 Memory read response receiving Recv_resp_nread control module processing flow chart.

[0042] Figure 7 yes Figure 2 Memory write receive Recv_nwrite control module processing flow chart.

[0043] Figure 8 yes Figure 2Memory read receive Recv_nread control module processing flow chart.

[0044] Fig. 9 yes Figure 2 Memory read response sending Send_resp_nread control module processing flow chart. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0046] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0047] This embodiment provides a method for implementing RapidIO memory reading and writing arbitrary byte lengths, including:

[0048] Both the communication nodes and FPGA nodes are interconnected with the RapidIO switch chip through the RapidIO bus;

[0049] The FPGA node unpacks and pads the length field of the memory write or memory read sent by the user logic input to achieve RapidIO memory reading and writing of arbitrary byte length.

[0050] See also Figure 1 , configuring a RapidIO switching network, including a communication node, a RapidIO switching chip and an FPGA node; the communication node is interconnected with the RapidIO switching chip through a RapidIO bus; the FPGA node is interconnected with the RapidIO switching chip through a RapidIO bus;

[0051] In some embodiments, the communication node type may be any one of three different types of nodes: an FPGA node, a DSP node, and a PPC node;

[0052] In some embodiments, the FPGA node chip uses a domestically produced K7, V7, Z7 or higher Xilinx FPGA device or a corresponding domestically produced FPGA device;

[0053] In some embodiments, the RapidIO switch chip uses an imported RapidIO switch device or a corresponding domestically produced RapidIO switch device.

[0054] See also Figure 2 The FPGA node internally includes a RapidIO IP core, a memory write sending Send_nwrite control module, a memory read sending Send_nread control module, a data sending Send_data control module, a memory read response receiving Recv_resp_nread control module, a memory write receiving Recv_nwrite control module, a memory read receiving Recv_nread control module and a memory read response sending Send_resp_nread control module.

[0055] The overall working principle is as follows: after the system is powered on and initialized, the memory write and send Send_nwrite control module and the memory read and send Send_nread control module monitor the user logic in real time to start the memory write and send or start the memory read and send operation; the length field of the memory write and send or memory read and send input by the user logic is unpacked and filled with zeros. The data send Send_data control module receives the FIFO empty identification signal input by the memory write and send Send_nwrite control module and the memory read and send Send_nread control module to make a judgment, start the memory write and send or memory read and send operation, and send the RapidIO data packet of the memory write and send or memory read and send to the RapidIO switching network through the RapidIOIP core. The memory read response receiving Recv_resp_nread control module receives the RapidIO data packet input from the RapidIO switching network, extracts the RapidIO data packet returned by the memory read response, and writes it into the Recv_resp_nread data FIFO; according to the memory read send length User_send_nread_len, reads the Recv_resp_nread data FIFO, and outputs the memory read response receiving data User_recv_resp_nread_data and the memory read response receiving data byte valid signal User_recv_resp_nread_data_byte_valid to the user logic.

[0056] In the present invention, on the one hand, the FPGA node unpacks and fills the memory write data length input by the user logic, and sends it out through the memory write mode, and after all the user application data are sent, the actual length of the application data is sent out through the memory write mode; the receiving end unpacks the memory write RapidIO data packet input from the RapidIO IP core, and discards the received memory write excess byte data according to the actual length of the application data, thereby solving the problem of arbitrary byte length of memory write. On the other hand, the FPGA node unpacks and fills the memory read data length input by the user logic, and then sends the unpacked and filled data packet through the memory read mode, the FPGA node unpacks the input memory read response RapidIO data packet through the RapidIO IP core, and discards the received excess byte memory read response receiving data according to the actual length of the data to be read recorded locally, thereby solving the problem of arbitrary byte length of memory read.

[0057] Figure 2 In the memory write send Send_nwrite control module, on the one hand, receives the memory write send start signal User_send_nwrite_start, the memory write send data User_send_nwrite_data, the memory write send length User_send_nwrite_len, and the memory write send start address User_send_nwrite_addr input from the user; on the other hand, the input data is unpacked according to the memory write send length User_send_nwrite_len, and split into N 256-byte integer data packets + 1 non-256-byte tail packet, and the tail packet is padded in an 8-byte alignment manner; the unpacked and padded data packet data is written into the Send_nwrite data FIFO; and when each 256-byte integer data packet and the tail packet data packet are written, the lower 32 bits are written to the Send_nwrite length FIFO. The length of the split data packet is written, and the upper 32 bits are written to the start address of the split data.

[0058] Figure 2In the control module of memory read and send Send_nread, on the one hand, it receives the memory read and send start signal User_send_nread_start, the memory read and send length User_send_nread_len, and the memory read and send start address User_send_nread_addr inputted by the user; on the other hand, it unpacks the input memory read and send length User_send_nwrite_len; it splits it into N 256-byte integer data packets + 1 tail data packet of non-256-byte length, and the tail data packet is padded according to 256 bytes; and writes each memory read and send length (256 bytes) after unpacking and padded into the lower 32 bits of Send_nread FIFO, and writes each memory read and send start address into the higher 32 bits of Send_nread FIFO.

[0059] Figure 2 In the data sending Send_data control module, on the one hand, receives the memory write data packet sending FIFO empty signal Send_nwrite_packet_empty, memory write data packet sending data Send_nwrite_packet_data, memory write data packet sending Send_nwrite_packet_len, memory write data packet sending starting address Send_nwrite_packet_addr, and memory write data packet sending tail packet indication signal Send_nwrite_last_flag output from the memory write sending Send_nwrite control module; on the other hand, receives the memory read data packet sending FIFO empty signal Send_nread_packet_empty, memory read data packet sending Send_nread_packet_len, and memory read data packet sending starting address Send_nread_packet_addr output from the memory read sending Send_nread module. When either the memory write data packet send FIFO empty signal Send_nwrite_packet_empty or the memory read data packet send FIFO empty signal Send_nread_packet_empty is 0, the internal sending process is started; a memory write send RapidIO data packet or a memory read send RapidIO data packet is generated and sent to the RapidIO switching network through the RapidIO IP core.

[0060] Figure 2In the memory read response receiving Recv_resp_nread control module, it receives the data RIO_IP_in input from the RapidIO IP core, extracts the memory read response data by parsing the RapidIO data packet, and writes it into the Recv_resp_nread data FIFO. According to the memory read send length User_send_nread_len, it reads the Recv_resp_nread data FIFO, and outputs the memory read response receiving data User_recv_resp_nread_data and the memory read response receiving data byte valid signal User_recv_resp_nread_data_byte_valid to the user logic.

[0061] Figure 2 In the memory write receive Recv_nwrite control module, it receives the data RIO_IP_in input from the RapidIO IP core, extracts the memory write receive data by parsing the RapidIO data packet, and writes it into the Recv_nwrite data FIFO; the extracted memory write receive data length User_recv_nwrite_len and the memory write receive data starting address User_recv_nwrite_addr are output to the user logic; according to the memory write receive data length User_recv_nwrite_len, the Recv_nwrite data FIFO is read, and the memory write receive data User_recv_nwrite_data and the memory write receive data byte valid signal User_recv_nwrite_data_byte_valid are output to the user logic.

[0062] Figure 2 In the example, the memory read receive Recv_nread control module receives the data RIO_IP_in input from the RapidIO IP core, extracts the memory read receive length Recv_nread_len and the memory read receive address Recv_nread_addr by parsing the RapidIO data packet, and then generates a memory read receive start signal Recv_nread_start.

[0063] Figure 2In the process, the memory read response sending Send_resp_nread control module receives the memory read receiving start signal Recv_nread_start output by the memory read receiving Recv_nread control module, and sends the memory read response data User_send_resp_nread_data from the user logic to the RapidIO switching network through the RapidIO IP core according to the memory read receiving length Recv_nread_len and the memory read receiving address Recv_nread_addr.

[0064] See also Figure 3 , the memory write send Send_nwrite control module enters the initial state after the power-on reset is completed, and then determines whether the user logic starts the memory write. If the user logic starts the memory write, it determines whether the length of the data to be sent is greater than 256 bytes:

[0065] If the length of the data to be sent is greater than 256 bytes, 256 bytes of data are written to the Send_nwrite data FIFO, and then the lower 32 bits of the Send_nwrite length FIFO are written with 256, and the upper 32 bits are written with the starting address of the data to be sent, and then the length of the data to be sent and the starting address of the data to be sent are updated, and then it is determined whether the length of the data to be sent is greater than 256 bytes, and the above process is repeated;

[0066] If the length of the data to be sent is not greater than 256 bytes, the length of the data to be sent will be padded with zeros according to 8 bytes, and then the aligned and padded data will be written to the Send_nwrite data FIFO. Then, the lower 32 bits of the aligned and padded data length will be written to the Send_nwrite length FIFO, and the upper 32 bits will be written to the starting address of the data to be sent, and finally the initial state will be returned.

[0067] See also Figure 4 , the memory read send Send_nread control module enters the initial state after the power-on reset is completed, and then determines whether the user logic starts the memory read. If the user logic starts the memory read, it determines whether the length of the data to be read is greater than 256 bytes:

[0068] If the length of the data to be read is greater than 256 bytes, the length 256 is written to the lower 32 bits of the Send_nread FIFO, and the starting address status of the data to be read is written to the upper 32 bits. Then the length of the data to be read and the starting address status of the data to be read are updated, and then it is determined whether the length of the data to be read is greater than 256 bytes, and the above process is repeated.

[0069] If the length of the data to be read is not greater than 256 bytes, the length of the data to be read will be aligned and padded with zeros, and then the lower 32 bits of the aligned and padded data length 256 will be written to the Send_nread FIFO, and the upper 32 bits will be written to the starting address of the data to be read, and then the initial state will be returned.

[0070] See also Figure 5 , the data sending Send_data control module enters the initial state after the power-on reset is completed, and then determines whether the memory read data packet send FIFO empty signal Send_nread_packet_empty is 0:

[0071] If the memory read packet sending FIFO empty signal Send_nread_packet_empty is 0, a memory read RapidIO packet is generated, and then it is determined whether a memory read response is received. If a memory read response is received, it returns to the initial state; otherwise, it is determined whether the memory read response has timed out. If so, it returns to the initial state;

[0072] If the memory read data packet sends the FIFO empty signal Send_nread_packet_empty is not 0, then determine whether the memory write data packet sends the FIFO empty signal Send_nwrite_packet_empty is 0, if the memory write data packet sends the FIFO empty signal Send_nwrite_packet_empty is not 0, then return to the initial state; if the memory write data packet sends the FIFO empty signal Send_nwrite_packet_empty is 0, then determine whether the memory write data packet sends the last packet indication identification signal Send_nwrite_last_flag is 0, if the memory write data packet sends the last packet indication identification signal Send_nwrite_last_flag is 0, then generate a RapidIO data packet with a memory write length of 256 bytes, and then return to the initial state;

[0073] If the memory write data packet sending tail packet indication identification signal Send_nwrite_last_flag is not 0, it is determined whether the memory write data packet sending length Send_nwrite_packet_len is equal to 256. If the memory write data packet sending length Send_nwrite_packet_len is equal to 256, a memory write tail packet RapidIO data packet with a length of 256 bytes is generated, and then the memory write receiving data length User_send_nwrite_len is sent to the recipient in the form of memory write, and then a doorbell is sent to the recipient, and then it is determined whether a doorbell response is received. If a doorbell response is received, it returns to the initial state; if no doorbell response is received, it is determined whether the doorbell response has timed out. If it has timed out, it returns to the initial state.

[0074] If the memory write data packet sending length Send_nwrite_packet_len is not equal to 256, then determine whether the memory write data packet sending length Send_nwrite_packet_len is equal to 128. If the memory write data packet sending length Send_nwrite_packet_len is equal to 128, generate a RapidIO data packet with a memory write length of 128 bytes, and then update the length of the data to be sent; then determine whether the length of the data to be sent is greater than or equal to 64. If the length of the data to be sent is greater than or equal to 64, generate a RapidIO data packet with a memory write length of 64 bytes, and then update the length of the data to be sent; if the length of the data to be sent is less than 64, then determine whether the length of the data to be sent is greater than or equal to 32. If the length of the data to be sent is greater than or equal to 32, generate a RapidIO data packet with a memory write length of 32 bytes. apidIO data packet, and then update the length of the data to be sent. If the length of the data to be sent is less than 32, it is determined whether the length of the data to be sent is greater than or equal to 16. If the length of the data to be sent is greater than or equal to 16, a RapidIO data packet with a memory write length of 16 bytes is generated, and then the state of the length of the data to be sent is updated; if the length of the data to be sent is less than 16, it is determined whether the length of the data to be sent is greater than or equal to 8. If the length of the data to be sent is greater than or equal to 8, a RapidIO data packet with a memory write length of 8 bytes is generated, and then the memory write receive data length User_send_nwrite_len is sent to the recipient in memory write mode, and then a doorbell is sent to the recipient, and then it is determined whether a doorbell response is received. If a doorbell response is received, it returns to the initial state; if no doorbell response is received, it is determined whether the doorbell response has timed out. If it has timed out, it returns to the initial state.

[0075] Figure 5 In the process, if the length of the data to be sent is less than 8, User_send_nwrite_len is sent to the receiver in memory write mode, and then the doorbell is sent to the receiver, and then it is determined whether a doorbell response is received. If a doorbell response is received, it returns to the initial state; if no doorbell response is received, it is determined whether the doorbell response has timed out. If so, it returns to the initial state.

[0076] See also Figure 6, the memory read response receiving Recv_resp_nread control module enters the initial state after the power-on reset is completed, and then determines whether the received RapidIO data packet is a memory read response. If the received RapidIO data packet is a memory read response, the received memory read response RapidIO data packet is written into the Recv_resp_nread data FIFO, and then determines whether all the current memory read response RapidIO data packets are written into the Recv_resp_nread data FIFO. If all the current memory read response RapidIO data packets are written into the Recv_resp_nread data FIFO, it determines whether the data length written into the Recv_resp_nread data FIFO is greater than or equal to the memory read reception and transmission length User_send_nread_len:

[0077] If the data length written to the Recv_resp_nread data FIFO is greater than or equal to the memory read receive send length User_send_nread_len, the Recv_resp_nread data FIFO is read according to the memory read receive send length User_send_nread_len, the data byte valid identification status is given, and then it is determined whether the Recv_resp_nread data FIFO is read empty. If the Recv_resp_nread data FIFO is read empty, the receive response data length count status is cleared, and then the initial state is returned.

[0078] If the length of the data written to the Recv_resp_nread data FIFO is less than User_send_nread_len, the process returns to determine whether the received RapidIO data packet is a memory read response, and the above process is repeated.

[0079] See also Figure 7 , the memory write receiving Recv_nwrite control module enters the initial state after the power-on reset is completed, and then determines whether the received RapidIO data packet is a memory write:

[0080] If the received RapidIO data packet is a memory write, determine whether the received RapidIO data packet is a length data packet. If the received RapidIO data packet is a length data packet, record the actual data length User_recv_nwrite_len sent by the sender, and then read the Recv_nwrite data FIFO according to the actual data length User_recv_nwrite_len sent, give the data byte valid flag User_recv_nwrite_byte_valid, and then return to the initial state.

[0081] If the received RapidIO data packet is not a memory write, the received data is written into the Recv_nwrite data FIFO, and then the process returns to determine whether the received RapidIO data packet is a memory write, and the above process is repeated.

[0082] See also Figure 8 The memory read receiving Recv_nread control module enters the initial state after the power-on reset is completed, and then determines whether the received RapidIO data packet is a memory read. If the received RapidIO data packet is a memory read, it records the address to be read Recv_nread_addr and the length to be read Recv_nread_len, and then returns to the initial state.

[0083] See also Fig. 9 , the memory read response sends Send_resp_nread. The control module enters the initial state after the power-on reset is completed, and then determines whether Recv_resp_start is valid. If Recv_resp_start is valid, a memory read response packet is generated according to the address to be read Recv_nread_addr and the length to be read Recv_nread_len, and then returns to the initial state.

[0084] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for implementing RapidIO memory reading and writing arbitrary byte lengths, characterized in that: include: Both the communication nodes and FPGA nodes are interconnected with the RapidIO switch chip through the RapidIO bus; The FPGA node unpacks and pads the length field of the memory write or memory read sent by the user logic input to achieve RapidIO memory reading and writing of arbitrary byte length.

2. The method for realizing RapidIO memory reading and writing arbitrary byte length according to claim 1, characterized in that: The FPGA node internally includes a RapidIO IP core, a memory write sending Send_nwrite control module, a memory read sending Send_nread control module, a data sending Send_data control module, a memory read response receiving Recv_resp_nread control module, a memory write receiving Recv_nwrite control module, a memory read receiving Recv_nread control module and a memory read response sending Send_resp_nread control module.

3. The method for realizing RapidIO memory reading and writing arbitrary byte length according to claim 2, characterized in that: The memory write send Send_nwrite control module receives a memory write send start signal, memory write send data, memory write send length, and memory write send start address input from a user on the one hand; on the other hand, unpacks the input data according to the memory write send length, splits it into N integer data packets + 1 tail packet data packet, and performs a padding operation on the tail packet data packet; the unpacked and padded data packet data is written into the data FIFO; When the integer data packet and the tail data packet are written, the length of the split data packet is written to the lower 32 bits of the length FIFO, and the starting address of the split data is written to the upper 32 bits.

4. The method for realizing RapidIO memory reading and writing arbitrary byte length according to claim 2, characterized in that: The memory read and send Send_nread control module receives a memory read and send start signal, a memory read and send length, and a memory read and send start address input by a user on the one hand; on the other hand, it unpacks the input memory read and send length, splits it into N integer data packets + 1 tail packet data packet, and pads the tail packet data packet; and writes each memory read and send length after unpacking and padding into the lower 32 bits of the FIFO, and writes each memory read and send start address into the upper 32 bits of the FIFO.

5. The method for realizing RapidIO memory reading and writing arbitrary byte length according to claim 2, characterized in that: The data sending Send_data control module receives, on the one hand, a memory write data packet sending FIFO empty signal, a memory write data packet sending data, a memory write data packet sending, a memory write data packet sending starting address, and a memory write data packet sending tail packet indication identification signal outputted from a memory write sending Send_nwrite control module; on the other hand, receives a memory read data packet sending FIFO empty signal, a memory read data packet sending, and a memory read data packet sending starting address outputted from a memory read sending Send_nread module module; When either the FIFO empty signal of the memory write data packet transmission or the FIFO empty signal of the memory read data packet transmission is 0, the internal transmission process is started; Generate memory write and send RapidIO data packets or memory read and send RapidIO data packets, and send them to the RapidIO switching network through the RapidIO IP core.

6. The method for realizing RapidIO memory reading and writing arbitrary byte length according to claim 2, characterized in that: The memory read reception Recv_nread control module receives data input from the RapidIO IP core, extracts the memory read reception length and the memory read reception address by parsing the RapidIO data packet, and then generates a memory read reception start signal.

7. The method for realizing RapidIO memory reading and writing arbitrary byte length according to claim 2, characterized in that: The memory read response sending Send_resp_nread control module receives the memory read receiving start signal output from the memory read receiving Recv_nread control module, and sends the memory read response data from the user logic to the RapidIO switching network through the RapidIO IP core according to the memory read receiving length and the memory read receiving address.

8. The method for realizing RapidIO memory reading and writing arbitrary byte length according to claim 3, characterized in that: The memory write send Send_nwrite control module enters the initial state after the power-on reset is completed, and then determines whether the user logic starts the memory write. If the user logic starts the memory write, it determines whether the length of the data to be sent is greater than X bytes: If the length of the data to be sent is greater than X bytes, X bytes of data are written to the data FIFO, and then the lower 32 bits of the length FIFO are written to X, and the upper 32 bits are written to the starting address of the data to be sent, and then the length of the data to be sent and the starting address of the data to be sent are updated, and then it is determined whether the length of the data to be sent is greater than X bytes, and the above process is repeated; If the length of the data to be sent is not greater than X bytes, the length of the data to be sent will be padded with zeros according to 8 bytes, and then the data after alignment and padding will be written into the data FIFO. Then, the length of the data after alignment and padding will be written into the length FIFO in the lower 32 bits, and the starting address of the data to be sent will be written into the upper 32 bits. Finally, the system returns to the initial state.

9. The method for realizing RapidIO memory reading and writing arbitrary byte length according to claim 4, characterized in that: The memory read send_nread control module enters the initial state after the power-on reset is completed, and then determines whether the user logic starts the memory read. If the user logic starts the memory read, it determines whether the length of the data to be read is greater than X bytes: If the length of the data to be read is greater than X bytes, the length X is written to the lower 32 bits of the FIFO, and the starting address status of the data to be read is written to the upper 32 bits. Then the length of the data to be read and the starting address status of the data to be read are updated, and then it is determined whether the length of the data to be read is greater than X bytes, and the above process is repeated; If the length of the data to be read is not greater than X bytes, the length of the data to be read will be aligned and padded with zeros. Then, the lower 32 bits of the aligned and zero-padded data length X will be written to the FIFO, and the upper 32 bits will be written to the starting address of the data to be read, and then the initial state will be returned.

10. The method for realizing RapidIO memory reading and writing arbitrary byte length according to claim 5, characterized in that: The data sending Send_data control module enters the initial state after the power-on reset is completed, and then determines whether the memory read data packet sending FIFO empty signal is 0: If the FIFO empty signal sent by the memory read data packet is 0, a memory read RapidIO data packet is generated, and then it is determined whether a memory read response is received. If a memory read response is received, it returns to the initial state; Otherwise, determine whether the memory read response has timed out, and if so, return to the initial state; If the memory read data packet sends the FIFO empty signal is not 0, then determine whether the memory write data packet sends the FIFO empty signal is 0. If the memory write data packet sends the FIFO empty signal is not 0, then return to the initial state; If the memory write data packet sends the FIFO empty signal is 0, determine whether the memory write data packet sends the last packet indication identification signal is 0, if the memory write data packet sends the last packet indication identification signal is 0, generate a memory write length X bytes of RapidIO data packet, and then return to the initial state; If the memory write data packet sending tail packet indication identification signal is not 0, determine whether the memory write data packet sending length is equal to X. If the memory write data packet sending length is equal to X, generate a memory write tail packet RapidIO data packet with a length of X bytes, and then send the memory write receiving data length to the receiver in the memory write mode, and then send a doorbell to the receiver, and then determine whether a doorbell response is received. If a doorbell response is received, return to the initial state; If no doorbell response is received, determine whether the doorbell response has timed out. If so, return to the initial state; If the memory write data packet sending length is not equal to X, the memory write data packet sending length is determined by half of the length each time until the shortest length is reached. Each time, a RapidIO data packet of the corresponding length is generated, and then the length of the data to be sent is updated. Then, the memory write receiving data length is sent to the receiver in the form of memory write, and then a doorbell is sent to the receiver. Then, it is determined whether a doorbell response is received. If a doorbell response is received, the system returns to the initial state. If no doorbell response is received, it is determined whether the doorbell response has timed out. If so, the system returns to the initial state.

11. The method for realizing RapidIO memory reading and writing arbitrary byte length according to claim 2, characterized in that: The memory read response receiving Recv_resp_nread control module enters the initial state after the power-on reset is completed, and then determines whether the received RapidIO data packet is a memory read response. If the received RapidIO data packet is a memory read response, the received RapidIO data packet of the memory read response is written into the Recv_resp_nread data FIFO, and then determines whether all the RapidIO data packets of the current memory read response are written into the FIFO. If all the RapidIO data packets of the current memory read response are written into the FIFO, it is determined whether the data length written into the FIFO is greater than or equal to the memory read receiving and sending length: If the data length written into FIFO is greater than or equal to the memory read receive send length, the data byte valid identification status is given according to the read FIFO, and then it is determined whether the FIFO is read empty. If the FIFO is read empty, the receive response data length count status is cleared, and then the initial state is returned; If the length of the data written to the FIFO is less than the length of the memory read reception and transmission, the process returns to determine whether the received RapidIO data packet is a memory read response, and the above process is repeated.

12. The method for realizing RapidIO memory reading and writing arbitrary byte length according to claim 2, characterized in that: The memory write receiving Recv_nwrite control module enters the initial state after the power-on reset is completed, and then determines whether the received RapidIO data packet is a memory write: If the received RapidIO data packet is a memory write, determine whether the received RapidIO data packet is a length data packet. If the received RapidIO data packet is a length data packet, record the actual length of the data sent by the sender, then read the FIFO according to the actual length of the data sent, give a valid data byte flag, and then return to the initial state; If the received RapidIO data packet is not a memory write, the received data is written into the FIFO, and then the process returns to determine whether the received RapidIO data packet is a memory write, and the above process is repeated.

13. The method for realizing RapidIO memory reading and writing arbitrary byte length according to claim 2, characterized in that: The memory read receiving Recv_nread control module enters the initial state after power-on reset is completed, and then determines whether the received RapidIO data packet is a memory read. If the received RapidIO data packet is a memory read, it records the address to be read and the length to be read, and then returns to the initial state.

14. The method for realizing RapidIO memory reading and writing arbitrary byte length according to claim 13, characterized in that: The memory read response sending Send_resp_nread control module enters the initial state after the power-on reset is completed, and then determines whether Recv_resp_start is valid. If Recv_resp_start is valid, a memory read response packet is generated according to the address to be read and the length to be read, and then returns to the initial state.

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