Electronic package and fabrication method thereof

Abstract

An electronic package and a method of fabricating the same, the electronic package including: a first wiring module including a dielectric material, a first wiring layer, a second wiring layer, a third wiring layer, and a fourth wiring layer; the first electronic element is embedded in the first circuit module and is electrically connected with the fourth circuit layer; the second circuit module is electrically connected with the first circuit layer; and the second electronic element is positioned between the first circuit layer and the second circuit module. According to the embodiment of the invention, the overall thickness of the electronic package can be greatly reduced, so that the space is saved; the heat dissipation effect of electronic components can be improved, so that the service life is prolonged; and the process can be effectively simplified, the yield and the production rate are improved, and the manufacturing cost is reduced.

Description

Technical Field

[0001] The invention relates to an electronic package and a manufacturing method thereof, and in particular to an electronic package capable of reducing the overall thickness and a manufacturing method thereof. Background Art

[0002] Due to the widespread popularity and rapid development of smart mobile communication devices and wearable devices, the requirements for the semiconductor components used in related products are becoming more and more stringent. On the one hand, the number of components contained therein must be increased to improve processing speed and performance, and on the other hand, the area and volume need to be reduced to save space. In this context, package structures and packaging technologies such as package on package (PoP) architecture are widely used in semiconductor components.

[0003] Figure 1 FIG. 1 is a cross-sectional view of an existing electronic package 1. Figure 1 As shown, the electronic package 1 includes a first circuit module 11 and a second circuit module 12. The first circuit module 11 may be, for example, a memory module including memory chips 112 and 113. The second circuit module 12 may be, for example, a logic module including electronic components such as semiconductor chips 121. The first circuit module 11 is combined with the upper part of the second circuit module 12 by a first conductive member 111 of a plurality of solder balls, and then a solder ball is set on the bottom surface of the second circuit module 12 as a second conductive member 122, thereby forming an electronic package 1 such as a ball grid array (BGA) packaging module.

[0004] However, in the existing electronic package 1, the height of the electronic package 1 cannot be reduced to be thinned due to the height limitation of the electronic components on the surface of the second circuit module 12 located below, so that the electronic package 1 needs to occupy a larger space in products such as mobile communication devices. In addition, since the overall thickness cannot be reduced, it is also impossible to increase the total number of components in the electronic package 1 by stacking more layers of circuit modules and / or components to improve the overall processing performance. In addition, since the components located between the first circuit module 11 and the second circuit module 12 usually still need to be at least partially coated with molded materials or bottom glue UF, when other circuit modules are arranged above them, it will lead to poor heat dissipation, resulting in a reduction in their performance and life.

[0005] Therefore, how to overcome the various problems of the above-mentioned prior art has become a topic that needs to be solved urgently. Summary of the invention

[0006] In view of the various deficiencies of the above-mentioned prior art, the present invention provides an electronic package, comprising: a first circuit module, which includes a dielectric material having a first surface and a second surface opposite to each other; a first circuit layer, a second circuit layer and a third circuit layer formed in the dielectric material; a fourth circuit layer formed on the second surface; and a first electronic component disposed in the dielectric material and electrically connected to the fourth circuit layer, wherein the first circuit layer and the first surface are coplanar; a second electronic component disposed on the first surface of the dielectric material and electrically connected to the first circuit layer; and a second circuit module disposed above the first surface of the dielectric material and electrically connected to the first circuit layer, so that the second electronic component is located between the first circuit module and the second circuit module.

[0007] In one embodiment, the dielectric material is a Mirin build-up layer film.

[0008] In a specific embodiment, the dielectric material includes a first insulating layer covering the first circuit layer; a second insulating layer formed on the first insulating layer and covering the second circuit layer; and a third insulating layer formed on the second insulating layer and covering the third circuit layer.

[0009] In a specific embodiment, the first circuit module also includes a plurality of conductive blind holes formed in the dielectric material to electrically connect the first circuit layer with the second circuit layer, electrically connect the second circuit layer with the third circuit layer, electrically connect the third circuit layer with the fourth circuit layer, and electrically connect the first electronic component with the fourth circuit layer.

[0010] In one embodiment, the first electronic component is a memory chip.

[0011] In a specific embodiment, the second circuit module includes a thin substrate having a core layer.

[0012] In a specific embodiment, the thickness of the substrate is less than or equal to 40 um.

[0013] In a specific embodiment, the electronic package further includes a solder mask formed on the first surface and the second surface of the dielectric material to expose a portion of the first circuit layer and each of the fourth circuit layers.

[0014] In a specific embodiment, the electronic package further includes a plurality of first conductive bumps electrically connecting the first circuit layer and the second circuit module.

[0015] In a specific embodiment, the electronic package further includes a plurality of second conductive bumps electrically connecting the second electronic element and the first circuit layer.

[0016] The present invention also provides a method for manufacturing an electronic package, comprising: providing a first circuit module, which includes a dielectric material having a first surface and a second surface relative to each other; a first circuit layer, a second circuit layer and a third circuit layer formed in the dielectric material; a fourth circuit layer formed on the second surface; and a first electronic component disposed in the dielectric material and electrically connected to the fourth circuit layer, wherein the first circuit layer and the first surface are coplanar; arranging a second electronic component on the first surface of the dielectric material to electrically connect to the first circuit layer; and arranging a second circuit module above the first surface of the dielectric material and electrically connecting to the first circuit layer so that the second electronic component is located between the first circuit module and the second circuit module.

[0017] In a specific embodiment of the method for manufacturing the electronic package, the preparation of the first circuit module includes: forming a first circuit layer on a carrier; forming a first insulating layer on the carrier to cover the first circuit layer; forming a second circuit layer on the first insulating layer, and electrically connecting the second circuit layer to the first circuit layer; forming a second insulating layer on the first insulating layer and the second circuit layer to cover the second circuit layer; forming an opening in the second insulating layer to expose a portion of the second circuit layer, and placing the first electronic component; forming a third insulating layer on the second insulating layer and the third circuit layer and in the opening to cover the third circuit layer and the first electronic component; and forming a fourth circuit layer on the third insulating layer, and electrically connecting the fourth circuit layer to the third circuit layer.

[0018] In a specific embodiment of the method for manufacturing the electronic package, the dielectric material is a Mirin build-up layer film.

[0019] In a specific embodiment of the method for manufacturing the electronic package, the dielectric material includes the first insulating layer covering the first circuit layer; the second insulating layer formed on the first insulating layer and covering the second circuit layer; and the third insulating layer formed on the second insulating layer and covering the third circuit layer.

[0020] In a specific embodiment of the method for manufacturing the electronic package, the preparation of the first circuit module also includes: forming a plurality of conductive blind holes in the first insulating layer that electrically connect the first circuit layer and the second circuit layer; forming a plurality of conductive blind holes in the second insulating layer that electrically connect the second circuit layer and the third circuit layer, and forming a plurality of conductive blind holes in the third insulating layer that electrically connect the third circuit layer and the fourth circuit layer and electrically connect the first electronic component and the fourth circuit layer.

[0021] In a specific embodiment of the method for manufacturing the electronic package, the first electronic component is a memory chip.

[0022] In a specific embodiment of the method for manufacturing the electronic package, the second circuit module includes a thin substrate having a core layer.

[0023] In a specific embodiment of the method for manufacturing the electronic package, the thickness of the substrate is less than or equal to 40 um.

[0024] In a specific embodiment of the method for manufacturing the electronic package, a solder mask is further formed on the first surface and the second surface of the dielectric material to expose a portion of the first circuit layer and each of the fourth circuit layers.

[0025] In a specific embodiment of the method for manufacturing the electronic package, a plurality of first conductive bumps are formed to electrically connect the first circuit layer and the second circuit module.

[0026] In a specific embodiment of the method for manufacturing the electronic package, a plurality of second conductive bumps are formed to electrically connect the second electronic element and the first circuit layer.

[0027] As can be seen from the above, in the electronic package and its manufacturing method of the present invention, by embedding the first electronic component in a circuit module, using a thin substrate to form a second circuit module, and vertically stacking a plurality of circuit modules and a second electronic component, the overall thickness and occupied space of the electronic package using a stacked package (Package on a package, referred to as PoP) architecture can be greatly reduced. In addition, since there is no need to fill and set molding materials between the plurality of circuit modules and the second electronic component for molding, the process can be effectively simplified. In addition, since the second electronic component is not covered by the molding material and can directly contact the external atmosphere, it has a good heat dissipation effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a cross-sectional schematic diagram of an existing electronic package.

[0029] FIG. 2A to FIG. 2N It is a cross-sectional schematic diagram of an embodiment of a method for manufacturing an electronic package of the present invention.

[0030] The reference numerals are described as follows:

[0031] 1, 2: Electronic packaging

[0032] 2a: First surface

[0033] 2b: Second surface

[0034] 10: Barrier layer

[0035] 100: Opening area

[0036] 11, 2': First line module

[0037] 111: First conductive element

[0038] 112, 113: Memory chips

[0039] 12,5: Second line module

[0040] 121: Semiconductor grains

[0041] 122: Second conductive member

[0042] UF: Primer

[0043] 21: First circuit layer

[0044] 22: First insulation layer

[0045] 220, 240, 280: Blind hole

[0046] 23: Second circuit layer

[0047] 230, 250, 290: Conductive blind vias

[0048] 231: Chip pad

[0049] 24: Second insulation layer

[0050] 241,300: Open

[0051] 25: The third circuit layer

[0052] 26: First Electronic Components

[0053] 261: Electrical connection pad

[0054] 27: Binding layer

[0055] 28: The third insulation layer

[0056] 29: Fourth circuit layer

[0057] 30: Solder mask

[0058] 4: Second electronic component

[0059] 50: Substrate

[0060] 52: Fifth circuit layer

[0061] 53: Sixth circuit layer

[0062] 70: first conductive bump

[0063] 80: Second conductive bump

[0064] 6: Printed Circuit Board

[0065] 9: Bearing parts

[0066] 90: Plate body

[0067] 91: Release layer

[0068] 92: Metal layer. DETAILED DESCRIPTION

[0069] The following describes the implementation of the present invention by means of specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0070] It should be noted that the structures, proportions, sizes, etc. shown in the attached drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size, without affecting the effects and purposes that can be produced by the present invention, should still fall within the scope of the technical contents disclosed in the present invention. At the same time, the terms such as "on", "first", "second", "one", etc. quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical contents.

[0071] FIG. 2A to FIG. 2N It is a cross-sectional schematic diagram of an embodiment of a method for manufacturing an electronic package of the present invention.

[0072] like Figure 2A As shown, a carrier 9 is provided. The carrier 9 is a temporary carrier, which can be a plate having metal layers on opposite sides, such as a copper foil substrate, and a release layer 91 is provided on the surface of the plate body 90, and a metal layer 92 such as a copper layer is formed on the release layer 91. Then, a resist layer 10 having an opening area 100 is symmetrically formed on opposite sides of the carrier 9, so that part of the surface of the carrier 9 is exposed in the opening area 100.

[0073] like Figure 2B As shown, a first circuit layer 21 is formed on the metal layer 92 in the opening area 100. Next, the resist layer 10 is removed.

[0074] like Figure 2CAs shown, a first insulating layer 22 covering the first circuit layer 21 is formed on the metal layer 92 of the carrier 9, and then a plurality of blind holes 220 are formed in the first insulating layer 22 by, for example, laser perforation to expose a portion of the first circuit layer 21. The material of the first insulating layer 22 can be a dielectric material, such as Ajinomoto build-up film (ABF). Similarly, the selection of the material is also determined according to the requirements of the subsequent process or the final product, and this embodiment is not specific to this.

[0075] like Figure 2D As shown, copper is electroplated on the first insulating layer 22 and in the blind holes 220, and a second circuit layer 23 is formed on the first insulating layer 22 by a patterning process, and a plurality of conductive pillars such as conductive blind holes 230 electrically connecting the first circuit layer 21 and the second circuit layer 23 are formed in the blind holes 220 of the first insulating layer 22. In addition, the second circuit layer 23 also includes a die pad 231.

[0076] Then, Figure 2E As shown, a second insulating layer 24 is formed on the first insulating layer 22 and the second circuit layer 23 by, for example, lamination to cover the second circuit layer 23, and a plurality of blind holes 240 can also be formed in the second insulating layer 24 by, for example, laser perforation to expose part of the second circuit layer 23.

[0077] like Figure 2F As shown, copper material is electroplated on the second insulating layer 24 and in the blind hole 240, and a third circuit layer 25 is formed on the second insulating layer 24 using a patterning process, and a plurality of conductive columns such as conductive blind holes 250 electrically connecting the second circuit layer 23 and the third circuit layer 25 are formed in the blind hole 240 of the second insulating layer 24.

[0078] like Figure 2G As shown, an opening 241 exposing a portion of the second circuit layer 23 is formed in the second insulating layer 24 by mechanical processing, plasma etching or laser ablation, and the first electronic component 26 is placed, wherein the non-active surface of the first electronic component 26 can be fixed on the chip pad 231 by a bonding layer 27 such as an adhesive, and the active surface of the first electronic component 26 having an electrical connection pad 261 for power supply, grounding and / or signal transmission is exposed upward in the opening 241.

[0079] The first electronic component 26 may be a memory chip, such as a double data rate (DDR) memory chip. Based on the consideration of thinness, the thickness of the first electronic component 26 is less than or equal to 40 um.

[0080] like Figure 2H As shown, a third insulating layer 28 is formed on the second insulating layer 24 and the third wiring layer 25 and in the opening 241 by, for example, lamination to cover the third wiring layer 25 and the first electronic element 26. In a specific embodiment, the material used for the third insulating layer 28 is the same as that of the first insulating layer 22 and the second insulating layer 24, and can be a Mikoto build-up layer film.

[0081] like Fig.2I As shown, a plurality of blind holes 280 may be formed in the third insulating layer 28 by, for example, laser drilling to expose a portion of the third circuit layer 25 and the electrical connection pad 261 of the first electronic element 26. Copper material is then electroplated on the third insulating layer 28 and in the blind holes 280, and a fourth circuit layer 29 is formed on the third insulating layer 28 by a patterning process, and a plurality of conductive posts such as conductive blind holes 290 electrically connecting the third circuit layer 25 and the fourth circuit layer 29 are formed in the blind holes 280 of the third insulating layer 28.

[0082] like Figure 2J As shown, the plate body 90 of the carrier 9 and the metal layer 92 are separated by the release layer 91 to retain the metal layer 92 on the first insulating layer 22 and the first circuit layer 21 .

[0083] like Figure 2K As shown, the metal layer 92 is removed by etching to make the surfaces of the first wiring layer 21 and the first insulating layer 22 coplanar.

[0084] According to the above, a first circuit module 2' can be provided, comprising a dielectric material having a first surface 2a and a second surface 2b opposite to each other; a first circuit layer 21, a second circuit layer 23 and a third circuit layer 25 formed in the dielectric material; a fourth circuit layer 29 formed on the second surface 2b; and a first electronic component 26 disposed in the dielectric material and electrically connected to the fourth circuit layer 29, wherein the first circuit layer 21 is coplanar with the first surface 2a, wherein the dielectric material comprises the first insulating layer 22 covering the first circuit layer 21; the second insulating layer 24 formed on the first insulating layer 22 and covering the second circuit layer 23; and the third insulating layer 28 formed on the second insulating layer 24 and covering the third circuit layer 25. Moreover, the dielectric material can be a glutinous rice flour film. In addition, the thickness of the second insulating layer 24 is greater than that of the first insulating layer 22 and the third insulating layer 28.

[0085] For example Figure 2LAs shown, a solder mask 30 such as green paint is formed on the first surface 2a and the second surface 2b of the dielectric material to protect the first circuit layer 21 and the fourth circuit layer 29. In addition, the solder mask 30 is formed with a plurality of openings 300 to expose a portion of the first circuit layer 21 and each of the fourth circuit layers 29.

[0086] like Figure 2M As shown, a second electronic component 4 electrically connected to the first circuit layer 21 is disposed in the opening 300 on the first surface 2a of the dielectric material that exposes the first circuit layer 21. In this embodiment, the second electronic component 4 is a packaged semiconductor die. However, it can also be other active components or passive components required to meet the design purpose, and this embodiment has no limitation to this.

[0087] like Figure 2N As shown, the second circuit module 5 is disposed above the first surface 2 a of the dielectric material, and the first circuit layer 21 and the second circuit module 5 are electrically connected, so that the second electronic component 4 is located between the first circuit module 2 ′ and the second circuit module 5 .

[0088] Furthermore, in order to meet the requirements of thinness, the second circuit module 5 in this embodiment includes a thin substrate 50 having a core layer, and a fifth circuit layer 52 and a sixth circuit layer 53 formed on at least one side of the substrate 50 or on both sides as shown in the figure, and the first circuit layer 21 and the fifth circuit layer 52 are electrically connected by a plurality of first conductive bumps 70. In addition, the second electronic component 4 is electrically connected to the first circuit layer 21 by a plurality of second conductive bumps 80.

[0089] On the other hand, the electronic package 2 of the present invention can also be disposed on a printed circuit board 6 by means of the fourth circuit layer 29 of the first circuit module 2 ′.

[0090] As described above, the present invention provides an electronic package 2, comprising: a first circuit module 2', comprising a dielectric material having a first surface 2a and a second surface 2b opposite to each other; a first circuit layer 21, a second circuit layer 23 and a third circuit layer 25 formed in the dielectric material; a fourth circuit layer 29 formed on the second surface 2b; and a first electronic component 26 disposed in the dielectric material and electrically connected to the fourth circuit layer 29, wherein the first circuit layer 21 is coplanar with the first surface 2a; a second electronic component 4, which is disposed on the first surface 2a of the dielectric material and electrically connected to the first circuit layer 21; and a second circuit module 5, which is disposed above the first surface 2a of the dielectric material and electrically connected to the first circuit layer 21, so that the second electronic component 4 is located between the first circuit module 2' and the second circuit module 5.

[0091] In one embodiment, the dielectric material is a Mirin build-up layer film.

[0092] In a specific embodiment, the dielectric material includes a first insulating layer 22 covering the first circuit layer 21 ; a second insulating layer 24 formed on the first insulating layer 22 and covering the second circuit layer 23 ; and a third insulating layer 28 formed on the second insulating layer 24 and covering the third circuit layer 25 .

[0093] In a specific embodiment, the first circuit module 2' also includes a plurality of conductive blind vias 230 formed in the dielectric material to electrically connect the first circuit layer 21 and the second circuit layer 23, a plurality of conductive blind vias 250 to electrically connect the second circuit layer 23 and the third circuit layer 25, a plurality of conductive blind vias 290 to electrically connect the third circuit layer 25 and the fourth circuit layer 29, and to electrically connect the first electronic component 26 and the fourth circuit layer 29.

[0094] In one embodiment, the first electronic component 26 is a memory chip.

[0095] In a specific embodiment, the thickness of the first electronic element 26 is less than or equal to 40 um.

[0096] In a specific embodiment, the second circuit module 5 includes a thin substrate 50 having a core layer.

[0097] In a specific embodiment, the thickness of the substrate 50 is less than or equal to 40 um.

[0098] In a specific embodiment, the electronic package 2 further includes a solder mask 30 formed on the first surface 2 a and the second surface 2 b of the dielectric material, exposing a portion of the first circuit layer 21 and each of the fourth circuit layers 29 .

[0099] In a specific embodiment, the electronic package 2 further includes a plurality of first conductive bumps 70 electrically connecting the first circuit layer 21 and the second circuit module 5 .

[0100] In a specific embodiment, the electronic package 2 further includes a plurality of second conductive bumps 80 electrically connecting the second electronic component 4 and the first circuit layer 21 .

[0101] In summary, in the electronic package and its manufacturing method of the present invention, by embedding a first electronic component such as a DDR memory chip in a first circuit module, and using a thin substrate as a second circuit module, a plurality of circuit modules and a second electronic component are vertically stacked, and the overall thickness and occupied space of the electronic package 2 using a stacked package (Package on a package, referred to as PoP) architecture are greatly reduced, so that more space can be saved under the same architecture, or more components can be accommodated in the same space and / or more layers of circuit modules can be stacked, thereby obtaining a lighter, thinner, shorter or more efficient electronic package. And since there is no need to perform a molding process between adjacent circuit modules and the second electronic component to fill the molding material, the process can be effectively simplified, the production rate can be accelerated, the manufacturing yield can be improved, and the production cost can be reduced. In addition, since the second electronic component is not covered by the molding material and can directly contact the external atmosphere, it has a good heat dissipation effect, thereby ensuring the reliability and working efficiency of the electronic package, and at the same time, the overall life can be extended.

[0102] The above embodiments are only used to illustrate the principles and effects of the present invention, and are not used to limit the present invention. Those skilled in the art may modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the claims.

Claims

1. An electronic package, comprising: A first circuit module includes a dielectric material having a first surface and a second surface opposite to each other; A first circuit layer, a second circuit layer and a third circuit layer formed in the dielectric material; a fourth circuit layer formed on the second surface; and a first electronic component disposed in the dielectric material and electrically connected to the fourth circuit layer, wherein the first circuit layer is coplanar with the first surface; A second electronic component is disposed on the first surface of the dielectric material and is electrically connected to the first circuit layer; as well as The second circuit module is disposed above the first surface of the dielectric material and is electrically connected to the first circuit layer so that the second electronic component is located between the first circuit module and the second circuit module.

2. The electronic package of claim 1, wherein: The dielectric material is a Mijinomoto build-up layer film.

3. The electronic package of claim 1, wherein: The dielectric material includes a first insulating layer covering the first circuit layer; a second insulating layer formed on the first insulating layer and covering the second circuit layer; and a third insulating layer formed on the second insulating layer and covering the third circuit layer.

4. The electronic package of claim 1, wherein: The first circuit module also includes a plurality of conductive blind vias formed in the dielectric material to electrically connect the first circuit layer with the second circuit layer, electrically connect the second circuit layer with the third circuit layer, electrically connect the third circuit layer with the fourth circuit layer, and electrically connect the first electronic component with the fourth circuit layer.

5. The electronic package of claim 1, wherein: The first electronic component is a memory chip.

6. The electronic package of claim 1, wherein: The second circuit module includes a thin substrate with a core layer.

7. The electronic package of claim 6, wherein: The thickness of the substrate is less than or equal to 40um.

8. The electronic package of claim 1, wherein: The electronic package also includes a solder mask formed on the first surface and the second surface of the dielectric material to expose a portion of the first circuit layer and each of the fourth circuit layers.

9. The electronic package of claim 1, wherein: The electronic package also includes a plurality of first conductive bumps electrically connecting the first circuit layer and the second circuit module.

10. The electronic package of claim 1, wherein: The electronic package also includes a plurality of second conductive bumps electrically connecting the second electronic element and the first circuit layer.

11. A method for manufacturing an electronic package, comprising: Providing a first circuit module, which includes a dielectric material having a first surface and a second surface opposite to each other; A first circuit layer, a second circuit layer and a third circuit layer formed in the dielectric material; a fourth circuit layer formed on the second surface; and a first electronic component disposed in the dielectric material and electrically connected to the fourth circuit layer, wherein the first circuit layer is coplanar with the first surface; Disposing a second electronic component on the first surface of the dielectric material to electrically connect to the first circuit layer; and A second circuit module is disposed above the first surface of the dielectric material and electrically connected to the first circuit layer so that the second electronic component is located between the first circuit module and the second circuit module.

12. The method for manufacturing an electronic package according to claim 11, wherein: The preparation of the first circuit module includes: forming the first circuit layer on a carrier; forming a first insulating layer covering the first circuit layer on the carrier; forming the second circuit layer on the first insulating layer, and making the second circuit layer electrically connected to the first circuit layer; forming a second insulating layer on the first insulating layer and the second circuit layer to cover the second circuit layer; Forming an opening in the second insulating layer to expose a portion of the second circuit layer, and placing the first electronic element thereon; forming a third insulating layer on the second insulating layer and the third circuit layer and in the opening to cover the third circuit layer and the first electronic element; and The fourth circuit layer is formed on the third insulating layer, and the fourth circuit layer is electrically connected to the third circuit layer.

13. The method for manufacturing an electronic package according to claim 11, wherein: The dielectric material is a Mijinomoto build-up layer film.

14. The method for manufacturing an electronic package according to claim 12, wherein: The dielectric material includes the first insulating layer covering the first circuit layer; the second insulating layer formed on the first insulating layer and covering the second circuit layer; and the third insulating layer formed on the second insulating layer and covering the third circuit layer.

15. The method for manufacturing an electronic package according to claim 12, wherein: The preparation of the first circuit module also includes: forming a plurality of conductive blind holes in the first insulating layer to electrically connect the first circuit layer and the second circuit layer; forming a plurality of conductive blind holes in the second insulating layer to electrically connect the second circuit layer and the third circuit layer, and forming a plurality of conductive blind holes in the third insulating layer to electrically connect the third circuit layer and the fourth circuit layer and to electrically connect the first electronic component and the fourth circuit layer.

16. The method for manufacturing an electronic package according to claim 11, wherein: The first electronic component is a memory chip.

17. The method for manufacturing an electronic package according to claim 11, wherein: The second circuit module includes a thin substrate with a core layer.

18. The method for manufacturing an electronic package according to claim 17, wherein: The thickness of the substrate is less than or equal to 40um.

19. The method for manufacturing an electronic package according to claim 11, wherein: The manufacturing method also includes forming a solder resist layer on the first surface and the second surface of the dielectric material to expose a portion of the first circuit layer and each of the fourth circuit layers.

20. The method for manufacturing an electronic package according to claim 11, wherein: The manufacturing method further includes forming a plurality of first conductive bumps to electrically connect the first circuit layer and the second circuit module.

21. The method for manufacturing an electronic package according to claim 11, wherein: The manufacturing method further includes forming a plurality of second conductive bumps to electrically connect the second electronic element and the first circuit layer.

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