IGBT digital driving system and control method thereof

Abstract

The invention relates to the technical field of power electronics, in particular to an IGBT (insulated gate bipolar transistor) digital driving system and a control method thereof, and the control method comprises the following steps: an SPI (serial peripheral interface) host established by an FPGA (field programmable gate array) adjusts driving parameters of an ASIC (application specific integrated circuit) digital driving chip and / or an EEPROM (electrically erasable programmable read-only memory) chip through an SPI interface, or reads operating parameters of the ASIC digital driving chip, and sends a corresponding control instruction to the ASIC digital driving chip; the ASIC digital driving chip interprets and executes the control instruction through an SPI (Serial Peripheral Interface); and the EEPROM chip stores the driving parameters through an I2C interface, or reads and returns the stored driving parameters to the ASIC digital driving chip. According to the technical scheme provided by the invention, the digital driving circuit can automatically store the driving parameters under the condition of power failure and recover the parameters after the system is powered on again. Meanwhile, a user-friendly upper computer interface for online parameter adjustment is further provided, and an operator is allowed to adjust driving parameters according to real-time feedback so as to optimize system performance.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronics, and in particular to an IGBT digital drive system and a control method thereof. Background Art

[0002] With the rapid development of power electronics technology, insulated gate bipolar transistors (IGBTs) have been widely used in motor drives, power converters, solar inverters, etc. due to their high efficiency and high power density. However, existing IGBT digital drive circuits have some limitations in design and application, especially in online monitoring and power-off recovery.

[0003] Traditional IGBT digital drive circuits usually lack effective online monitoring functions, which makes it difficult to monitor and adjust drive parameters in real time in practical applications, such as fault judgment time, fault start delay, IGBT turn-on or turn-off time, etc., to adapt to different working conditions and load changes. In addition, once a power outage occurs, the existing circuits are often unable to save the modified drive parameters, resulting in the need to reset the parameters when the system is restarted, which not only increases the complexity of operation, but also affects the stability and reliability of the system.

[0004] Although there have been some studies and attempts to address these issues, most solutions still have problems such as high cost, complex operation or poor compatibility. Summary of the invention

[0005] In order to overcome the above defects, the present invention proposes an IGBT digital drive system and a control method thereof.

[0006] In a first aspect, an IGBT digital drive system is provided, the IGBT digital drive system comprising:

[0007] SPI host, ASIC digital driver chip and EEPROM chip built by FPGA;

[0008] The SPI host is used to adjust the driving parameters of the ASIC digital driver chip and / or the EEPROM chip through the SPI interface, or read the operating parameters of the ASIC digital driver chip, and send corresponding control instructions to the ASIC digital driver chip;

[0009] The ASIC digital driver chip is used to interpret and execute the control instructions through the SPI interface;

[0010] The EEPROM chip is used to save the driving parameters through the I2C interface, or read the saved driving parameters and return them to the ASIC digital driving chip.

[0011] Preferably, the control instruction is a 24-bit code, wherein the lower 16 bits are a data field, the lower 15 bits of the data field are used to store the specific value of the drive parameter to be adjusted, the highest bit of the data field indicates whether the drive parameter to be adjusted is written into the control bit of the EEPROM chip, the upper 8 bits are an address field, the lower 7 bits of the address field indicate the SPI address corresponding to the drive parameter to be adjusted, and the highest bit of the address field indicates the read-write control bit.

[0012] Furthermore, when the highest bit of the data field is 0, it indicates that the driving parameters are transmitted to the driver of the ASIC digital driver chip and the EEPROM chip at the same time; when the highest bit of the data field is 1, it indicates that the driving parameters are transmitted only to the driver of the ASIC digital driver chip.

[0013] Furthermore, when the highest bit of the address field is 0, it indicates that the driving parameters are written into the corresponding target according to the highest bit of the data field, and when the highest bit of the address field is 1, it indicates that the operating parameters of the ASIC digital driving chip are read.

[0014] Preferably, the ASIC digital driver chip comprises: a first-in first-out module, a data mapping module, a switch module, an SPI interface module, an I2C interface module and a driver;

[0015] The first-in first-out module is used to perform rate matching, bit width matching and data screening on data transmitted by the SPI interface and the I2C interface;

[0016] The data mapping module is used to map the drive parameters and their addresses with the storage space of the EEPROM;

[0017] The switch module is composed of switch 1 and switch 2, wherein switch 1 is used to control the communication connection when the ASIC chip reads the EEPROM chip data or writes the drive parameters into the driver, and switch 2 is used to control the communication connection when the drive parameters are written into the driver and / or when writing / reading the EEPROM chip;

[0018] The SPI interface module is used to receive the control instruction sent by the SPI host and translate the control instruction into an instruction format recognized by the switch module;

[0019] The I2C interface module is used to receive the address data pair written in the first-in first-out module and convert it into a standard I2C instruction format, or read it in reverse;

[0020] The driver is used to adjust a driving signal for controlling the IGBT according to the received driving parameters.

[0021] Furthermore, the data mapping module is specifically used to: expand the single-byte address Addr of the address domain into two bytes: (2×Addr, 2×Addr+1), and map it to the first-in-first-out module, each address byte marks the storage position of the lower 8-bit data adjacent to it in the EEPROM chip, and transmit the upper 16 bits and lower 16 bits of the first-in-first-out module through the I2C bus respectively, and save them in the EEPROM chip space corresponding to each address byte.

[0022] Furthermore, the initial state of the switch 1 is a communication connection when the ASIC chip is connected to read the data of the EEPROM chip.

[0023] Further, when the highest bit of the address field is 0 and the highest bit of the data field is 0, the switch 2 is connected to the communication connection when the drive parameter is written into the driver and when writing / reading the EEPROM chip;

[0024] When the highest bit of the address field is 0 and the highest bit of the data field is 1, switch 2 is connected to transmit the drive parameters to the driver of the ASIC digital driver chip;

[0025] When the highest bit of the address field is 1, the switch 2 is connected to the communication connection for reading the operating parameters of the ASIC digital driver chip.

[0026] In a second aspect, a control method based on the IGBT digital drive system is provided, the method comprising:

[0027] The SPI host built by FPGA adjusts the driving parameters of the ASIC digital driver chip and / or EEPROM chip through the SPI interface, or reads the operating parameters of the ASIC digital driver chip, and sends the corresponding control instructions to the ASIC digital driver chip;

[0028] The ASIC digital driver chip interprets and executes the control instructions through the SPI interface;

[0029] The EEPROM chip saves the driving parameters through the I2C interface, or reads out the saved driving parameters and returns them to the ASIC digital driving chip.

[0030] The above one or more technical solutions of the present invention have at least one or more of the following beneficial effects:

[0031] The present invention relates to the field of power electronics technology, and specifically provides an IGBT digital drive system and a control method thereof, including: an SPI host constructed by FPGA adjusts the drive parameters of an ASIC digital drive chip and / or an EEPROM chip through an SPI interface, or reads the operating parameters of the ASIC digital drive chip, and sends corresponding control instructions to the ASIC digital drive chip; the ASIC digital drive chip interprets and executes the control instructions through the SPI interface; the EEPROM chip saves the drive parameters through an I2C interface, or reads the saved drive parameters and returns them to the ASIC digital drive chip. The technical solution provided by the present invention is a digital drive circuit that can automatically save drive parameters in the event of a power outage, and restore these parameters after the system is powered on again. At the same time, a user-friendly upper computer interface for online parameter adjustment is also provided, allowing the operator to adjust the drive parameters according to real-time feedback to optimize system performance, specifically:

[0032] By using EEPROM as non-volatile storage, the present invention ensures that important drive parameters will not be lost in the event of a sudden power failure. When the system is reset or restarted, these parameters can be automatically restored from the EEPROM, thereby ensuring the continuous operation and stability of the system. This mechanism significantly reduces system failures and restart time caused by parameter loss, and improves overall reliability.

[0033] The present invention provides an intuitive and flexible user interaction method through physical switches and SPI interfaces. Users can easily switch between different operation modes, such as reading parameters from EEPROM or updating parameters in real time through the SPI interface. In addition, the real-time monitoring function of the host computer enables users to understand the system status at any time and make adjustments quickly as needed, greatly improving the user experience and the convenience of operation.

[0034] The design of the FIFO buffer in the present invention effectively solves the difference in speed and bit width between the SPI and I2C buses, and improves the efficiency of data transmission. By temporarily storing, splitting and splicing data, the FIFO ensures the smoothness and accuracy of data transmission between different buses, avoiding data congestion and loss. In addition, the data screening function allows the system to selectively save data according to the flag bit set by the user, further improving the flexibility and efficiency of data processing.

[0035] The host computer of the present invention can read the status of the ASIC chip in real time through the SPI interface, including the current drive parameters and fault handling status. This real-time monitoring capability enables the user to understand the operating status of the system in a timely manner and make adjustments quickly when necessary. For example, if the system detects an abnormal situation, the user can immediately update the parameters or take other measures through the host computer, thereby achieving rapid response and problem solving, and ensuring the efficient operation of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a structural schematic diagram of an IGBT digital drive system according to an embodiment of the present invention;

[0037] Figure 2 1 is a schematic diagram of the SPI instruction format of an embodiment of the present invention;

[0038] Figure 3 It is an address mapping relationship diagram of the data mapping module according to an embodiment of the present invention. DETAILED DESCRIPTION

[0039] The specific implementation modes of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0040] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] As disclosed in the background technology, with the rapid development of power electronics technology, insulated gate bipolar transistors (IGBTs) have been widely used in motor drive, power converters, solar inverters, etc. due to their high efficiency and high power density. However, existing IGBT digital drive circuits have some limitations in the design and application process, especially in online monitoring and power-off state recovery.

[0042] Traditional IGBT digital drive circuits usually lack effective online monitoring functions, which makes it difficult to monitor and adjust drive parameters in real time in practical applications, such as fault judgment time, fault start delay, IGBT turn-on or turn-off time, etc., to adapt to different working conditions and load changes. In addition, once a power outage occurs, the existing circuits are often unable to save the modified drive parameters, resulting in the need to reset the parameters when the system is restarted, which not only increases the complexity of operation, but also affects the stability and reliability of the system.

[0043] Although there have been some studies and attempts to address these issues, most solutions still have problems such as high cost, complex operation or poor compatibility.

[0044] In order to improve the above-mentioned problems, the present invention relates to the field of power electronics technology, and specifically provides an IGBT digital drive system and a control method thereof, including: an SPI host constructed by FPGA adjusts the drive parameters of an ASIC digital drive chip and / or an EEPROM chip through an SPI interface, or reads the operating parameters of the ASIC digital drive chip, and sends corresponding control instructions to the ASIC digital drive chip; the ASIC digital drive chip interprets and executes the control instructions through the SPI interface; the EEPROM chip saves the drive parameters through an I2C interface, or reads the saved drive parameters and returns them to the ASIC digital drive chip. The technical solution provided by the present invention is a digital drive circuit that can automatically save drive parameters in the event of a power failure, and restore these parameters after the system is powered on again. At the same time, a user-friendly upper computer interface for online parameter adjustment is also provided, allowing the operator to adjust the drive parameters according to real-time feedback to optimize system performance, specifically:

[0045] By using EEPROM as non-volatile storage, the present invention ensures that important drive parameters will not be lost in the event of a sudden power failure. When the system is reset or restarted, these parameters can be automatically restored from the EEPROM, thereby ensuring the continuous operation and stability of the system. This mechanism significantly reduces system failures and restart time caused by parameter loss, and improves overall reliability.

[0046] The present invention provides an intuitive and flexible user interaction method through physical switches and SPI interfaces. Users can easily switch between different operation modes, such as reading parameters from EEPROM or updating parameters in real time through the SPI interface. In addition, the real-time monitoring function of the host computer enables users to understand the system status at any time and make adjustments quickly as needed, greatly improving the user experience and the convenience of operation.

[0047] The design of the FIFO buffer in the present invention effectively solves the difference in speed and bit width between the SPI and I2C buses, and improves the efficiency of data transmission. By temporarily storing, splitting and splicing data, the FIFO ensures the smoothness and accuracy of data transmission between different buses, avoiding data congestion and loss. In addition, the data screening function allows the system to selectively save data according to the flag bit set by the user, further improving the flexibility and efficiency of data processing.

[0048] The host computer of the present invention can read the status of the ASIC chip in real time through the SPI interface, including the current drive parameters and fault handling status. This real-time monitoring capability enables the user to understand the operating status of the system in a timely manner and make adjustments quickly when necessary. For example, if the system detects an abnormal situation, the user can immediately update the parameters or take other measures through the host computer, thereby achieving rapid response and problem solving, and ensuring the efficient operation of the system.

[0049] The above scheme is described in detail below.

[0050] Example 1

[0051] See attached Figure 1 , Figure 1 FIG. 1 is a schematic diagram of the structure of an IGBT digital drive system according to an embodiment of the present invention. Figure 1 As shown, it includes: SPI host built by FPGA, ASIC digital driver chip and EEPROM chip;

[0052] The SPI host is used to adjust the driving parameters of the ASIC digital driver chip and / or the EEPROM chip through the SPI interface, or read the operating parameters of the ASIC digital driver chip, and send corresponding control instructions to the ASIC digital driver chip;

[0053] The ASIC digital driver chip is used to interpret and execute the control instructions through the SPI interface;

[0054] The EEPROM chip is used to save the driving parameters through the I2C interface, or read the saved driving parameters and return them to the ASIC digital driving chip.

[0055] In this embodiment, FPGA (field programmable gate array) serves as the main controller (host computer) of the system, which can coordinate and manage the operation of the entire digital drive circuit. It realizes the logic control and data processing between the ASIC chip and the external communication interface. The host computer serves as the monitoring and configuration interface of the system, allowing the user to set parameters and monitor the system through the software interface, and can read the operating parameters of the ASIC driver chip in real time, and then write the driver parameters to be adjusted into the ASIC chip through the SPI interface according to user needs.

[0056] SPI is a high-speed serial communication interface used for data transmission between the host computer and EEPROM. Figure 2SPI instruction format diagram. SPI supports 24-bit address and data transmission, of which the lower 16 bits (including the upper 8-bit data Data H and the lower 8-bit data Data L) are the data field. The lower 15 bits of the data field ([14:0]) are used to save the specific value of the drive parameter to be adjusted. The highest bit of the data field (Data_MSB,

[15] ) indicates whether the drive parameter to be adjusted is written to the EEPROM. For example, 0 means that the drive parameter is passed to the driver and the parameter is saved in the EEPROM at the same time, so that the system can restore the driver parameters written to the EEPROM for the last time after the second power-on (Write Driver&PROM); 1 means that the drive parameter is only passed to the drive circuit (Only write Driver). This is usually used for the operator to make multiple attempts to adjust the drive parameters when the operator is not sure of the final appropriate drive parameters. The high 8 bits of SPI are the address field, and the low 7 bits of the address field ([22:16]) represent the SPI address corresponding to the drive parameter to be adjusted (each drive parameter corresponds to a unique SPI address). The highest bit (Addr_MSB,

[23] ) is the read / write control bit. 0 means that the host computer writes to the ASIC chip (SPI WR) (at this time, the target to be written is selected according to Data_MSB), and 1 means that the host computer reads the current operating parameters of the ASIC chip (SPI RD).

[0057] EEPROM (Electrically Erasable Programmable Read-Only Memory) is a non-volatile memory used to store the configuration parameters of the IGBT driver. After the system loses power, the parameters can be saved to ensure that the system can be restored to the previous state when it is restarted. It is connected to the ASIC chip through the I2C interface.

[0058] In this embodiment, the ASIC digital driver chip includes: a first-in first-out module, a data mapping module, a switch module, an SPI interface module, an I2C interface module and a driver;

[0059] The first-in first-out module is used to perform rate matching, bit width matching and data screening on data transmitted by the SPI interface and the I2C interface;

[0060] The data mapping module is used to map the drive parameters and their addresses with the storage space of the EEPROM;

[0061] The switch module is composed of switch 1 and switch 2, wherein switch 1 is used to control the communication connection when the ASIC chip reads the EEPROM chip data or writes the drive parameters into the driver, and switch 2 is used to control the communication connection when the drive parameters are written into the driver and / or when writing / reading the EEPROM chip;

[0062] The SPI interface module is used to receive the control instruction sent by the SPI host and translate the control instruction into an instruction format recognized by the switch module;

[0063] The I2C interface module is used to receive the address data pair written in the first-in first-out module and convert it into a standard I2C instruction format, or read it in reverse;

[0064] The driver is used to adjust a driving signal for controlling the IGBT according to the received driving parameters.

[0065] In one embodiment, the ASIC digital driver chip communicates with external devices through SPI and I2C interfaces, receives parameter configurations and performs corresponding drive control. Specifically, the ASIC chip (ASIC Chip) includes the following modules:

[0066] a. First-in-first-out module (FIFO)

[0067] The functional description of FIFO is as follows:

[0068] i. Rate matching: SPI transmission rate is faster (~1MHz), I2C transmission rate is slower (≤400kHz). When users write data to EEPROM through the host computer, FIFO can effectively alleviate data congestion caused by the mismatch of the two bus transmission rates and avoid data loss caused by overlap.

[0069] ii. Bit width matching: The SPI bus data width is 32 bits, and the I2C bus data width is 16 bits. FIFO can split the data written to the EEPROM or splice the data read from the EEPROM.

[0070] iii. Data screening: According to the data side flag bit (Data_MSB) provided by the user, the drive parameters that need to be written into the EEPROM are screened.

[0071] b. Data Mapping Module

[0072] Map the driver parameters and addresses of the user-side host computer to the storage space of the EEPROM. Figure 3This is the address mapping relationship diagram of the data mapping module. Since each drive parameter requires 16 bits of data space to save, it occupies 2 bytes of address space in FIFO, so it is necessary to independently address each byte of address space. The module first expands the single-byte address (Addr) of SPI into two bytes (2×Addr, 2×Addr+1) and maps it to FIFO. Each address byte marks the storage location of the lower 8 bits of data adjacent to it in EEPROM. Then, the upper 16 bits and lower 16 bits of FIFO are transmitted through the I2C bus respectively, and then saved in the EEPROM space corresponding to each address byte.

[0073] c. Switch module

[0074] It consists of switch 1 and switch 2. Switch 1 controls the ASIC chip to read EEPROM data or write host computer data into the driver Driver (one of the two is selected). Switch 2 controls the host computer data to be written into the driver Driver or into the EEPROM (can be turned on at the same time).

[0075] d.SPI Interface Module

[0076] The SPI slave is responsible for receiving the SPI format command sent from the host computer and translating the command into a command format that can be recognized by the switch module.

[0077] e.I2C Interface Module

[0078] The I2C host is responsible for receiving the "(address + data) pair" written from the FIFO and then converting it into the standard I2C command format. Or reverse reading.

[0079] f. Driver module

[0080] The core processing module of the system is responsible for the drive control logic and parameter processing of the IGBT. The driver module receives parameters sent from the host computer or EEPROM, such as fault judgment time, fault start delay, IGBT turn-on or turn-off time, etc., and sets the IGBT drive conditions according to these parameters. Based on the received parameters, the driver module adjusts the switch state of the IGBT in real time to ensure that the power electronic system can accurately respond to load changes and control requirements.

[0081] In one embodiment, the initial state of the switch 1 is a communication connection when the ASIC chip is connected to read the data of the EEPROM chip.

[0082] In one embodiment, when the highest bit of the address field is 0 and the highest bit of the data field is 0, the switch 2 connects the communication connection when the drive parameter is written into the driver and when writing / reading the EEPROM chip;

[0083] When the highest bit of the address field is 0 and the highest bit of the data field is 1, switch 2 is connected to transmit the drive parameters to the driver of the ASIC digital driver chip;

[0084] When the highest bit of the address field is 1, the switch 2 is connected to the communication connection for reading the operating parameters of the ASIC digital driver chip.

[0085] In a specific embodiment, in combination Figure 1 , the working process of the IGBT digital drive system is as follows:

[0086] a. After the system reset is completed, switch 1 is set to the default down position. At this time, the ASIC chip can read all the parameters of the driver from the EEPROM in sequence. During this period, the user's operation of configuring the driver parameters through SPI is invalid;

[0087] b. After initialization, switch 1 is turned up, and switch 2 can now freely select the connection port:

[0088] If the user needs to configure the drive parameters, the SPI host writes the drive parameters of the corresponding address to the ASIC chip through the SPI interface (switch 2 is turned right), and chooses whether to write the parameters to the EEPROM for backup (switch 2 is turned down);

[0089] c. The host computer can read the driver parameter value of the current register of the ASIC chip in real time through the SPI interface.

[0090] Example 2

[0091] The present invention also provides a control method based on the IGBT digital drive system, the method comprising:

[0092] The SPI host built by FPGA adjusts the driving parameters of the ASIC digital driver chip and / or EEPROM chip through the SPI interface, or reads the operating parameters of the ASIC digital driver chip, and sends the corresponding control instructions to the ASIC digital driver chip;

[0093] The ASIC digital driver chip interprets and executes the control instructions through the SPI interface;

[0094] The EEPROM chip saves the driving parameters through the I2C interface, or reads out the saved driving parameters and returns them to the ASIC digital driving chip.

[0095] Preferably, the control instruction is a 24-bit code, wherein the lower 16 bits are a data field, the lower 15 bits of the data field are used to store the specific value of the drive parameter to be adjusted, the highest bit of the data field indicates whether the drive parameter to be adjusted is written into the control bit of the EEPROM chip, the upper 8 bits are an address field, the lower 7 bits of the address field indicate the SPI address corresponding to the drive parameter to be adjusted, and the highest bit of the address field indicates the read-write control bit.

[0096] Furthermore, when the highest bit of the data field is 0, it indicates that the driving parameters are transmitted to the driver of the ASIC digital driver chip and the EEPROM chip at the same time; when the highest bit of the data field is 1, it indicates that the driving parameters are transmitted only to the driver of the ASIC digital driver chip.

[0097] Furthermore, when the highest bit of the address field is 0, it indicates that the driving parameters are written into the corresponding target according to the highest bit of the data field, and when the highest bit of the address field is 1, it indicates that the operating parameters of the ASIC digital driving chip are read.

[0098] Preferably, the ASIC digital driver chip comprises: a first-in first-out module, a data mapping module, a switch module, an SPI interface module, an I2C interface module and a driver;

[0099] The first-in first-out module is used to perform rate matching, bit width matching and data screening on data transmitted by the SPI interface and the I2C interface;

[0100] The data mapping module is used to map the drive parameters and their addresses with the storage space of the EEPROM;

[0101] The switch module is composed of switch 1 and switch 2, wherein switch 1 is used to control the communication connection when the ASIC chip reads the EEPROM chip data or writes the drive parameters into the driver, and switch 2 is used to control the communication connection when the drive parameters are written into the driver and / or when writing / reading the EEPROM chip;

[0102] The SPI interface module is used to receive the control instruction sent by the SPI host and translate the control instruction into an instruction format recognized by the switch module;

[0103] The I2C interface module is used to receive the address data pair written in the first-in first-out module and convert it into a standard I2C instruction format, or read it in reverse;

[0104] The driver is used to adjust a driving signal for controlling the IGBT according to the received driving parameters.

[0105] Furthermore, the data mapping module is specifically used to: expand the single-byte address Addr of the address domain into two bytes: (2×Addr, 2×Addr+1), and map it to the first-in-first-out module, each address byte marks the storage position of the lower 8-bit data adjacent to it in the EEPROM chip, and transmit the upper 16 bits and lower 16 bits of the first-in-first-out module through the I2C bus respectively, and save them in the EEPROM chip space corresponding to each address byte.

[0106] Furthermore, the initial state of the switch 1 is a communication connection when the ASIC chip is connected to read the data of the EEPROM chip.

[0107] Further, when the highest bit of the address field is 0 and the highest bit of the data field is 0, the switch 2 is connected to the communication connection when the drive parameter is written into the driver and when writing / reading the EEPROM chip;

[0108] When the highest bit of the address field is 0 and the highest bit of the data field is 1, switch 2 is connected to transmit the drive parameters to the driver of the ASIC digital driver chip;

[0109] When the highest bit of the address field is 1, the switch 2 is connected to the communication connection for reading the operating parameters of the ASIC digital driver chip.

[0110] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0111] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0112] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0113] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0114] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. An IGBT digital drive system, characterized in that: The system includes: an SPI host built by FPGA, an ASIC digital driver chip and an EEPROM chip; The SPI host is used to adjust the driving parameters of the ASIC digital driver chip and / or the EEPROM chip through the SPI interface, or read the operating parameters of the ASIC digital driver chip, and send corresponding control instructions to the ASIC digital driver chip; The ASIC digital driver chip is used to interpret and execute the control instructions through the SPI interface; The EEPROM chip is used to save the driving parameters through the I2C interface, or read the saved driving parameters and return them to the ASIC digital driving chip.

2. The system according to claim 1, characterized in that The control instruction is a 24-bit code, wherein the lower 16 bits are a data field, the lower 15 bits of the data field are used to store the specific value of the drive parameter to be adjusted, the highest bit of the data field indicates whether the drive parameter to be adjusted is written into the control bit of the EEPROM chip, the upper 8 bits are an address field, the lower 7 bits of the address field indicate the SPI address corresponding to the drive parameter to be adjusted, and the highest bit of the address field indicates the read-write control bit.

3. The system according to claim 2, characterized in that When the highest bit of the data field is 0, it means that the driving parameters are transmitted to the driver of the ASIC digital driver chip and the EEPROM chip at the same time. When the highest bit of the data field is 1, it means that the driving parameters are only transmitted to the driver of the ASIC digital driver chip.

4. The system according to claim 3, characterized in that When the highest bit of the address field is 0, it indicates that the driving parameters are written into the corresponding target according to the highest bit of the data field. When the highest bit of the address field is 1, it indicates that the operating parameters of the ASIC digital driving chip are read.

5. The system according to claim 1, characterized in that The ASIC digital driver chip includes: a first-in first-out module, a data mapping module, a switch module, an SPI interface module, an I2C interface module and a driver; The first-in first-out module is used to perform rate matching, bit width matching and data screening on data transmitted by the SPI interface and the I2C interface; The data mapping module is used to map the drive parameters and their addresses with the storage space of the EEPROM; The switch module is composed of switch 1 and switch 2, wherein switch 1 is used to control the communication connection when the ASIC chip reads the EEPROM chip data or writes the drive parameters into the driver, and switch 2 is used to control the communication connection when the drive parameters are written into the driver and / or when writing / reading the EEPROM chip; The SPI interface module is used to receive the control instruction sent by the SPI host and translate the control instruction into an instruction format recognized by the switch module; The I2C interface module is used to receive the address data pair written in the first-in first-out module and convert it into a standard I2C instruction format, or read it in reverse; The driver is used to adjust a driving signal for controlling the IGBT according to the received driving parameters.

6. The system according to claim 5, characterized in that The data mapping module is specifically used to: expand the single-byte address Addr of the address domain into two bytes: (2×Addr, 2×Addr+1), and map it to the first-in first-out module, each address byte marks the storage position of the lower 8-bit data adjacent to it in the EEPROM chip, and transmit the upper 16 bits and lower 16 bits of the first-in first-out module through the I2C bus respectively, and save them in the EEPROM chip space corresponding to each address byte.

7. The system according to claim 5, characterized in that The initial state of the switch 1 is a communication connection when the ASIC chip is connected to read the data of the EEPROM chip.

8. The system according to claim 5, characterized in that When the highest bit of the address field is 0 and the highest bit of the data field is 0, switch 2 is connected to the communication connection when the drive parameters are written into the driver and when writing / reading the EEPROM chip; When the highest bit of the address field is 0 and the highest bit of the data field is 1, the switch 2 is connected to transmit the drive parameters to the driver of the ASIC digital drive chip; When the highest bit of the address field is 1, the switch 2 is connected to the communication connection for reading the operating parameters of the ASIC digital driver chip.

9. A control method for an IGBT digital drive system according to any one of claims 1 to 8, characterized in that: The method comprises: The SPI host built by FPGA adjusts the driving parameters of the ASIC digital driver chip and / or EEPROM chip through the SPI interface, or reads the operating parameters of the ASIC digital driver chip, and sends the corresponding control instructions to the ASIC digital driver chip; The ASIC digital driver chip interprets and executes the control instructions through the SPI interface; The EEPROM chip saves the driving parameters through the I2C interface, or reads out the saved driving parameters and returns them to the ASIC digital driving chip.

Images