Data selection circuit, method, device and equipment and storage medium

Abstract

The invention discloses a data selection circuit, method, device and equipment and a storage medium, and relates to the technical field of data processing, the data selection circuit comprises a plurality of data channels, the input ends of the data channels are respectively connected with different input data, and the output ends of the data channels are mutually connected to form a multi-input and one-output structure. When input data of a certain data channel is selected to be output, the first resistive device and the second resistive device are switched to be in a low-resistance state, and the input data can be output after passing through the first resistive device in the low-resistance state and the second resistive device in the low-resistance state; when input data of a certain data channel is not selected to be output, the first resistive device and the second resistive device are in a high-resistance state, and the input data cannot be normally output through the first resistive device in the high-resistance state and the second resistive device in the high-resistance state; the data selection function is realized by using the resistance state change of the resistance change device, and compared with a gate circuit, the data selection circuit has the advantages of fewer used devices, simple circuit structure and strong expandability.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to a data selection circuit, method, device, equipment and storage medium. Background Art

[0002] A data selector is a circuit that selects and transmits multiple data to a unique channel to achieve data selection. It is a switch with multiple inputs and a single output, and is also the basis for realizing other complex logic. The traditional CMOS (Complementary Metal Oxide Semiconductor) data selector circuit requires a NOT gate circuit, two AND gate circuits, and an OR gate circuit, and uses the logical calculation of the gate circuit to realize the data selection process. However, each gate circuit is composed of multiple transistors, resulting in a very high cost for the entire data selector and a large area. Especially when the amount of input data is large, the circuit of the entire data selector will become very complicated.

[0003] It can be seen that how to realize a simpler data selector circuit is a problem that those skilled in the art need to solve. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a data selection circuit, method, device, equipment and storage medium, which can solve the problem of high cost and large occupied area of ​​the data selection circuit.

[0005] In order to solve the above technical problems, an embodiment of the present invention provides a data selection circuit, including:

[0006] A plurality of data channels, the output ends of the data channels are connected to each other for outputting selected data; the input ends of the data channels are used for receiving different input data;

[0007] For any data channel, the data channel includes:

[0008] A first resistive switching device, wherein the first end is used to access input data, and the first resistive switching device is used to switch to a low impedance state when the input data accessed by the first resistive switching device is within a preset valid range, and to switch to a high impedance state when the input data accessed by the first resistive switching device is not within the preset valid range;

[0009] A second resistive switching device, wherein the first end is connected to the second end of the first resistive switching device, and the second end serves as the output end of the data channel. The second resistive switching device is used to switch to a low-impedance state when the input data connected to the corresponding first resistive switching device is selected for output, and to switch to a high-impedance state when the input data connected to the corresponding first resistive switching device is not selected for output.

[0010] In some embodiments, the first resistive switching device and the second resistive switching device are both resistive switching memories; and the data selection circuit further includes:

[0011] A bias voltage output circuit, the bias voltage output circuit comprising a plurality of output terminals corresponding one-to-one to each of the data channels;

[0012] For any output end of the bias voltage output circuit, the output end is respectively connected to the second end of the first resistive switching device in the corresponding data channel and the first end of the second resistive switching device in the corresponding data channel;

[0013] The bias voltage output circuit is used to output a bias voltage to each of the data channels according to the selected output condition of the input data, so as to control the second resistive switching device to switch the resistance state.

[0014] In some embodiments, the second resistive switching device is a non-volatile resistive switching memory, and the first resistive switching device is a volatile resistive switching memory.

[0015] In some embodiments, the second resistive switching device is a bipolar resistive switching memory; the initial state of the second resistive switching device is a high impedance state;

[0016] The data selection circuit also includes:

[0017] a processor, having an input end connected to the output end of the data selection circuit and an output end connected to the input end of the bias voltage output circuit, for receiving output data of the data selection circuit and outputting a data selection completion instruction to the bias voltage output circuit upon receiving the output data of the data selection circuit;

[0018] The bias voltage output circuit is specifically used for outputting a first preset bias voltage to a first end of a second resistive switching device in the target data channel when input data of the target data channel is selected for output, so as to control the second resistive switching device in the target data channel to switch from a high resistance state to a low resistance state; and when receiving the data selection completion instruction, outputting a second preset bias voltage to the first end of the second resistive switching device in the target data channel, so as to control the second resistive switching device in the target data channel to recover from a low resistance state to a high resistance state;

[0019] Wherein, the voltage directions of the first preset bias voltage and the second preset bias voltage are opposite.

[0020] In some embodiments, the second resistive switching device is a unipolar resistive switching memory; the initial state of the second resistive switching device is a high impedance state;

[0021] The bias voltage output circuit is specifically used to output a third preset bias voltage to the first end of the second resistive device in the target data channel when the input data of the target data channel is selected to be output, so as to control the second resistive device in the target data channel to switch from a high resistance state to a low resistance state; when a data selection completion instruction is received, the third preset bias voltage is output to the first end of the second resistive device in the target data channel again, so as to control the second resistive device in the target data channel to recover from a low resistance state to a high resistance state.

[0022] In some embodiments, the bias voltage output circuit is a controller, and several general input and output ports of the controller are connected to each of the data channels in a one-to-one correspondence;

[0023] The controller is used to configure the pin level state of each of the general input and output ports according to the selected output status of the input data, so as to control the second resistive switching device to switch the resistance state.

[0024] To solve the above technical problem, an embodiment of the present invention further provides a data selection method, which is applied to the data selection circuit as described above. The data selection method includes:

[0025] Determine the target data channel corresponding to the target data to be output;

[0026] Controlling the first resistive switching device and the second resistive switching device in the target data channel to switch to a low resistance state, so that the target data passes through the first resistive switching device in the low resistance state and the second resistive switching device in the low resistance state;

[0027] Receive target data output from the target data channel.

[0028] In order to solve the above technical problems, an embodiment of the present invention further provides a data selection device, which is applied to the data selection circuit as described above, and the data selection device includes:

[0029] A target determination unit, used to determine a target data channel corresponding to target data to be output;

[0030] A control conduction unit, used for controlling the first resistive switching device and the second resistive switching device in the target data channel to switch to a low resistance state, so that the target data passes through the first resistive switching device in the low resistance state and the second resistive switching device in the low resistance state;

[0031] The data receiving unit is used to receive the target data output from the target data channel.

[0032] To solve the above technical problems, an embodiment of the present invention further provides an electronic device, including:

[0033] Memory for storing computer programs;

[0034] A processor is used to execute the computer program to implement the steps of the data selection method as described above.

[0035] To solve the above technical problem, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the data selection method as described above are implemented.

[0036] It can be seen from the above technical solution that the data selection circuit includes multiple data channels, and the input ends of each data channel are respectively connected to different input data, and the output ends are connected to each other to form a multi-input and one-output structure. When the input data of a certain data channel is selected for output, the first resistive switching device and the second resistive switching device therein will switch to a low-resistance state, and the input data can be output after passing through the first resistive switching device in the low-resistance state and the second resistive switching device in the low-resistance state; when the input data of a certain data channel is not selected for output, the first resistive switching device and the second resistive switching device therein will be in a high-resistance state, and the input data cannot be normally output through the first resistive switching device in the high-resistance state and the second resistive switching device in the high-resistance state. The beneficial effect of the present invention is that the data selection function is realized by utilizing the resistance state change of the resistive switching device, and compared with the gate circuit, fewer devices are used, the circuit structure is simple, and the scalability is strong. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0038] Figure 1 A schematic diagram of the structure of a data selection circuit provided by an embodiment of the present invention;

[0039] Figure 2 A schematic diagram of the structure of a data selection circuit including two data channels provided by an embodiment of the present invention;

[0040] Figure 3 A schematic diagram of the structure of a data selection circuit including N data channels provided by an embodiment of the present invention;

[0041] Figure 4 A schematic diagram of electrical characteristics of a bipolar non-volatile resistive random access memory provided by an embodiment of the present invention;

[0042] Figure 5 A schematic diagram of electrical characteristics of a volatile resistive random access memory provided by an embodiment of the present invention;

[0043] Figure 6 A schematic diagram of electrical characteristics of a unipolar non-volatile resistive random access memory provided by an embodiment of the present invention;

[0044] Figure 7 A schematic diagram of a flow chart of a data selection method provided by an embodiment of the present invention;

[0045] Figure 8 A schematic diagram of the structure of a data selection device provided by an embodiment of the present invention;

[0046] Fig. 9 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0048] The terms "including" and "having" in the specification of the present invention and the above-mentioned drawings, as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but may include steps or units that are not listed.

[0049] In order to enable those skilled in the art to better understand the solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0050] Since the invention of integrated circuits, its process technology has been continuously improving in accordance with Moore's Law. Today, the minimum line width has reached several nanometers, entering the realm of quantum physics and mesoscopic physics, resulting in physical phenomena such as Fermi pinning, Coulomb blockade, quantum tunneling, impurity fluctuations and spin transport. These physical obstacles encountered by Moore's Law, which has continued for more than 50 years, have made silicon-based CMOS technology face huge challenges in physical principles and process technology by relying on simple size reduction to increase integration. On the other hand, with the increase in transistor density, the power consumption per unit area is also increasing, and the huge heat generated has seriously affected the high-frequency performance and reliability of integrated circuits. For example, from 1997 to 2010, the gate length of CMOS devices has been reduced by about 300 times, but the energy consumption density has increased by nearly 100,000 times, and the clock frequency has only increased by about 2,000 times. Power consumption has become another challenge for the development of the microelectronics industry.

[0051] In this context, it is necessary to seek new technological breakthroughs to maintain the continuous growth of electronic equipment performance. As a new type of non-volatile storage technology, resistive random access memory has gradually become a research hotspot due to its advantages such as higher storage density, lower energy consumption and faster read and write speeds. Resistive random access memory uses the resistance change of materials to store information, providing new possibilities for surpassing Moore's Law. The design of emerging circuit devices based on resistive random access memory is conducive to simplifying the current mainstream transistor-based CMOS circuits. Based on this, the present invention uses resistive random access memory to realize a data selection circuit.

[0052] Next, a data selection circuit provided by an embodiment of the present invention is described in detail. Figure 1 As shown, Figure 1 A schematic diagram of a data selection circuit provided by an embodiment of the present invention, the data selection circuit comprising:

[0053] A plurality of data channels, the output ends of the data channels are connected to each other for outputting selected data; the input ends of the data channels are used for receiving different input data;

[0054] For any data channel, the data channel includes:

[0055] A first resistive switching device, wherein the first end is used to access input data, and the first resistive switching device is used to switch to a low impedance state when the input data accessed by the first resistive switching device is within a preset valid range, and to switch to a high impedance state when the input data accessed by the first resistive switching device is not within the preset valid range;

[0056] A second resistive switching device, wherein the first end is connected to the second end of the first resistive switching device, and the second end serves as the output end of the data channel. The second resistive switching device is used to switch to a low-impedance state when the input data connected to the corresponding first resistive switching device is selected for output, and to switch to a high-impedance state when the input data connected to the corresponding first resistive switching device is not selected for output.

[0057] It can be understood that the data selection circuit includes multiple data channels, and the input ends of each data channel are independent of each other, and are used to access different input data respectively. The output ends of all data channels are connected together, thereby forming a multi-input single-output data selection circuit structure. When there is data input in the data channel, the data selection circuit will only select one input data for output. At this time, the state of the first resistive switching device and the second resistive switching device in each data channel will be switched according to the corresponding input data and whether it is selected for output. When a data channel receives valid data in a preset effective range, and the input data corresponding to the access of the data channel is selected for output, the first resistive switching device and the second resistive switching device will be switched to a low resistance state, and the resistance value of the first resistive switching device and the second resistive switching device in the low resistance state is very small. At this time, the selected output input data can be normally output through the first resistive switching device and the second resistive switching device in the low resistance state, and there will be no data loss. However, if the data received by a certain data channel is not valid data and / or the corresponding input data is not selected for output, the first resistive switching device and / or the second resistive switching device will be in a high-impedance state, and the resistance of the first resistive switching device and the second resistive switching device in the high-impedance state is very large, and the corresponding input data cannot be normally output through the data channel. Thus, the selective output of multiple input data is achieved by utilizing the resistance state change process of the resistive switching device.

[0058] It should be noted that the resistance change of the second resistive switching device depends on whether the data channel in which it is located is the target data channel corresponding to the target data selected for output. The default initial state of the second resistive switching device is a high resistance state. If a certain input data is selected as the target data output, the second resistive switching device in the corresponding data channel will receive a control signal and switch from a high resistance state to a low resistance state; the second resistive switching devices in other data channels will remain in a high resistance state. The resistance change of the first resistive switching device depends on the voltage of the input data connected to its first end. The default initial state of the first resistive switching device is a high resistance state. When the voltage of the input data is greater than the first preset threshold corresponding to the first resistive switching device, the first resistive switching device will switch from a high resistance state to a low resistance state; therefore, the first resistive switching device can only pass input data with a voltage greater than a preset value. When designing a data selection circuit, the type of the first resistive switching device will be adjusted according to the data type and voltage level used in the current application scenario. Therefore, when designing and applying a data selection circuit, it is necessary to cooperate with the first preset threshold of the first resistive device to achieve the selection of the target data. The preferred setting method is to select a first resistive device with a very small first preset threshold to achieve a data selection circuit with a wider range of applications. The first preset threshold is also the opening threshold of the first resistive device.

[0059] It is not difficult to understand that valid data refers to data that can support the change of the first resistive switching device to a low-resistance state when input to the first end of the first resistive switching device. Generally, the voltage of the data itself can reach the first preset threshold value for controlling the configuration switching of the first resistive switching device. The data is in the preset valid range, which means that the voltage of the data is greater than the first preset threshold value of the first resistive switching device. Taking digital signals as an example, digital signals include signals 0 and 1. Generally, there will be multiple data channels receiving signal 1. At this time, it is necessary to select a target data channel to output the corresponding connected signal 1. Therefore, the first resistive switching device needs to switch to a low-resistance state when receiving signal 1. At this time, if signal 1 is a 3.3V voltage signal, the first preset threshold value of the first resistive switching device can be less than 3.3V. Taking analog signals as an example, if an analog signal above 0.5V is required in a certain application scenario, then the data selection circuit needs to support the output of a minimum analog signal of 0.5V, then it is necessary to select a first resistive switching device with a first preset threshold value less than 0.5V.

[0060] It should be noted that this application does not make any special restrictions on the specific types and implementation methods of the first resistive switching device and the second resistive switching device in each data channel. They need to be set and adjusted according to the specific voltage levels of the data in the actual application scenario. This application does not make any special restrictions on the number of data channels.

[0061] As a specific embodiment, see Figure 2 As shown, Figure 2 A schematic diagram of a data selection circuit including two data channels provided by an embodiment of the present invention; taking a two-choice data selector as an example, its structure is as follows Figure 2 As shown, the bit line X is the input, including two inputs X1 and X2, Y is the selection signal, that is, the control signal set for the second resistive switching device, and the process of selecting which input data to output is realized by outputting different selection signals to each data channel, including Y1 corresponding to the first data channel and Y2 corresponding to the second data channel, and Z is the output line. The first resistive switching device includes resistive switching memory B1 and resistive switching memory B2, and the second resistive switching device includes resistive switching memory A1 and resistive switching memory A2.

[0062] As a specific embodiment, see Figure 3 As shown, Figure 3 A schematic diagram of a data selection circuit including N data channels provided by an embodiment of the present invention; based on a two-to-one data selector, four-to-one, eight-to-one, and more data selection functions can be realized by directly increasing the number of resistive switching devices linearly. The specific structure of the N-to-one data selector based on the resistive switching memory is as follows Figure 3As shown, there are n inputs X1, X2 to Xn and corresponding n selection signals Y1, Y2 to Yn, and Z is the output line. The first resistive switching device includes resistive switching memory B1, resistive switching memory B2 to resistive switching memory Bn, and the second resistive switching device includes resistive switching memory A1, resistive switching memory A2 to resistive switching memory An. A bias voltage is applied to the Ym corresponding to the line M to be selected, and then the corresponding second resistive switching device Am will become a low-resistance state under the action of the bias voltage. At the same time, due to the input of data, the divided voltage across the corresponding first resistive switching device Bm is greater than its opening threshold, and the first resistive switching device Bm becomes a low-resistance state. When Xm=1, no matter how many other line X inputs are, Z=1 can be obtained. If the input data is a digital signal, multiple channels can be opened at the same time, that is, when multiple input data outputs are selected, the multiple signals are OR-operated, that is, if any input data of the selected multiple channels is 1, the output result will be 1.

[0063] The data selection circuit provided by the present invention realizes the data selection function based on resistive switching devices such as resistive switching memory, realizes the method of multiple-select-one data selector with lower hardware complexity and lower power consumption, and has strong scalability. It has the advantages of using fewer devices, simple circuit structure, strong scalability, etc., and realizes the data selection function with lower hardware complexity.

[0064] In some embodiments, the first resistive switching device and the second resistive switching device are both resistive switching memories; and the data selection circuit further includes:

[0065] A bias voltage output circuit, the bias voltage output circuit comprising a plurality of output terminals corresponding one-to-one to each of the data channels;

[0066] For any output end of the bias voltage output circuit, the output end is respectively connected to the second end of the first resistive switching device in the corresponding data channel and the first end of the second resistive switching device in the corresponding data channel;

[0067] The bias voltage output circuit is used to output a bias voltage to each of the data channels according to the selected output condition of the input data, so as to control the second resistive switching device to switch the resistance state.

[0068] It is not difficult to understand that the first resistive switching device and the second resistive switching device can be implemented by using a resistive switching memory, and the resistance state change of the first resistive switching device and the second resistive switching device is realized by the change of the bias voltage at both ends of the device. Therefore, a bias voltage output voltage can be set to connect to the first end of the second resistive switching device, and the resistance state change of the second resistive switching device can be controlled by whether the bias voltage output circuit outputs the bias voltage, thereby realizing the process of selecting data output.

[0069] It should be noted that the specific electrical characteristics of the resistive memory A as the second resistive device are as follows: Figure 4 As shown, the initial state of the device is a high-resistance state. When the bias voltage across the device is higher than its turn-on threshold, the device changes to a low-resistance state. Curve 1 represents the relationship between the voltage across the device and the current flowing through the device when the resistive memory A is in a high-resistance state, and curve 2 represents the relationship between the voltage across the device and the current flowing through the device when the resistive memory A is in a low-resistance state. The electrical characteristics of the resistive memory B as the first resistive device are shown in FIG. Figure 5 As shown, the initial state of the device is a high-resistance insulating state. When the bias voltage across the device is higher than its turn-on threshold Vth2, the device will change to a low-resistance state, wherein curve 3 represents the relationship between the voltage across the device and the current flowing through the device when the resistive memory B is in a high-resistance state, and curve 4 represents the relationship between the voltage across the device and the current flowing through the device when the resistive memory B is in a low-resistance state.

[0070] It can be understood that when a certain input data needs to be selected for output, a bias voltage output circuit can be used to output a preset bias voltage to the second end of the first resistive switching device in the corresponding data channel and the first end of the second resistive switching device in the corresponding data channel. The output end is in a zero voltage state when there is no output. After the preset bias voltage is applied, the voltage across the second resistive switching device is greater than its opening threshold, and the second resistive switching device switches to a low resistance state. At the same time, when the input data is connected to the corresponding first resistive switching device, the voltage of the data itself will also cause the voltage across the first resistive switching device to be greater than its opening threshold, and the first resistive switching device switches to a low resistance state, thereby realizing the output of data. The specific type and implementation method of the bias voltage output voltage are not particularly limited in this application. The specific value of the preset bias voltage output can be selected and adjusted according to the opening threshold corresponding to the set second resistive switching device.

[0071] As a specific embodiment, Figure 2For example, the output end of the bias voltage output voltage outputs selection signals Y1 and Y2 respectively. When there is no selection, the selection signals Y1 and Y2 do not bias the corresponding data channels, and the resistive memory A1, the resistive memory A2, the resistive memory B1, and the resistive memory B2 are all in high-resistance state. At this time, even if there are input signals on the bit lines X1 and X2, the output cannot be detected due to the high-resistance resistive memory A1 and the resistive memory A2 connected in series on the line. That is to say, when X1=0, X2=0, Y1=0, and Y2=0, Z=0. When the X1 line is selected for data output, a bias voltage is applied at Y1, so that the resistive memory A1 becomes a low-resistance state, and because there is data input to X1, the voltage across the resistive memory B1 is greater than its opening threshold, and the resistive memory B1 becomes a low-resistance state, so the input signal at X1 can be output from Z. At this time, X1=1, and when X2=0 or X2=1, Z=1 can be obtained. Similarly, when the X2 line is selected, a bias voltage is applied to the Y2 point, so that the resistive memory A2 changes to a low-resistance state. At the same time, the voltage across the resistive memory B2 is greater than its opening threshold, and the resistive memory B2 changes to a low-resistance state. The output of the line Z corresponds to the input of X2. At this time, X2=1, when X1=0 or X1=1, Z=1 can be obtained.

[0072] Specifically, both the first resistive switching device and the second resistive switching device can be directly implemented using a resistive switching memory. In this case, the second resistive switching device can be controlled by setting a bias voltage output circuit, and the resistance state change of each second resistive switching device can be controlled by outputting a preset bias voltage or not, thereby realizing the data selection output process, which is simple, effective and easy to implement.

[0073] See also Figure 4 As shown, Figure 4 A schematic diagram of electrical characteristics of a bipolar non-volatile resistive random access memory provided by an embodiment of the present invention; see Figure 5 As shown, Figure 5 A schematic diagram of electrical characteristics of a volatile resistive memory provided in an embodiment of the present invention; in some embodiments, the second resistive device is a non-volatile resistive memory, and the first resistive device is a volatile resistive memory.

[0074] It can be understood that when the second resistive device switches to a low resistance state, if there is still a bias voltage at the first end of the second resistive device, this bias voltage may affect the accuracy of the final output data. Therefore, a non-volatile resistive memory can be used to implement the second resistive device. The resistance state change of the first resistive device is determined by the voltage of the input data itself. As long as the input data is always at the first end of the first resistive device, the first resistive device can always receive the input data. Therefore, the first resistive device can use a volatile resistive memory.

[0075] like Figure 2 and Figure 3 As shown, the resistive memory A has a non-volatile resistive switching characteristic, which means that the low resistance state switched to by the resistive memory A under the action of a preset bias voltage is non-volatile. At this time, it is necessary to apply a voltage to the resistive memory A again, and the resistive memory A will return to the high resistance state, otherwise the resistive memory A will remain in the low resistance state; while the resistive memory B has a volatile resistive switching characteristic, which means that the low resistance state switched to by the resistive memory B under the action of input data is volatile, and when the bias voltage is canceled or when the bias voltage at both ends is less than the device's holding voltage Vth1, the device will return to the initial high resistance insulating state. That is, the volatile resistive memory needs to be powered on all the time to maintain the low resistance state, while the non-volatile resistive memory only needs to add a bias voltage for a moment to achieve the retention of the low resistance state. Therefore, a non-volatile resistive memory is used to implement the second resistive device. The bias voltage output voltage only needs to output a preset bias voltage at the moment of selecting the data path to control the second resistive device to switch to a low-resistance state. There is no need to continuously output the preset bias voltage to the second resistive device, thereby avoiding the influence of the bias voltage on the output data.

[0076] Specifically, the first resistive variable device and the second resistive variable device are implemented by combining a volatile resistive variable memory and a non-volatile resistive variable memory, avoiding the method of continuously outputting a preset bias voltage to maintain the low resistance state of the second resistive variable device. While ensuring that the first resistive variable device and the second resistive variable device corresponding to the selected output data can be maintained in a low resistance state throughout the entire process of data output, the accuracy and reliability of the final output data are improved.

[0077] In some embodiments, the second resistive switching device is a bipolar resistive switching memory; the initial state of the second resistive switching device is a high impedance state;

[0078] The data selection circuit also includes:

[0079] a processor, having an input end connected to the output end of the data selection circuit and an output end connected to the input end of the bias voltage output circuit, for receiving output data of the data selection circuit and outputting a data selection completion instruction to the bias voltage output circuit upon receiving the output data of the data selection circuit;

[0080] The bias voltage output circuit is specifically used for outputting a first preset bias voltage to a first end of a second resistive switching device in the target data channel when input data of the target data channel is selected for output, so as to control the second resistive switching device in the target data channel to switch from a high resistance state to a low resistance state; and when receiving the data selection completion instruction, outputting a second preset bias voltage to the first end of the second resistive switching device in the target data channel, so as to control the second resistive switching device in the target data channel to recover from a low resistance state to a high resistance state;

[0081] Wherein, the voltage directions of the first preset bias voltage and the second preset bias voltage are opposite.

[0082] It is not difficult to understand that non-volatile resistive memory includes two types: bipolar resistive memory and unipolar resistive memory. When the second resistive device is implemented using a bipolar resistive memory, the device will only return to a high-resistance state when a reverse bias voltage is applied to the device again. Therefore, the bias voltage output circuit will control the second resistive device to switch from a high-resistance state to a low-resistance state by outputting a first preset bias voltage when data output needs to be selected; when the selected data output ends, it is necessary to switch the second resistive device in this low-resistance state to a high-resistance state again, that is, to turn off the previously selected data channel. At this time, it is necessary to apply a reverse voltage to the first end of the second resistive device in the data channel to be turned off, so as to reset the resistive memory A in the data channel to its initial high-resistance state, thereby turning off the data channel in which it is located. The resistive memory B will spontaneously return to the initial high-resistance state after the input voltage is removed, that is, the data is input, to prepare for the next data selection. The present application does not make any special restrictions on the specific values ​​of the first preset bias voltage and the second preset bias voltage. The absolute values ​​of the first preset bias voltage and the second preset bias voltage do not necessarily have to be equal, as long as they can both trigger the resistance state switching of the second resistive device.

[0083] Furthermore, in order to facilitate the bias voltage output circuit to determine whether the selected data has been output, a processor can be further set in the data selection circuit to detect the data output in real time. The processor can directly reuse the device that receives the output data, or the device that receives the output data and the device that outputs the data selection completion instruction can be set separately, and a communication connection can be established in advance between the two. When the processor receives the output data, it means that the data output is completed. At this time, the bias voltage output voltage can be instructed to control the second resistive variable device to return to a high impedance state. The specific type and implementation method of the processor and the data selection completion instruction are not particularly limited in this application.

[0084] Considering that the data transmission speed itself is relatively fast, a timer or a delay device can also be directly set in the bias voltage output circuit, and after outputting the first preset bias voltage to the first end of the second resistive switching device in the target data channel, the second preset bias voltage is directly output to the first end of the second resistive switching device in the target data channel after a delay of a preset time length. The specific value of the preset time length can be set according to the line length and the data transmission speed.

[0085] Specifically, when the second resistive device is implemented using a bipolar resistive memory, the bias voltage output circuit needs to output a second preset bias voltage opposite to the first preset bias voltage at the end of data output to control the second resistive device to restore to a high-impedance state so that the next data selection and output process can proceed.

[0086] See also Figure 6 As shown, Figure 6 A schematic diagram of electrical characteristics of a unipolar non-volatile resistive memory provided by an embodiment of the present invention; in some embodiments, the second resistive device is a unipolar resistive memory; the initial state of the second resistive device is a high impedance state;

[0087] The bias voltage output circuit is specifically used to output a third preset bias voltage to the first end of the second resistive device in the target data channel when the input data of the target data channel is selected to be output, so as to control the second resistive device in the target data channel to switch from a high resistance state to a low resistance state; when a data selection completion instruction is received, the third preset bias voltage is output to the first end of the second resistive device in the target data channel again, so as to control the second resistive device in the target data channel to recover from a low resistance state to a high resistance state.

[0088] It is understandable that the resistive memory A can also be implemented by a unipolar non-volatile resistive memory, and the data selection function can also be realized. The specific electrical characteristics of the unipolar non-volatile resistive memory are as follows: Figure 6As shown, curve 5 represents the relationship between the voltage across the device and the current flowing through the device when the resistive memory A is in a high-resistance state, and curve 6 represents the relationship between the voltage across the device and the current flowing through the device when the resistive memory A is in a low-resistance state. At this time, there is a certain difference in the operation of controlling the second resistive device to restore the high-resistance state. When the bias voltage received by the unipolar resistive memory is greater than its opening threshold Vset, it changes from the initial high-resistance state to the low-resistance state, so that the circuit is turned on, which plays a role in data selection. When it is subjected to a bias voltage higher than the opening threshold Vreset again, the unipolar resistive memory will return from the low-resistance state to the initial high-resistance insulating state. At this time, the line where it is located is closed and data cannot be selected. Therefore, after the bias voltage output circuit outputs the third preset bias voltage to control the second resistive device to switch from the high-resistance state to the low-resistance state, if the data output is completed, the same third preset bias voltage can be output again to control the second resistive device to restore the high-resistance state. The specific value of the third preset bias voltage is not specifically limited in this application. The bias voltage output when restoring the high impedance state may not be consistent with the third preset bias voltage, and only needs to be greater than the opening threshold of the second resistive variable device. For the convenience of implementation, the same bias voltage is used in the two application processes in this embodiment. The specific method for determining the end of data output by the bias voltage output circuit is not specifically limited in this application, and the implementation method in the previous embodiment can be referred to.

[0089] Specifically, when the second resistive device is implemented using a unipolar resistive memory, the bias voltage output circuit needs to output the third preset bias voltage again at the end of data output to control the second resistive device to restore to a high-impedance state so that the next data selection output process can proceed; this method is simpler and easier to implement, which is conducive to further reducing the cost and volume of the entire data selection circuit.

[0090] In some embodiments, the bias voltage output circuit is a controller, and several general input and output ports of the controller are connected to each of the data channels in a one-to-one correspondence;

[0091] The controller is used to configure the pin level state of each of the general input and output ports according to the selected output status of the input data, so as to control the second resistive switching device to switch the resistance state.

[0092] It is not difficult to understand that the bias voltage output circuit can be directly implemented by a controller, using the form of address selection code to implement the selection signal in the data selection circuit, and realizing the selection of data output and the application of the corresponding bias voltage through a high-level signal. Therefore, the controller only needs to set a number of output ports connected to each data channel in a one-to-one correspondence. When a general input and output port is at a high level, the input data of the corresponding data channel is selected and output. At this time, the high level is directly applied as a bias voltage to the first end of the second resistive variable device to control the second resistive variable device to switch to a low-resistance state. The specific type and implementation method of the controller are not particularly limited in this application, and the processor can be directly multiplexed to achieve it.

[0093] It should be noted that the bias voltage output circuit can also be provided with bias voltage output subcircuits corresponding to each data channel one by one, each bias voltage output subcircuit includes a switch device having one end connected to a preset power supply, and the other end of the switch device is connected to the first end of the second resistive switching device in the corresponding data channel. When a data channel is selected as a target data channel, the corresponding switch device is turned on, and the preset power supply is applied to the first end of the second resistive switching device, thereby controlling the state switching of the second resistive switching device. In this way, the voltage value of the preset power supply is more flexible and has a wider range of applications.

[0094] Specifically, a controller can be directly used to implement a bias voltage output circuit, and the controller's own power supply can be used to generate a high-level signal to control the state switching of the second resistive device. This is simple, effective, and easy to implement. In particular, it can be multiplexed with a processor that receives output data, further reducing the cost and volume of the entire data selection circuit.

[0095] See also Figure 7 As shown, Figure 7 A flow chart of a data selection method provided by an embodiment of the present invention; To solve the above technical problem, an embodiment of the present invention further provides a data selection method, which is applied to the data selection circuit as described above, and the data selection method includes:

[0096] S11: Determine the target data channel corresponding to the target data to be output;

[0097] S12: Control the first resistive switching device and the second resistive switching device in the target data channel to switch to a low resistance state, so that the target data passes through the first resistive switching device in the low resistance state and the second resistive switching device in the low resistance state;

[0098] S13: Receive target data output from the target data channel.

[0099] It can be understood that when data output and data selection are required, the data to be selected can be controlled to be input into each data channel first, thereby controlling the state switching of the first resistive device corresponding to the valid data. Then, after determining the target data and target data channel to be output, the second resistive device in the target data channel is controlled to switch to a low-resistance state by applying a bias voltage or the like. At this time, the selected valid data can be output through the first resistive device in the low-resistance state and the second resistive device in the low-resistance state, thereby receiving the required target data.

[0100] For the description of the features in the data selection method provided in the embodiment of the present invention, reference can be made to the relevant description of the embodiment of the data selection circuit, which will not be described in detail here.

[0101] See also Figure 8 As shown, Figure 8 A schematic diagram of the structure of a data selection device provided by an embodiment of the present invention; To solve the above technical problem, an embodiment of the present invention further provides a data selection device, which is applied to the data selection circuit as described above, and the data selection device includes:

[0102] A target determination unit 11 is used to determine a target data channel corresponding to target data to be output;

[0103] A control conduction unit 12, used for controlling the first resistive switching device and the second resistive switching device in the target data channel to switch to a low resistance state, so that the target data passes through the first resistive switching device in the low resistance state and the second resistive switching device in the low resistance state;

[0104] The data receiving unit 13 is used to receive the target data output from the target data channel.

[0105] For the description of the features of the data selection device provided in the embodiments of the present invention, reference can be made to the relevant description of the embodiments of the data selection circuit and the data selection method, which will not be described in detail here.

[0106] See also Fig. 9 As shown, Fig. 9 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. To solve the above technical problems, an embodiment of the present invention further provides an electronic device, including:

[0107] A memory 60, for storing computer programs;

[0108] The processor 61 is used to execute the computer program to implement the steps of the data selection method as described above.

[0109] The electronic device provided in this embodiment may include but is not limited to a smart phone, a tablet computer, a laptop computer or a desktop computer.

[0110] Among them, the processor 61 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 61 can be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). The processor 61 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 61 may be integrated with a graphics processing unit (GPU), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 61 may also include an artificial intelligence (AI) processor, which is used to process computing operations related to machine learning.

[0111] The memory 60 may include one or more computer-readable storage media, which may be non-transitory. The memory 60 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory 60 is at least used to store the following computer program 601, wherein the computer program, after being loaded and executed by the processor 61, can implement the relevant steps of the data selection method disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory 60 may also include an operating system 602 and data 603, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 602 may include Windows, Unix, Linux, etc. Data 603 may include, but is not limited to, data in the data selection method, etc.

[0112] In some embodiments, the electronic device may further include a display screen 62 , an input / output interface 63 , a communication interface 64 , a power supply 65 , and a communication bus 66 .

[0113] Those skilled in the art will understand that Fig. 9 The structure shown in the figure does not constitute a limitation on the electronic device, and may include more or fewer components than shown in the figure.

[0114] For descriptions of features in the electronic device provided by the embodiments of the present invention, reference may be made to the relevant descriptions of the embodiments of the data selection circuit and the data selection method, which will not be described in detail here.

[0115] It is understandable that if the data selection method in the above embodiment is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the current technology, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium to execute all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, magnetic disk or optical disk, etc. Various media that can store program codes.

[0116] Based on this, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned data selection method are implemented.

[0117] For the description of the features in the computer-readable storage medium provided in the embodiments of the present invention, reference can be made to the relevant description of the embodiments of the data selection circuit and the data selection method, which will not be described in detail here.

[0118] An embodiment of the present invention further provides a computer program product, including a computer program / instruction, which implements the steps of the data selection method described in the above embodiment when executed by a processor.

[0119] For descriptions of features in the computer program product provided by the embodiments of the present invention, reference may be made to the relevant descriptions of the embodiments of the data selection circuit and the data selection method, which will not be described in detail here.

[0120] The above is a detailed introduction to a data selection circuit, method, device, equipment and storage medium provided by an embodiment of the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0121] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0122] The above is a detailed introduction to a data selection circuit, method, device, equipment and storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A data selection circuit, characterized in that: include: A plurality of data channels, the output ends of which are connected to each other for outputting selected data; The input end of each of the data channels is used to access different input data; For any data channel, the data channel includes: A first resistive switching device, wherein the first end is used to access input data, and the first resistive switching device is used to switch to a low impedance state when the input data accessed by the first resistive switching device is within a preset valid range, and to switch to a high impedance state when the input data accessed by the first resistive switching device is not within the preset valid range; A second resistive switching device, wherein the first end is connected to the second end of the first resistive switching device, and the second end serves as the output end of the data channel. The second resistive switching device is used to switch to a low-impedance state when the input data connected to the corresponding first resistive switching device is selected for output, and to switch to a high-impedance state when the input data connected to the corresponding first resistive switching device is not selected for output.

2. The data selection circuit according to claim 1, characterized in that: The first resistive switching device and the second resistive switching device are both resistive switching memories; The data selection circuit also includes: A bias voltage output circuit, the bias voltage output circuit comprising a plurality of output terminals corresponding one-to-one to each of the data channels; For any output end of the bias voltage output circuit, the output end is respectively connected to the second end of the first resistive switching device in the corresponding data channel and the first end of the second resistive switching device in the corresponding data channel; The bias voltage output circuit is used to output a bias voltage to each of the data channels according to the selected output condition of the input data, so as to control the second resistive switching device to switch the resistance state.

3. The data selection circuit according to claim 2, characterized in that: The second resistive switching device is a non-volatile resistive switching memory, and the first resistive switching device is a volatile resistive switching memory.

4. The data selection circuit according to claim 2, characterized in that: The second resistive switching device is a bipolar resistive switching memory; the initial state of the second resistive switching device is a high impedance state; The data selection circuit also includes: a processor, having an input end connected to the output end of the data selection circuit and an output end connected to the input end of the bias voltage output circuit, for receiving output data of the data selection circuit and outputting a data selection completion instruction to the bias voltage output circuit upon receiving the output data of the data selection circuit; The bias voltage output circuit is specifically used for outputting a first preset bias voltage to a first end of a second resistive switching device in the target data channel when input data of the target data channel is selected for output, so as to control the second resistive switching device in the target data channel to switch from a high resistance state to a low resistance state; and when receiving the data selection completion instruction, outputting a second preset bias voltage to the first end of the second resistive switching device in the target data channel, so as to control the second resistive switching device in the target data channel to recover from a low resistance state to a high resistance state; Wherein, the voltage directions of the first preset bias voltage and the second preset bias voltage are opposite.

5. The data selection circuit according to claim 2, characterized in that: The second resistive switching device is a unipolar resistive switching memory; the initial state of the second resistive switching device is a high-resistance state; The bias voltage output circuit is specifically used to output a third preset bias voltage to the first end of the second resistive switching device in the target data channel when the input data of the target data channel is selected to be output, so as to control the second resistive switching device in the target data channel to switch from a high resistance state to a low resistance state; When the data selection completion instruction is received, the third preset bias voltage is output again to the first end of the second resistive device in the target data channel to control the second resistive device in the target data channel to recover from a low resistance state to a high resistance state.

6. The data selection circuit according to any one of claims 2 to 5, characterized in that: The bias voltage output circuit is a controller, and several general input and output ports of the controller are connected to each of the data channels in a one-to-one correspondence; The controller is used to configure the pin level state of each of the general input and output ports according to the selected output status of the input data, so as to control the second resistive switching device to switch the resistance state.

7. A data selection method, characterized in that: Applied to the data selection circuit according to any one of claims 1 to 6, the data selection method comprises: Determine the target data channel corresponding to the target data to be output; Controlling the first resistive switching device and the second resistive switching device in the target data channel to switch to a low resistance state, so that the target data passes through the first resistive switching device in the low resistance state and the second resistive switching device in the low resistance state; Receive target data output from the target data channel.

8. A data selection device, characterized in that: Applicable to the data selection circuit according to any one of claims 1 to 6, the data selection device comprising: A target determination unit, used to determine a target data channel corresponding to target data to be output; A control conduction unit, used for controlling the first resistive switching device and the second resistive switching device in the target data channel to switch to a low resistance state, so that the target data passes through the first resistive switching device in the low resistance state and the second resistive switching device in the low resistance state; The data receiving unit is used to receive the target data output from the target data channel.

9. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the steps of the data selection method according to claim 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the data selection method according to claim 7 are implemented.

Images