System and method for carrying out prototype verification on circuit to be tested

Abstract

The invention provides a system and a method for performing prototype verification on a circuit to be tested. The system comprises a packet generator, a scrambling circuit, the circuit to be tested and a detection circuit, wherein the scrambling circuit, the circuit to be tested and the detection circuit are implemented on a field programmable gate array. The packet generator outputs a plurality of standard packets, wherein the length of each standard packet is within a standard range. The scrambling circuit generates a plurality of scrambling packets to the circuit to be tested according to the plurality of standard packets, so that the circuit to be tested generates a plurality of output packets according to the plurality of scrambling packets, and the length of any scrambling packet is out of the standard range. The detection circuit verifies the operation of the circuit to be tested according to the plurality of disturbance packets and the plurality of output packets.

Description

Technical Field

[0001] The present invention relates to a network communication chip, and more particularly to a system and method for performing field programmable gate array (FPGA) prototype verification on a circuit to be tested (such as a prototype circuit of a switch chip). Background Art

[0002] In the network communication system, the switch plays a core role in data forwarding. Therefore, ensuring the reliability of the switch chip is an important prerequisite for the normal operation of the overall network system. For the switch chip, the packets at the sending end are generated internally, which is relatively controllable and has a lower probability of error; while the packets at the receiving end come from various types of external devices and cannot be controlled by internal software / hardware, so it is more likely to have unexpected errors.

[0003] The conventional field editable logic gate array prototype verification method is to use the IXIA network tester to generate packets whose length and packet gap are both within the corresponding standard range, and send them to the receiving port of the prototype circuit of the switch chip (referred to as the switch prototype circuit) to detect the processing ability of the switch prototype circuit for packets. However, in real application situations, the switch chip may receive packets with various length errors or packet gap errors. Therefore, due to the limitations of the IXIA network tester used in the conventional verification method, it is currently impossible to confirm whether the switch chip can properly process packets when the packet format is incorrect.

[0004] Therefore, a novel method and corresponding system architecture are needed to simulate various erroneous packets (such as packets with incorrect length or incorrect packet interval) that a switch chip may receive in a field-editable logic gate array as much as possible without side effects or with less side effects, thereby improving the operating stability of the switch chip. Summary of the invention

[0005] The object of the present invention is to provide a system and method for performing field programmable gate array (FPGA) prototype verification on a circuit under test (e.g., a prototype circuit of a switch chip) to ensure that the circuit under test can operate properly when receiving various combinations of packets (e.g., packets with various lengths or various packet gaps).

[0006] At least one embodiment of the present invention provides a system for performing field-editable logic gate array prototype verification on a circuit to be tested. The system includes a packet generator, a scramble circuit, the circuit to be tested, and a detection circuit, wherein the scramble circuit is coupled to the packet generator and the circuit to be tested, and the detection circuit is coupled to the scramble circuit and the circuit to be tested. The packet generator is used to output one or more standard packets, wherein the length of each of the one or more standard packets falls within a standard range. The scramble circuit is used to receive the one or more standard packets, and generate one or more scramble packets based on the one or more standard packets for output to the circuit to be tested, so that the circuit to be tested generates one or more output packets based on the one or more scramble packets, wherein the length of any one of the one or more scramble packets falls outside the standard range. The detection circuit is used to receive the one or more scramble packets and the one or more output packets, and verify the operation of the circuit to be tested based on the one or more scramble packets and the one or more output packets. Specifically, the disturbance circuit, the circuit to be tested and the detection circuit are implemented on a field programmable logic gate array.

[0007] At least one embodiment of the present invention provides a method for prototyping a field-editable logic gate array of a circuit to be tested. The method comprises: using a packet generator to output one or more standard packets, wherein the length of each of the one or more standard packets falls within a standard range; using a scramble circuit to receive the one or more standard packets, and generating one or more scramble packets based on the one or more standard packets, wherein the length of any of the one or more scramble packets falls outside the standard range; using the circuit to be tested to receive the one or more scramble packets, and generating one or more output packets based on the one or more scramble packets; and using a detection circuit to receive the one or more scramble packets and the one or more output packets, and verifying the operation of the circuit to be tested based on the one or more scramble packets and the one or more output packets. In addition, the scramble circuit, the circuit to be tested, and the detection circuit are implemented on a field-editable logic gate array.

[0008] The system and method provided by the embodiment of the present invention can generate scrambled packets with various lengths and various packet intervals by configuring the scramble circuit on the field programmable logic gate array, so that the processing status of the switch chip when receiving various types of packets can be fully verified. In addition, the embodiment of the present invention does not significantly increase the additional cost. Therefore, the present invention can ensure the stability of the operation of the switch chip without side effects or with less side effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1The diagram is a schematic diagram of a system for performing field-programmable logic gate array prototype verification on a circuit under test according to an embodiment of the present invention.

[0010] Figure 2 According to an embodiment of the present invention, a method for Figure 1 The schematic diagram of the workflow of the method for field-editable logic gate array prototype verification of the circuit under test is shown.

[0011] Figure 3 According to an embodiment of the present invention Figure 2 An example of the workflow is shown.

[0012] Figure 4A FIG. 4 is a schematic diagram of a portion of a workflow for performing length scrambling on a packet according to an embodiment of the present invention.

[0013] Figure 4B FIG. 4 is a schematic diagram of another part of a workflow for performing length scrambling on a packet according to an embodiment of the present invention.

[0014] Figure 4C FIG. 4 is a schematic diagram of another part of a workflow for performing length scrambling on a packet according to an embodiment of the present invention.

[0015] Figure 5 FIG. 4 is a schematic diagram of a packet format of a standard packet according to an embodiment of the present invention.

[0016] Figure 6 FIG. 4 is a schematic diagram of a workflow for performing content scrambling on a destination address field and a source address field of a standard packet according to an embodiment of the present invention.

[0017] Figure 7 FIG. 4 is a schematic diagram of a control scheme when a scrambling circuit operates in a certain mode according to an embodiment of the present invention. DETAILED DESCRIPTION

[0018] Figure 1 The present invention is a schematic diagram of a system 10 for performing field programmable gate array (FPGA) prototype verification on a circuit under test 130 according to an embodiment of the present invention, wherein the system 10 may include the circuit under test 130, and specifically, the circuit under test 130 may represent a prototype circuit of a switch chip. In this embodiment, the system 10 may further include a packet generator 20 (such as an IXIA network test instrument), a scrambler circuit 100, a control register 110, a random number generator 120, and a detection circuit 140, wherein the scrambler circuit 100, the control register 110, the random number generator 120, and the detection circuit 140 may be implemented on a field programmable gate array 50. Figure 1 As shown, the scrambling circuit 100 is coupled to the packet generator 20, the control register 110, the random number generator 120 and the circuit under test 130, and the detection circuit 140 is coupled to the scrambling circuit 100 and the circuit under test 130. In detail, the packet generator 20 can be used to output one or more standard packets such as the standard packet {P orig}, where the standard packet {P orig Each standard packet P in orig The length of the packet generator is within a standard range. orig Each standard packet P orig The length of the packet and the inter-packet gap (IPG), such as the gap between any two packets, conform to a specific network communication specification. The scrambling circuit 100 can be used to receive a standard packet {P orig}, and according to the standard package {P orig} Generate one or more scramble packets such as scramble packet {P in} to the circuit under test 130, so that the circuit under test 130 can detect the disturbance packet {P in} Generate one or more output packets such as n output packets {P out1}、{P out2}, ... and {P outn}, where n is a positive integer, and the scrambled packet {P in Any disturbing packet P in The length falls outside this standard range.

[0019] Figure 2 According to an embodiment of the present invention, a method for Figure 1 The schematic diagram of the working process of the method for field-editable logic gate array prototype verification of the circuit under test 130 is shown. It should be noted that Figure 2 The workflow shown is for illustrative purposes only and is not intended to limit the present invention. For example, one or more steps may be Figure 2 The steps may be added, deleted, or modified from the workflow shown. In addition, the steps do not necessarily need to be followed exactly as shown if the overall result is not changed. Figure 2 Execute in the order shown.

[0020] In step S210, the system 10 may utilize the packet generator 20 to output one or more standard packets (eg, standard packet {P orig}), wherein the length of each of the one or more standard packets falls within a standard range.

[0021] In step S220, the system 10 may utilize the scrambling circuit 100 to receive the one or more standard packets, and generate one or more scrambled packets (eg, scrambled packets {P in}), wherein the length of any one of the one or more scrambled packets falls outside the standard range.

[0022] In step S230, the system 10 may utilize the circuit under test 130 to receive the one or more scrambling packets, and generate one or more output packets (eg, output packet {P out1}、{P out2}, ... and {P outn}).

[0023] In step S240 , the system 10 may utilize the detection circuit 140 to receive the one or more scrambling packets and the one or more output packets, and verify the operation of the circuit under test according to the one or more scrambling packets and the one or more output packets.

[0024] Scramble Packet {P in} may include one or more of at least one fragmented packet, at least one short packet, at least one long packet, and at least one normal packet. orig At least one standard packet P in orig The fragment packets are decomposed into a plurality of fragment packets, wherein the length of each of the plurality of fragment packets is less than a minimum length within the standard range, and each of the fragment packets can be used as a scrambled packet P in For example, when the minimum packet length and the maximum packet length defined by the specific network communication specification are 64 bits (Byte) and 1518 bits respectively, the length of each of the plurality of fragmented packets is less than 64 bits. orig At least one standard packet P in orig The length of the packet is reduced by one bit to generate at least one short packet, wherein the at least one short packet can be used as a scrambled packet P in For example, the scrambling circuit 100 may send a standard packet P of length orig_len bits to the orig Any bit in the packet is discarded to generate a short packet with a length of (orig_len-1) bits. orig} in multiple standard packets P orig The at least one long packet is concatenated into at least one long packet, and the length of the at least one long packet may be greater than a maximum length within the standard range, wherein the at least one long packet may be used as a scrambling packet P inFor example, when the minimum packet length and the maximum packet length defined by the specific network communication specification are 64 bits and 1518 bits respectively, the scrambling circuit 100 may be configured to receive more than a certain number of standard packets P orig The scrambling circuit 100 can connect the standard packet {P orig Any standard packet P in orig Without any disturbance processing, it is directly output as a normal packet, wherein the normal packet can be used as the disturbance packet P in For example, the scrambling circuit 100 may send a standard packet P of length orig_len bits to the orig Directly output as a normal packet with a length of orig_len bits.

[0025] As described above, the scrambling circuit 100 can generate different types of scrambling packets P, such as fragmented packets, short packets, long packets, and normal packets. in In this embodiment, the scrambling circuit 100 can receive a mode control signal PATTERN from the control register 110 to determine the scrambling mode executed by the scrambling circuit 100 according to the mode control signal PATTERN, wherein different scrambling modes can correspond to the above-mentioned different types of scrambling packets P in For example, the mode control signal PATTERN may be a four-bit binary value (for example, represented by 4'bxxxx). When PATTERN=4'b0000, the scrambling circuit 100 may avoid scrambling the packet length to keep the packet length unchanged (for example, scrambling the packet P in The length is equal to the standard packet P origlength). When PATTERN=4'b0001, the scramble circuit 100 may generate a large number of fragmented packets and a small number of normal packets (for example, the number of fragmented packets is greater than the number of normal packets). When PATTERN=4'b0010, the scramble circuit 100 may generate a fragmented packet followed by a normal packet. When PATTERN=4'b0011, the scramble circuit 100 may generate two fragmented packets followed by two normal packets. When PATTERN=4'b0100, the scramble circuit 100 may generate a large number of short packets and a small number of normal packets (for example, the number of short packets is greater than the number of normal packets). When PATTERN=4'b0101, the scramble circuit 100 may alternately generate short packets and normal packets (for example, a normal packet is followed by each short packet). When PATTERN=4'b0110, the scramble circuit 100 may generate a large number of long packets and a small number of normal packets (for example, the number of long packets is greater than the number of normal packets). When PATTERN=4'b0111, the scramble circuit 100 may alternately generate long packets and normal packets (for example, a normal packet is followed by each long packet). When PATTERN=4'b1000, the scramble circuit 100 may alternately generate long packets and short packets (for example, a short packet is followed by each long packet). When PATTERN=4'b1001, the scramble circuit 100 may periodically generate the following packet combination: a long packet followed by a fragmented packet or a normal packet, wherein the random number generator 120 may generate a random number to control whether a fragmented packet or a normal packet is followed by any long packet.

[0026] It should be noted that the above-mentioned details of controlling the operating mode of the scrambling circuit 100 with the mode control signal PATTERN are for illustrative purposes only and are not intended to limit the present invention. For example, the mode control signal PATTERN may be a binary value greater than four bits or a binary value less than four bits. For another example, the arrangement and combination of scrambling packets corresponding to each value may be changed. In addition, the length of the fragmented packet and / or the long packet may be controlled by a random value. For example, the scrambling circuit 100 may convert the standard packet P into a random number based on a plurality of random numbers within a predetermined range (for example, a plurality of random numbers within the interval [0,63] generated by the random number generator 120 when the minimum packet length and the maximum packet length defined by the specific network communication specification are 64 bits and 1518 bits respectively). origThe scrambling circuit 100 may be configured to be a plurality of fragment packets, so that the lengths of the plurality of fragment packets are respectively the plurality of random numbers (for example, the lengths of the plurality of fragment packets are randomly distributed). For another example, the scrambling circuit 100 may be configured to be a plurality of standard packets P according to at least one random number within a predetermined range (for example, when the minimum packet length and the maximum packet length defined by the specific network communication specification are 64 bits and 1518 bits respectively, at least one random number within the interval [1519, max_long_len] is generated by the random number generator 120, wherein max_long_len may represent a positive integer greater than 1519 and may be written in at least one register in the random number generator 120). orig The length of the fragmented packets and / or the long packets may be controlled by a fixed value. For example, the scrambling circuit 100 may convert the standard packet P into the at least one long packet according to a fixed number of fragmented packets in the interval [0,63]. orig The scrambler circuit 100 is further configured to decompose the standard packets P into a plurality of fragment packets, so that the length of each of the plurality of fragment packets is equal to the fixed number of fragment packets, wherein the fixed number can be written in at least one register in the scrambler circuit 100, but the present invention is not limited thereto. For another example, the scrambler circuit 100 can, according to a fixed number of long packets in the interval [1519, max_long_len], divide the corresponding number of standard packets P into a plurality of fragment packets. orig The at least one long packet is concatenated to make the length of the at least one long packet equal to the long packet fixed number, wherein the long packet fixed number can be written in at least one register in the scrambling circuit 100 .

[0027] In some embodiments, the scrambling circuit 100 may divide the standard packet P into two packets according to at least one packet interval random number within a predetermined range of a packet interval. orig The random number generator 120 may generate the at least one packet interval random number within the interval [ipg_min, ipg_max] to allow the scrambling circuit 100 to convert the standard packet P into the plurality of fragmented packets, so that the interval between any two adjacent fragmented packets in the plurality of fragmented packets is equal to the at least one packet interval random number. orig The scrambling circuit 100 can be configured to decompose the standard packet P into the plurality of fragment packets so that the interval between any two adjacent fragment packets is randomly distributed within the interval [ipg_min, ipg_max]. orig The plurality of fragment packets are disassembled so that the intervals between each group of adjacent fragment packets in the plurality of fragment packets are equal to the fixed packet interval value.

[0028] In some embodiments, when the scrambling circuit 100 converts the standard packet Porig When the standard packet P is decomposed into the plurality of fragmented packets, the scrambling circuit 100 can orig The source address of the standard packet P is directly applied to the source address of each of the plurality of fragmented packets, and the standard packet P orig The destination address of the standard packet P is directly applied to the destination address of each of the plurality of fragmented packets. In some embodiments, the scrambling circuit 100 may replace the standard packet P with at least one replacement source address. orig The source address of at least one fragmented packet among the plurality of fragmented packets is determined by using the source address of the at least one standard packet, and / or the destination address of the at least one fragmented packet is determined by replacing the destination address of the at least one standard packet with at least one replacement destination address.

[0029] Figure 3 According to an embodiment of the present invention, the above-mentioned scrambling operation, length scrambling and content scrambling are provided. Figure 2 An example of the workflow is shown in Figure 1. Note that Figure 3 The workflow shown is for illustrative purposes only and is not intended to limit the present invention. For example, one or more steps may be Figure 3 The steps may be added, deleted, or modified from the workflow shown. In addition, the steps do not necessarily need to be followed exactly as shown if the overall result is not changed. Figure 3 Execute in the order shown.

[0030] In step S310 , the system 10 may configure the control register 110 (eg, set the value of the mode control signal PATTERN) to enable the scrambling circuit 100 to enter the corresponding packet scrambling mode.

[0031] In step S320, the system 10 may control the packet generator 20 to generate a packet in an original correct format (eg, a standard packet P that complies with a specific network communication specification). orig )Input disturbance circuit 100.

[0032] In step S330 , the system 10 may control the scrambling circuit 100 to scramble the packet length according to its scrambling mode (eg, according to the mode control signal PATTERN).

[0033] In step S340, the system 10 may control the scrambling circuit 100 to replace the content of the fragmented packet (eg, replace the standard packet P with a specific source / destination address). orig the original source / destination address).

[0034] In step S350, the system 10 may control the scrambling circuit 100 to scramble the packet {P in} is transmitted to the data receiving port of the circuit under test 130.

[0035] In step S360, the system 10 may control the circuit under test 130 (eg, a prototype circuit of a switch chip) to detect packets (eg, scrambled packets {P in}) is processed and then transmitted to the data transmission port (for example, port P1, P2, ... and Pn).

[0036] In step S370, the system 10 may scramble the packet output by the scrambling circuit 100 (eg, the scrambling packet {P in}) and packets output by the circuit under test 130 (for example, output packets {P out1}、{P out2}, ... and {P outn}) is transmitted to the detection circuit 140 for statistics to obtain the test result.

[0037] Figure 4A FIG. 1 is a schematic diagram of a portion of a workflow for performing length scrambling on a packet according to an embodiment of the present invention. Figure 4B is a schematic diagram of another part of the workflow of performing length scrambling on a packet according to an embodiment of the present invention, and Figure 4C FIG. 1 is a schematic diagram of another part of the workflow for performing length scrambling on a packet according to an embodiment of the present invention. It should be noted that: Figure 4A , Figure 4B and / or Figure 4C The workflow shown is for illustrative purposes only and is not intended to limit the present invention. For example, one or more steps may be Figure 4A , Figure 4B and / or Figure 4C The steps may be added, deleted, or modified from the workflow shown. In addition, the steps do not necessarily need to be followed exactly as shown if the overall result is not changed. Figure 4A , Figure 4B and / or Figure 4C Execute in the order shown.

[0038] Please refer to Figure 4A ,in Figure 4A Steps S400 , S402 , S404 , S406 , S408 , S410 , S412 , S414 , S416 , S418 , and S420 are shown as follows.

[0039] In step S400, the packet generator 20 may generate a standard packet {P orig} and the standard packet {P orig} is transmitted to the scrambling circuit 100, and the process starts.

[0040] In step S402, the scrambling circuit 100 may determine whether to receive the received standard packet P according to the mode control signal PATTERN or its derivative signal. origThe disturbance is a fragmented packet. If the judgment result is "yes", the process proceeds to step S602. If the judgment result is "no", the process proceeds to step S404.

[0041] In step S404, the scrambling circuit 100 may determine whether to receive the received standard packet P according to the mode control signal PATTERN or its derivative signal. orig The disturbance is a short packet. If the judgment result is "yes", the process goes to step S502. If the judgment result is "no", the process goes to step S406.

[0042] In step S406, the scrambling circuit 100 may determine whether to receive the received standard packet P according to the mode control signal PATTERN or its derivative signal. orig The disturbance is a long packet. If the judgment result is "yes", the process proceeds to step S408. If the judgment result is "no", the process proceeds to step S414.

[0043] In step S408 , the random number generator 120 may generate a random number long_len.

[0044] In step S410, the scrambling circuit 100 may determine whether a rising edge of a receiving control signal rxdv occurs. If the determination result is "yes" (indicating that the scrambling circuit 100 begins to receive and concatenate multiple standard packets P orig ), the process goes to step S412. If the determination result is "No" (indicating that the scrambling circuit 100 has not yet started to receive the standard packet P orig ), the process returns to step S410 to perform the above judgment again.

[0045] In step S412, the scrambler circuit 100 may pull up a transmission control signal txen at the same time as the rising edge of the receive control signal rxdv appears to indicate that the scrambler circuit 100 starts to transmit the long packet. In particular, the transmission control signal txen may be kept at a high level for long_len cycles and then the transmission control signal txen may be pulled low, so that the scrambler circuit 100 sends a long packet of length long_len.

[0046] In step S414, the scrambling circuit 100 may determine whether a rising edge of the receiving control signal rxdv occurs. If the determination result is "yes" (indicating that the scrambling circuit 100 begins to receive the standard packet P with a length of ori_len), orig If the result of the determination is “No” (indicating that the scrambling circuit 100 has not yet started to receive the standard packet P), the process proceeds to step S416. orig ), the process returns to step S414 to perform the above judgment again.

[0047] In step S416, the scrambler circuit 100 may pull up the transmission control signal txen when the rising edge of the reception control signal rxdv appears to indicate that the scrambler circuit 100 starts to transmit the normal packet. In particular, the transmission control signal txen may be kept at a high level for ori_len cycles and then the transmission control signal txen may be pulled low, so that the scrambler circuit 100 sends a normal packet of length ori_len.

[0048] In step S418, the scrambling circuit S418 can determine whether the length scrambling operation has ended according to the mode control signal PATTERN or its derivative signal. If the determination result is "yes", the process proceeds to step S420. If the determination result is "no", the process proceeds to step S402.

[0049] Please refer to Figure 4B ,in Figure 4B Steps S502, S504, S506, S508, S510, S512, and S514 are shown as follows.

[0050] In step S502 , the random number generator 120 may generate a random number drop_index.

[0051] In step S504, the scrambling circuit 100 may determine whether a rising edge of the receiving control signal rxdv occurs. If the determination result is "yes" (indicating that the scrambling circuit 100 begins to receive the standard packet P with a length of ori_len), orig ), the process goes to step S506. If the determination result is "No" (indicating that the scrambling circuit 100 has not yet started to receive the standard packet P orig ), the process returns to step S504 to perform the above judgment again.

[0052] In step S506, the scrambling circuit 100 may keep the transmission control signal txen at a low level (e.g., "0") for one cycle after the rising edge of the reception control signal rxdv appears, and send a packet gap of one bit on the data line ( Figure 4B IPG) and converts the original packet data (such as the standard packet P orig data) is stored in a first-in first-out (FIFO) register (in Figure 4B is referred to as "FIFO" in the literature).

[0053] In step S508, the scrambling circuit 100 may determine whether the current index value index is equal to drop_index (in Figure 4BIn the example, the data corresponding to the current index value index is the bit data to be discarded. If the judgment result is "yes" (indicating that the data corresponding to the current index value index is the bit data to be discarded), the process proceeds to step S512. If the judgment result is "no" (indicating that the data corresponding to the current index value index is not the bit data to be discarded), the process proceeds to step S510.

[0054] In step S510 , the scramble circuit 100 may read the next data.

[0055] In step S512 , the scrambling circuit 100 may skip the next data (ie, discard and do not read the bit data corresponding to the current index value index), and then read the next data of the next data.

[0056] In step S514, the scramble circuit 100 may continue to read the remaining data in the FIFO register until the number of clock cycles of the transmit control signal txen being pulled high reaches (ori_len-1), so that the scramble circuit 100 outputs a short packet with a length of (ori_len-1) bits.

[0057] Please refer to Figure 4C ,in Figure 4C Steps S602 , S604 , S606 , S608 , S610 , S612 , S614 , and S616 are shown as follows.

[0058] In step S602, the scrambling circuit 100 can determine whether the packet length is a random number according to the mode control signal PATTERN or its derivative signal. If the determination result is "yes", the process proceeds to step S604. If the determination result is "no", the process proceeds to step S606.

[0059] In step S604 , the random number generator 120 may generate a random number frag_len.

[0060] In step S606, the scrambling circuit 100 can determine whether the currently generated fragmented packet is the first fragmented packet. If the determination result is "yes", the process proceeds to step S608. If the determination result is "no", the process proceeds to step S612.

[0061] In step S608, the scrambling circuit 100 may determine whether a rising edge of the receiving control signal rxdv occurs. If the determination result is "yes" (indicating that the scrambling circuit 100 starts to receive the standard packet P orig and generates fragmented packets by disassembling the packets), the process proceeds to step S610. If the determination result is "No" (indicating that the scrambling circuit 100 has not yet started to receive the standard packet P orig ), the process returns to step S608 to perform the above judgment again.

[0062] In step S610, the scrambler circuit 100 may pull up the transmission control signal txen when the rising edge of the reception control signal rxdv appears to indicate that the scrambler circuit 100 starts to transmit the fragmented packet. In particular, the transmission control signal txen may be kept at a high level for frag_len cycles and then the transmission control signal txen may be pulled low, so that the scrambler circuit 100 sends a fragmented packet with a length of frag_len.

[0063] In step S612, the scrambling circuit 100 may determine the packet interval (in Figure 4C If the determination result is "yes", the process proceeds to step S614. If the determination result is "no", the scrambling circuit 100 uses the preset value as the packet gap length.

[0064] In step S614 , the random number generator 120 may generate a random number ipg_len to allow the scrambling circuit to use the random number ipg_len as the inter-packet gap length.

[0065] In step S616 , the scrambling circuit 100 may send a packet gap.

[0066] Figure 5 is a standard packet P according to an embodiment of the present invention. orig Schematic diagram of packet format 700. Figure 5 As shown, the standard packet P orig The packet format 700 of the standard packet may include a plurality of fields such as a destination address field DMAC, a source address field SMAC, a plurality of tag fields such as CPUTAG, OTAG and ITAG, a length field LENGTH, a data field DATA and a check field FCS. orig The destination address field DMAC and the source address field SMAC are scrambled.

[0067] Specifically, the embodiment of the present invention is intended to test whether the prototype circuit of the switch chip can identify the addresses of all the disrupted packets. However, since the fragmented packets are obtained by disassembling the standard packets P orig Therefore, most of the fragmented packets do not contain their own address information, but are obtained by copying the original packet (such as the standard packet P orig For the fragment packets that do not contain their own address information but meet the length requirements, the scrambling circuit 100 can perform content scrambling, such as Figure 6 shown. Figure 6 According to an embodiment of the present invention, a standard packet Porig Schematic diagram of the workflow of content scrambling using the destination address field DMAC and the source address field SMAC. It should be noted that Figure 6 The workflow shown is for illustrative purposes only and is not intended to limit the present invention. For example, one or more steps may be Figure 6 The steps may be added, deleted, or modified from the workflow shown. In addition, the steps do not necessarily need to be followed exactly as shown if the overall result is not changed. Figure 6 Execute in the order shown.

[0068] In step S810 , the scrambling circuit 100 may obtain fragmented packets by length scrambling.

[0069] In step S820, the scrambling circuit 100 can determine whether the length of the fragmented packet is greater than a predetermined number of bits (e.g., the total number of bits of the destination address field DMAC and the source address field SMAC, such as 12 bits). If the determination result is "yes" (indicating that the fragmented packet has a complete destination address field DMAC and source address field SMAC), the process proceeds to step S830. If the determination result is "no" (indicating that the fragmented packet does not have a complete destination address field DMAC and source address field SMAC and address replacement cannot be performed), the process proceeds to step S850.

[0070] In step S830, the scrambling circuit 100 may replace the content corresponding to the index value in the range [0,5] (eg, the content of the first to sixth bits) in the fragmented packet with DMAC_replace (eg, Figure 5 The destination address field DMAC is shown replaced with DMAC_replace).

[0071] In step S840, the scrambling circuit 100 may replace the content corresponding to the index value in the range [6, 11] (eg, the content of the seventh to twelfth bits) in the fragmented packet with SMAC_replace (eg, Figure 5 The destination address field SMAC shown is replaced with SMAC_replace).

[0072] In step S850 , the scrambling circuit 100 has finished the above-mentioned scrambling process for the contents of the destination address field DMAC and the source address field SMAC.

[0073] In addition, in order to ensure that the switch chip does not fail when receiving some packets that are truncated right after the tag field, the scrambling circuit 100 can generate a scrambled packet P containing only the destination address field DMAC, the source address field SMAC, and the tag fields CPUTAG, OTAG, and ITAG. inTo the circuit under test 130, to determine whether the circuit under test 130 can properly handle such a situation. For example, the mode control signal PATTERN can be configured as 4'b0001, and the scramble circuit 100 is controlled to use the total length of the destination address field DMAC, the source address field SMAC, and the tag fields CPUTAG, OTAG, and ITAG (for example, 28 bits) as the fixed length of the fragmented packet (for example, frag_len is fixed to 28), so that the fragmented packet generated by the scramble circuit 100 only includes the destination address field DMAC, the source address field SMAC, and the tag fields CPUTAG, OTAG, and ITAG.

[0074] In some embodiments, the detection circuit 140 may detect the scrambling packet {P in} to obtain at least one first statistical result, and for the output packet {P out1}、{P out2}, ... and {P outn} Perform statistics to obtain at least one second statistical result, wherein the detection circuit 140 can compare the at least one first statistical result and the at least one second statistical result to see if they match, so as to verify the operation of the circuit under test 130 (for example, the packet processing / forwarding operation of the prototype of the switch chip).

[0075] The scrambling packet {P in}, the detection circuit 140 can count the total number of packets D_total_cnt whose source address is the input port of the circuit under test 130, the destination address is within the range of the output port of the circuit under test 130 (e.g., P1 to Pn), the packet length meets the specific network communication specification, the check code (e.g., the content of the check field FCS) is correct, and / or the packet gap length before the packet meets the specific network communication specification. In addition, the detection circuit 140 can count the destination address corresponding to each port to obtain the number of packets D_P_cnt(k) corresponding to each port, where k is an arbitrary integer in the interval [1, n]. For the output packet {P_cnt(k) output by the circuit under test 130, out1}、{P out2}, ... and {P outn}, the detection circuit 140 can perform corresponding statistical operations to obtain the total number of packets S_total_cnt of all ports and the number of packets S_P_cnt(k) corresponding to each port. Therefore, the total number of packets D_total_cnt and the number of packets D_P_cnt(k) corresponding to each port can be used as an expected statistical result (such as the first statistical result mentioned above), and the total number of packets S_total_cnt and the number of packets S_P_cnt(k) corresponding to each port can be used as an actual statistical result (such as the second statistical result mentioned above), wherein the detection circuit 140 can compare the expected statistical result with the actual statistical result (for example, determine whether D_total_cnt is equal to S_total_cnt and D_P_cnt(k) is equal to S_P_cnt(k)) to determine whether the circuit under test 130 (such as the prototype circuit of the switch chip) can correctly handle various types of disturbing packets.

[0076] Figure 7 Schematic diagram of a control scheme when the mode control signal PATTERN is set to 4'b0110 according to an embodiment of the present invention. Specifically, the scrambling circuit 100 can generate a large number of long packets and a small number of normal packets in this mode, wherein the number of long packets and normal packets can be controlled by the random number generated by the random number generator 120. For example, the random number generator 120 can generate a length random number long_len in the interval [1519, max_long_len], a packet interval random number ipg_len in the interval [ipg_min, ipg_max], a long packet random number long_num_lot in the interval [32, 255], and a normal packet random number good_num_few in the interval [1, 31].

[0077] When the scrambler circuit 100 detects that PATTERN is equal to 4'b0110, the scrambler circuit 100 may enter the long packet state GEN_LONG from the idle state IDLE. When the scrambler circuit 100 detects the rising edge of the receive control signal rxdv, the transmit control signal txen may be pulled high and start timing to generate a timing result len_cnt, wherein the timing result len_cnt may represent the number of cycles during which the transmit control signal txen is at a high level. When the timing result len_cnt reaches long_len, the scrambler circuit 100 may pull the transmit control signal txen low, wherein the data output by the scrambler circuit 100 during this period is consistent with the original packet (e.g., the standard packet P orig ) remains the same without any change. At this point, a long packet with a length of long_len is sent, and the long packet count result long_cnt is accumulated to 1.

[0078] After the transmission control signal txen is pulled low, the scrambling circuit 100 can start timing to generate a timing result ipg_cnt. When the timing result ipg_cnt is equal to the random number of the packet interval ipg_len, a packet interval of the length ipg_len has been sent.

[0079] The scrambling circuit 100 can determine whether the long packet counting result long_cnt reaches the long packet random number long_num_lot. If the long packet counting result long_cnt is not equal to the long packet random number long_num_lot, it means that the operation of sending long packets has not yet ended, and the scrambling circuit 100 can continue to send long packets, and the random number generator can generate a new random number to update long_len (so that the length of each long packet is randomly distributed). If the long packet counting result long_cnt is equal to the long packet random number long_num_lot, it means that the specified number of long packets have been sent, and the scrambling circuit 100 can enter the normal packet state GEN_GOOD from the long packet state GEN_LONG to start sending normal packets.

[0080] In the normal packet state GEN_GOOD, the scramble circuit 100 may pull the transmission control signal txen high and start timing to generate a timing result len_cnt when detecting the rising edge of the receiving control signal rxdv. When the timing result len_cnt reaches a preset value good_len, the scramble circuit 100 may pull the transmission control signal txen low, wherein the data output by the scramble circuit 100 during this period is consistent with the original packet (e.g., the standard packet P orig ) remains consistent without any change. At this point, a normal packet with a length of good_len is sent, and the normal packet count result good_cnt is accumulated to 1.

[0081] The scrambling circuit 100 can determine whether the normal packet counting result good_cnt reaches the normal packet random number good_num_few. If the normal packet counting result good_cnt is not equal to the normal packet random number good_num_few, it means that the operation of sending normal packets has not yet ended, and the scrambling circuit 100 can continue to send normal packets. If the normal packet counting result good_cnt is equal to the normal packet random number good_num_few, it means that the specified number of normal packets have been sent, and the scrambling circuit 100 can enter the long packet state GEN_LONG from the normal packet state GEN_GOOD to start sending long packets.

[0082] As described above, the scramble circuit 100 can continuously switch between the long packet state GEN_LONG and the normal packet state GEN_GOOD during operation in this mode until the scramble operation ends. For example, when the scramble circuit 100 detects that the mode control signal PATTERN is switched to other values ​​such as 4'b0000, the scramble circuit 100 can return to the idle state.

[0083] In summary, the system and method provided by the embodiments of the present invention can utilize a scrambling circuit to scramble the original packets (e.g., packets that meet the specification requirements) to generate various types of permutations and combinations of scrambled packets. In this way, the prototype circuit of the switch chip can be verified by a field-editable logic gate array prototype before the switch chip is manufactured to ensure that the switch chip will not fail in actual application scenarios due to encountering these packets that do not meet the specification requirements. In addition, the embodiments of the present invention will not significantly increase additional costs. Therefore, the present invention can solve the problems of the related art without side effects or with less side effects.

[0084] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

[0085]

Explanation of symbols

[0086] 10: System

[0087] 20: Packet Generator

[0088] 50: Field editable logic gate array

[0089] 100: Disrupt the circuit

[0090] 110: Control register

[0091] 120: Random number generator

[0092] 130: Circuit under test

[0093] 140: Detection circuit

[0094] P orig :Standard Packet

[0095] P in :Scramble Packet

[0096] P out1 ,P out2 ,P outn :Output Packet

[0097] P1,P2,Pn:Port

[0098] PATTERN: Pattern control signal

[0099] S210~S240: Steps

[0100] S310~S370: Steps

[0101] S400~S420: Steps

[0102] S502~S514: Steps

[0103] S602~S616: Steps

[0104] 700:Packet format

[0105] DMAC,SMAC,CPUTAG,OTAG,ITAG,LENGTH,DATA,FCS:field

[0106] S810~S850: Steps

[0107] IDLE,GEN_LONG,GEN_GOOD: Status

[0108] long_cnt,good_cnt: counting results

[0109] long_num_lot: long packet random number

[0110] good_num_few: normal packet random number.

Claims

1. A system for prototyping a field-editable logic gate array of a circuit under test, wherein: The system includes the circuit to be tested, and the system also includes: a packet generator, configured to output one or more standard packets, wherein the length of each of the one or more standard packets falls within a standard range; a scrambling circuit, coupled to the packet generator and the circuit under test, for receiving the one or more standard packets and generating one or more scrambling packets according to the one or more standard packets for output to the circuit under test, so that the circuit under test generates one or more output packets according to the one or more scrambling packets, wherein the length of any one of the one or more scrambling packets falls outside the standard range; and a detection circuit coupled to the scrambling circuit and the circuit to be tested, for receiving the one or more scrambling packets and the one or more output packets, and verifying the operation of the circuit to be tested according to the one or more scrambling packets and the one or more output packets; The disturbing circuit, the circuit to be tested and the detecting circuit are implemented on a field programmable logic gate array.

2. The system according to claim 1, wherein: The scrambling circuit disassembles at least one of the one or more standard packets into a plurality of fragment packets, each of which has a length less than a minimum length within the standard range, and the one or more scrambled packets include the plurality of fragment packets.

3. The system according to claim 2, wherein: The scrambling circuit replaces the source address of the at least one standard packet with at least one replacement source address to determine the source address of at least one fragmented packet among the multiple fragmented packets, or replaces the destination address of the at least one standard packet with at least one replacement destination address to determine the destination address of at least one fragmented packet among the multiple fragmented packets.

4. The system according to claim 2, wherein: The scrambling circuit disassembles the at least one standard packet into a plurality of fragment packets according to a plurality of random numbers within a predetermined range, so that the lengths of the plurality of fragment packets are respectively the plurality of random numbers.

5. The system according to claim 2, wherein: The scrambling circuit disassembles the at least one standard packet into multiple fragment packets according to a fixed number so that the length of each of the multiple fragment packets is equal to the fixed number. Each standard packet of the one or more standard packets includes a destination address field, a source address field, multiple tag fields, a length field, a data field and a check field. The total length of the destination address field, the source address field and the multiple tag fields is equal to a predetermined number of bits. The scrambling circuit sets the fixed number to the predetermined number of bits so that at least one fragment packet among the multiple fragment packets only includes the destination address field, the source address field and the multiple tag fields.

6. The system according to claim 2, wherein: The scrambling circuit disassembles the at least one standard packet into a plurality of fragment packets according to at least one random number within a predetermined range, so that the interval between any two adjacent fragment packets in the plurality of fragment packets is equal to the at least one random number.

7. The system according to claim 1, wherein: The scrambling circuit reduces the length of at least one of the one or more standard packets by one bit to generate at least one short packet, and the one or more scrambled packets include the at least one short packet.

8. The system according to claim 1, wherein: The scrambling circuit concatenates multiple standard packets in the one or more standard packets into at least one long packet, the length of the at least one long packet is greater than a maximum length within the standard range, and the one or more scrambled packets include the at least one long packet.

9. The system according to claim 1, wherein: The one or more scrambled packets include at least two of at least one fragmented packet, at least one short packet, at least one long packet, and at least one normal packet, the length of the at least one fragmented packet being less than a minimum length within the standard range, the length of the at least one short packet being equal to the length of at least one standard packet among the one or more standard packets minus one bit, and the at least one normal packet being equal to any one of the one or more standard packets.

10. A method for prototyping a field editable logic gate array of a circuit under test, comprising: Outputting one or more standard packets using a packet generator, wherein: The length of each of the one or more standard packets falls within a standard range; Using a scrambling circuit to receive the one or more standard packets and generate one or more scrambled packets based on the one or more standard packets, wherein the length of any one of the one or more scrambled packets falls outside the standard range; Utilizing the circuit under test to receive the one or more scrambled packets, and generating one or more output packets according to the one or more scrambled packets; as well as Using a detection circuit to receive the one or more scrambling packets and the one or more output packets, and verifying the operation of the circuit under test according to the one or more scrambling packets and the one or more output packets; The disturbing circuit, the circuit to be tested and the detecting circuit are implemented on a field programmable logic gate array.

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