Silicon carbide power semiconductor device
By introducing specific structural designs in silicon carbide power semiconductor devices, including the N-drift layer and the polysilicon gate layer, and the connection of block pairs, the problem of spike voltage when the device is turned off is solved, and the reliability and service life of the device are improved.
Patent Information
- Application Number
- CN202411664253.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2022-03-25
- Publication Date
- 2025-03-14
AI Technical Summary
Silicon carbide power semiconductor devices may experience spike voltage when shut down, causing the drain voltage to exceed the rated voltage, increasing the risk of the bomb and shortening the service life.
By introducing an N-drift layer and a polysilicon gate layer into the silicon carbide power semiconductor device, and setting up several pairs of block regions connected by the polysilicon P-type block region and the N-type block region, it is ensured that when the MOSFET is turned off, the drain voltage VD does not exceed the maximum voltage stabilization value of the gate voltage VG.
It effectively curbs the generation of spike voltage, ensures that the drain voltage at shutdown does not exceed the rated voltage, reduces the occurrence of bombs, and extends the service life of the device.
Smart Images
Figure CN119630037A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of power semiconductor devices, and in particular to a silicon carbide power semiconductor device. Background Art
[0002] Silicon carbide (SiC) is a third-generation semiconductor material. Compared with existing silicon materials, it has the advantages of wide bandgap, high critical breakdown electric field, and high saturation drift speed. MOSFET devices made of SiC materials have the advantages of low on-resistance, small size, and fast switching speed compared with silicon-based MOSFETs with the same voltage resistance level.
[0003] MOSFET devices are generally used as high-power switching devices in circuits. For switching devices, they are generally in the linear region when turned on, that is, the device is in a low on-voltage and high on-current mode; when the switch is turned off, the device is in the cut-off region, at which both ends of the device can withstand high voltage and only have very small leakage current. Therefore, under normal working conditions, MOSFET devices will not bear high voltage and high current at the same time. Summary of the invention
[0004] The purpose of the present invention is to provide a silicon carbide power semiconductor device, which curbs the generation of spike voltage. When the MOSFET is turned off, the drain voltage VD will not exceed the maximum regulated value of the gate voltage VG due to the voltage stabilization effect of the voltage stabilization area, so that the drain voltage when turned off will not exceed its rated voltage, reducing the occurrence of machine explosion and extending the service life of the device. It also overcomes the phenomenon that the application voltage exceeds the rated voltage when the power supply fluctuates. When a suitable VZ is set, the silicon carbide power semiconductor device can be applied to the maximum extent, so that its voltage application range is as close to the rated voltage as possible, expanding the application scenario and improving reliability.
[0005] To achieve the above-mentioned purpose, the technical solution adopted by the present invention is: a silicon carbide power semiconductor device, comprising at least two device cells, wherein the device cell further comprises: an N+ type substrate layer and an N-drift layer located on the upper part of the N+ type substrate layer, wherein the upper part of the N-drift layer has a P-type base region, and the upper part of the P-type base region has a left N+ body region, a P+ type source region, and a right N+ body region connected in sequence in the horizontal direction, wherein the left N+ body region and the right N+ body region are each isolated from the N-drift layer on one side opposite to the P+ type source region by the P-type base region, and the upper surfaces of the left N+ body region and the left side of the P-type base region are each covered with a first gate oxide layer, and the upper surfaces of the right N+ body region and the right side of the P-type base region are each covered with a second gate oxide layer; The first gate oxide layer and the second gate oxide layer are each covered with a polysilicon gate layer on their upper surfaces, the polysilicon gate layer is covered with a dielectric layer on its upper surface, a source metal layer is in electrical contact with the P+ type source region, a gate metal layer is in electrical contact with the polysilicon gate layer, and a drain metal layer is in electrical contact with the lower surface of the N+ type substrate layer; The upper surface of the N-drift layer is covered with a first metal layer, the first metal layer is electrically connected to a first polysilicon N-type block area, a first polysilicon P-type block area is electrically connected to a polysilicon gate layer, and a plurality of block area pairs consisting of a second polysilicon P-type block area and a second polysilicon N-type block area are sequentially arranged between the first polysilicon N-type block area and the first polysilicon P-type block area, and the second polysilicon P-type block area in each pair of block areas is connected to the second polysilicon N-type block area in an adjacent pair of block areas; The N-drift layer has a P+ protection column in the area between adjacent device cells. The upper end of the P+ protection column extends to the upper surface of the N-drift layer, and the lower end of the P+ protection column extends to the middle of the N-drift layer.
[0006] The further improved scheme in the above technical scheme is as follows: 1. In the above solution, the contact surface between the P-type base region and the N-drift layer is an arc-shaped surface.
[0007] 2. In the above scheme, the surface shape of the left N+ body region, the right N+ body region in contact with the P-type base region is a semicircular arc.
[0008] 3. In the above scheme, the depth ratio of the N-drift layer to the P-type base region is 10:6~8.
[0009] 4. In the above solution, the depth of the left N+ body region and the right N+ body region are both greater than the depth of the P+ type source region.
[0010] 5. In the above scheme, the depth ratio of the left N+ body region, the right N+ body region and the P-type base region is 10:20~35.
[0011] 6. In the above solution, an insulating layer is provided between the first polysilicon N-type block region, the first polysilicon P-type block region and the N-drift layer.
[0012] 7. In the above solution, an insulating layer is provided between the pair of block areas.
[0013] Due to the application of the above technical solution, the present invention has the following advantages compared with the prior art: 1. The silicon carbide power semiconductor device of the present invention, wherein the upper surface of the N-drift layer is covered with a first metal layer, the first metal layer is electrically connected to the first polysilicon N-type block area, a first polysilicon P-type block area is electrically connected to the polysilicon gate layer, and a plurality of block area pairs consisting of a second polysilicon P-type block area and a second polysilicon N-type block area are sequentially arranged between the first polysilicon N-type block area and the first polysilicon P-type block area, and the second polysilicon P-type block area in each pair of block areas is connected to the second polysilicon N-type block area in the adjacent block area pair, thereby suppressing the generation of spike voltage When the MOSFET is turned off, the drain voltage VD will not exceed the maximum regulated value of the gate voltage VG due to the regulated effect of the regulated area, so that the drain voltage when turned off will not exceed its rated voltage, reducing the occurrence of machine explosion and extending the service life of the device. It also overcomes the phenomenon that the application voltage exceeds the rated voltage when the power supply fluctuates. When the appropriate VZ is set, the silicon carbide power semiconductor device can be applied to the maximum extent, making its voltage application range as close to the rated voltage as possible, expanding the application scenarios and improving reliability.
[0014] 2. The silicon carbide power semiconductor device of the present invention has an N-drift layer located in the area between adjacent device cells and has a P+ protection column. The upper end of the P+ protection column extends to the upper surface of the N-drift layer, and the lower end of the N-doped deep well portion extends to the middle of the N-drift layer, so that the electric field curve tends to be flat, the increase in leakage current is improved, and the isolation performance between device cells is enhanced, thereby further improving the overall reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Attached Figure 1 It is a front view structural schematic diagram of the silicon carbide power semiconductor device of the present invention; Attached Figure 2 It is a front perspective schematic diagram of a silicon carbide power semiconductor device of the present invention; Attached Figure 3 It is a rear perspective schematic diagram of the silicon carbide power semiconductor device of the present invention.
[0016] In the above figures: 1, N+ type substrate layer; 2, N- drift layer; 3, P- type base region; 41, left N+ body region; 42, right N+ body region; 5, P+ type source region; 61, first gate oxide layer; 62, second gate oxide layer; 7, polysilicon gate layer; 8, dielectric layer; 9, source metal layer; 10, gate metal layer; 11, drain metal layer; 12, first metal layer; 131, first polysilicon N-type block region; 132, first polysilicon P-type block region; 14, block region pair; 141, second polysilicon P-type block region; 142, second polysilicon N-type block region; 15, insulating layer; 16, P+ protection column; 17, device unit cell. DETAILED DESCRIPTION
[0017] The present invention can be further understood through the specific embodiments given below, but they are not intended to limit the present invention.
[0018] Embodiment 1: A silicon carbide power semiconductor device, comprising at least two device cells 17, wherein the device cell 17 further comprises: an N+ substrate layer 1 and an N-drift layer 2 located on the upper part of the N+ substrate layer 1, wherein the upper part of the N-drift layer 2 has a P-type base region 3, and the upper part of the P-type base region 3 has a left N+ body region 41, a P+ source region 5, and a right N+ body region 42 connected in sequence in a horizontal direction, wherein the left N+ body region 41 and the right N+ body region 42 are each isolated from the N-drift layer 2 on a side opposite to the P+ source region 5 by the P-type base region 3, and the upper surfaces of the left N+ body region 41 and the left side of the P-type base region 3 are each covered with a first gate oxide layer 61, and the upper surfaces of the right N+ body region 42 and the right side of the P-type base region 3 are each covered with a second gate oxide layer 62; The first gate oxide layer 61 and the second gate oxide layer 62 are each covered with a polysilicon gate layer 7 on their upper surfaces, the polysilicon gate layer 7 is covered with a dielectric layer 8 on its upper surface, a source metal layer 9 is in electrical contact with the P+ type source region 5, a gate metal layer 10 is in electrical contact with the polysilicon gate layer 7, and a drain metal layer 11 is in electrical contact with the lower surface of the N+ type substrate layer 1; The upper surface of the N-drift layer 2 is covered with a first metal layer 12, the first metal layer 12 is electrically connected to a first polysilicon N-type block 131, a first polysilicon P-type block 132 is electrically connected to the polysilicon gate layer 7, and a plurality of pairs of block area pairs 14 consisting of a second polysilicon P-type block area 141 and a second polysilicon N-type block area 142 are sequentially arranged between the first polysilicon N-type block area 131 and the first polysilicon P-type block area 132, and the second polysilicon P-type block area 141 in each pair of block area pairs 14 is connected to the second polysilicon N-type block area 142 in the adjacent block area pair 14; The N-drift layer 2 has a P+ protection column 16 located between adjacent device cells 17 . The upper end of the P+ protection column 16 extends to the upper surface of the N-drift layer 2 , and the lower end of the P+ protection column 16 extends to the middle of the N-drift layer 2 .
[0019] The surface shape of the left N+ body region 41 and the right N+ body region 42 contacting the P-type base region 3 is a semicircular arc.
[0020] The depth ratio of the N-drift layer 2 to the P-type base region 3 is 10:7.8.
[0021] The left N+ body region 41 and the right N+ body region 42 have the same depth, and the depth ratio of the P+ type source region 5 to the P- type base region 3 is 10:35.
[0022] Embodiment 2: A silicon carbide power semiconductor device, comprising at least two device cells 17, wherein the device cell 17 further comprises: an N+ substrate layer 1 and an N-drift layer 2 located on the upper part of the N+ substrate layer 1, wherein the upper part of the N-drift layer 2 has a P-type base region 3, and the upper part of the P-type base region 3 has a left N+ body region 41, a P+ source region 5, and a right N+ body region 42 connected in sequence in a horizontal direction, wherein the left N+ body region 41 and the right N+ body region 42 are each isolated from the N-drift layer 2 on a side opposite to the P+ source region 5 by the P-type base region 3, and the upper surfaces of the left N+ body region 41 and the left side of the P-type base region 3 are each covered with a first gate oxide layer 61, and the upper surfaces of the right N+ body region 42 and the right side of the P-type base region 3 are each covered with a second gate oxide layer 62; The first gate oxide layer 61 and the second gate oxide layer 62 are each covered with a polysilicon gate layer 7 on their upper surfaces, the polysilicon gate layer 7 is covered with a dielectric layer 8 on its upper surface, a source metal layer 9 is in electrical contact with the P+ type source region 5, a gate metal layer 10 is in electrical contact with the polysilicon gate layer 7, and a drain metal layer 11 is in electrical contact with the lower surface of the N+ type substrate layer 1; The upper surface of the N-drift layer 2 is covered with a first metal layer 12, the first metal layer 12 is electrically connected to a first polysilicon N-type block 131, a first polysilicon P-type block 132 is electrically connected to the polysilicon gate layer 7, and a plurality of pairs of block area pairs 14 consisting of a second polysilicon P-type block area 141 and a second polysilicon N-type block area 142 are sequentially arranged between the first polysilicon N-type block area 131 and the first polysilicon P-type block area 132, and the second polysilicon P-type block area 141 in each pair of block area pairs 14 is connected to the second polysilicon N-type block area 142 in the adjacent block area pair 14; The N-drift layer 2 has a P+ protection column 16 located between adjacent device cells 17 . The upper end of the P+ protection column 16 extends to the upper surface of the N-drift layer 2 , and the lower end of the P+ protection column 16 extends to the middle of the N-drift layer 2 .
[0023] The surface shape of the left N+ body region 41 and the right N+ body region 42 contacting the P-type base region 3 is a semicircular arc.
[0024] The depth ratio of the N-drift layer 2 to the P-type base region 3 is 10:7.8.
[0025] The depth ratio of the left N+ body region 41, the right N+ body region 42 and the P-type base region 3 is 10:25.
[0026] The left N+ body region 41 and the right N+ body region 42 have the same depth, and the depth ratio of the P+ type source region 5 to the P- type base region 3 is 10:38.
[0027] When the above silicon carbide power semiconductor device is used, the upper surface of the N-drift layer is covered with a first metal layer, the first metal layer is electrically connected to the first polysilicon N-type block area, a first polysilicon P-type block area is electrically connected to the polysilicon gate layer, and a plurality of block area pairs consisting of a second polysilicon P-type block area and a second polysilicon N-type block area are sequentially arranged between the first polysilicon N-type block area and the first polysilicon P-type block area, and the second polysilicon P-type block area in each pair of block areas is connected to the second polysilicon N-type block area in the adjacent block area pair, thereby curbing the generation of spike voltage. When the MOSFET is turned off, the drain voltage VD will not exceed the maximum regulated value of the gate voltage VG due to the regulated effect of the regulated area, so that the drain voltage when turned off will not exceed its rated voltage, reducing the occurrence of machine explosion and extending the service life of the device. It also overcomes the phenomenon that the application voltage exceeds the rated voltage when the power supply fluctuates. When the appropriate VZ is set, the silicon carbide power semiconductor devices can be applied to the maximum extent, making its voltage application range as close to the rated voltage as possible, expanding the application scenarios and improving reliability.
[0028] In addition, the N-drift layer is provided with a P+ protection column in the area between adjacent device cells, the upper end of the P+ protection column extends to the upper surface of the N-drift layer, and the lower end of the N-doped deep well portion extends to the middle of the N-drift layer, so that the electric field curve tends to be flat, the increase in leakage current is improved, and the isolation performance between device cells is enhanced, thereby further improving the overall reliability of the device.
[0029] The above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.
Claims
1. A silicon carbide power semiconductor device, characterized in that: The device unit cell (17) comprises at least two device units (17), wherein the device unit cell (17) further comprises: an N+ type substrate layer (1) and an N- type drift layer (2) located on the upper part of the N+ type substrate layer (1); the upper part of the N- type drift layer (2) comprises a P- type base region (3); the upper part of the P- type base region (3) comprises a left N+ body region (41), a P+ type source region (5), and a right N+ body region (42) connected in sequence in a horizontal direction; the left N+ body region (41) and the right N+ body region (42) are each isolated from the N- drift layer (2) on a side opposite to the P+ type source region (5) by the P- type base region (3); the left upper surfaces of the left N+ body region (41) and the P- type base region (3) are each covered with a first gate oxide layer (61); the right upper surfaces of the right N+ body region (42) and the P- type base region (3) are each covered with a second gate oxide layer (62); The first gate oxide layer (61) and the second gate oxide layer (62) are each covered with a polysilicon gate layer (7) on their upper surfaces, the polysilicon gate layer (7) being covered with a dielectric layer (8) on its upper surface, a source metal layer (9) being in electrical contact with the P+ type source region (5), a gate metal layer (10) being in electrical contact with the polysilicon gate layer (7), and a drain metal layer (11) being in electrical contact with the lower surface of the N+ type substrate layer (1); The upper surface of the N-drift layer (2) is covered with a first metal layer (12), the first metal layer (12) is electrically connected to a first polysilicon N-type block region (131), a first polysilicon P-type block region (132) is electrically connected to the polysilicon gate layer (7), a plurality of pairs of block region pairs (14) consisting of a second polysilicon P-type block region (141) and a second polysilicon N-type block region (142) are sequentially arranged between the first polysilicon N-type block region (131) and the first polysilicon P-type block region (132), and the second polysilicon P-type block region (141) in each pair of block region pairs (14) is connected to the second polysilicon N-type block region (142) in an adjacent block region pair (14); The N-drift layer (2) is provided with a P+ protection column (16) in a region between adjacent device cells (17), the upper end of the P+ protection column (16) extending to the upper surface of the N-drift layer (2), and the lower end of the P+ protection column (16) extending to the middle of the N-drift layer (2); The depth ratio of the N-drift layer (2) to the P-type base region (3) is 10:6-8, the depth of the left N+ body region (41) and the right N+ body region (42) are both greater than the depth of the P+ type source region (5), the depth ratio of the left N+ body region (41), the right N+ body region (42) to the P-type base region (3) is 10:20-35; and the depth ratio of the P+ type source region (5) to the P-type base region (3) is 10:30-40.
2. The silicon carbide power semiconductor device according to claim 1, characterized in that: The depth ratio of the N-drift layer (2) to the P-type base region (3) is 10:7.
8.
3. The silicon carbide power semiconductor device according to claim 1, characterized in that: The surface shapes of the left N+ body region (41), the right N+ body region (42) and the P-type base region (3) in contact with each other are semicircular.
4. The silicon carbide power semiconductor device according to claim 1, characterized in that: An insulating layer (15) is provided between the first polysilicon N-type block region (131), the first polysilicon P-type block region (132) and the N-drift layer (2).
5. The silicon carbide power semiconductor device according to claim 7, characterized in that: The depth ratio of the left N+ body region (41), the right N+ body region (42) and the P-type base region (3) is 10:25.