Method for manufacturing printed wiring board

Abstract

After an insulating layer (14) and an electrolytic copper foil (15) are laminated in this order on an inner layer substrate (13), a resist pattern (17B) is formed on the electrolytic copper foil (15). Next, with the resist pattern (17B) as a resist, the electrolytic copper foil (15) is etched using an etching solution containing sulfuric acid and hydrogen peroxide, and a via hole formation mask (18) is formed. Next, the resist pattern (17B) is removed, and a via hole (14A) is formed by removing a portion of the insulating layer (14) that is not covered by the via hole formation mask (18) with a laser.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a printed wiring board having a via hole. Background Art

[0002] In recent years, in addition to the miniaturization and high performance of semiconductor elements, the high density, multi-layering, small diameter and high precision of the via holes of the printed wiring board equipped with semiconductor elements have also become indispensable. The printed wiring board is miniaturized, for example, by using a laser in the formation of the via holes in the lamination process. As a method of forming via holes using a laser, for example, the following method can be cited. First, an insulating layer and an electrolytic copper foil are formed in sequence on an inner layer substrate on which an inner layer circuit is formed, and an anti-etching layer is provided on the surface of the electrolytic copper foil, and exposure and development are performed to form an anti-etching pattern in which the portion used to form the via hole is removed. Then, the electrolytic copper foil is etched using the anti-etching pattern as an anti-etching agent. After forming a mask for forming the via hole, the portion of the insulating layer not covered by the mask for forming the via hole is removed by laser to form the via hole. As an etching solution for etching the electrolytic copper foil, for example, a cupric chloride aqueous solution can be used (for example, refer to Patent Document 1).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: International Publication No. WO2018 / 026004 Summary of the invention

[0006] Problem that the invention aims to solve

[0007] However, since the etching amount of electrolytic copper foil is large when etching with a cupric chloride aqueous solution, it is not easily affected by the opening diameter of the resist pattern, and the opening diameter of the via hole forming mask becomes large, which makes it difficult to process small-diameter via holes.

[0008] The present invention has been made based on the above-mentioned problems, and an object of the present invention is to provide a method for manufacturing a printed wiring board capable of performing small-diameter hole processing of via holes.

[0009] Solutions for solving problems

[0010] The present invention is as follows. [1]

[0012] A method for manufacturing a printed wiring board, characterized in that it includes: a step of sequentially stacking an insulating layer and an electrolytic copper foil on an inner layer substrate having an inner layer circuit formed thereon to form a multilayer board;

[0013] A process of providing an anti-etching layer on the electrolytic copper foil, exposing and developing the layer, and forming an anti-etching pattern from which a portion for forming a via hole is removed;

[0014] After forming the resist pattern, the electrolytic copper foil is etched using an etching solution containing sulfuric acid and hydrogen peroxide using the resist pattern as a resist to form a mask for forming a via hole;

[0015] After forming the via hole forming mask, removing the resist pattern; and

[0016] A step of removing the resist pattern and then removing the portion of the insulating layer not covered by the via hole forming mask by laser to form a via hole. [2]

[0018] The method for manufacturing a printed wiring board according to [1], further comprising a step of removing scum after forming the resist pattern and before forming the via hole forming mask. [3]

[0020] The method for manufacturing a printed wiring board according to [1] is characterized in that the etching rate of the etching solution is 0.5 μm·m / min to 20 μm·m / min. [4]

[0022] The method for producing a printed wiring board according to [1], wherein the etching solution contains 0.1 w / v% to 10 w / v% of hydrogen peroxide and 0.5 w / v% to 9 w / v% of sulfuric acid. [5]

[0024] The method for producing a printed wiring board according to [1], wherein the etching solution contains 0.1 w / v% to 5 w / v% of alcohol. [6]

[0026] The method for producing a printed wiring board according to [1], wherein the etching solution contains an azole or a salt thereof. [7]

[0028] The method for producing a printed wiring board according to [6], wherein the azole is a heterocyclic compound having a five-membered heterocyclic ring or a condensed heterocyclic ring thereof having two nitrogen atoms. [8]

[0030] The method for producing a printed wiring board according to [7], wherein the azole is at least one selected from the group consisting of pyrazoles, imidazoles, and benzimidazoles. [9]

[0032] The method for producing a printed wiring board according to [8], wherein the azole is at least one selected from the group consisting of compounds represented by the following general formula (1), (2) or (3):

[0033]

[0034] In the above general formula (1), (2) or (3), R 1 , R 2 , R 3 , R 4 , R 5 and R 6 Each independently is a hydrogen atom, C 1 ~C 6 Alkyl, C 6 ~C 10 Aryl, Carboxyl, Carboxyl C 1 ~C 6 Alkyl, nitro, hydroxyl, C 2 ~C 7 carboxylate or a halogen atom.

[10]

[0036] The method for producing a printed wiring board according to [1], wherein the etching solution contains glycol ethers.

[11]

[0038] The method for manufacturing a printed wiring board according to [1], wherein the etching solution contains halide ions.

[12]

[0040] The method for producing a printed wiring board according to

[11] , wherein the halide ions are chloride ions.

[13]

[0042] A method for manufacturing a printed wiring board, characterized in that it includes: a step of sequentially stacking an insulating layer and an electrolytic copper foil on an inner layer substrate having an inner layer circuit formed thereon to form a multilayer board;

[0043] A process of providing an anti-etching layer on the electrolytic copper foil, exposing and developing the layer, and forming an anti-etching pattern from which a portion for forming a via hole is removed;

[0044] After forming the resist pattern, removing scum;

[0045] After removing the scum, the electrolytic copper foil is etched using an etching solution using the resist pattern as a resist to form a mask for forming a via hole;

[0046] After forming the via hole forming mask, removing the resist pattern; and

[0047] A step of removing the resist pattern and then removing the portion of the insulating layer not covered by the mask by laser to form a via hole.

[0048] Effects of the Invention

[0049] According to the present invention, when etching the electrolytic copper foil to form a mask for forming a via hole, the etching amount can be reduced because an etching solution containing sulfuric acid and hydrogen peroxide is used. This makes it easier to be affected by the opening diameter of the resist pattern, and the opening diameter of the mask for forming the via hole can be reduced, thereby reducing the aperture of the via hole.

[0050] In addition, according to the present invention, since scum is removed after forming the resist pattern, the opening diameter of the resist pattern can be made smaller. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 It is a figure which shows each process of the manufacturing method of the printed wiring board which concerns on 1st Embodiment of this invention.

[0052] Figure 2 Yes means Figure 1 Diagrams of subsequent steps.

[0053] Figure 3 Yes means Figure 2 Diagrams of subsequent steps. DETAILED DESCRIPTION

[0054] Hereinafter, a mode for carrying out the present invention (hereinafter referred to as “embodiment”) will be described in detail, but the present invention is not limited thereto and various modifications can be made without departing from the gist of the present invention.

[0055] [First embodiment]

[0056] Figures 1 to 3 1 is a diagram showing each step of a method for manufacturing a printed wiring board according to a first embodiment of the present invention. In this embodiment, a method for manufacturing a build-up multilayer printed wiring board is described. First, for example, Figure 1 As shown in (A), an insulating layer 14 and an electrolytic copper foil 15 are sequentially stacked on an inner layer substrate 13 having an inner layer circuit 12 formed on an insulating substrate 11 to form a multilayer board 16 (multilayer board forming step). Specifically, for example, it is formed as follows.

[0057] The inner substrate 13 can be manufactured by a conventionally known method. An example is given to illustrate the manufacturing process of the inner substrate 13. For example, a through hole (not shown) is first formed on the insulating substrate 11 composed of a resin substrate such as a glass epoxy system or a polyimide system, and electrolytic copper plating is performed on the upper and lower surfaces of the insulating substrate 11 and the inner peripheral surface of the through hole with chemical copper plating as the base. Next, an anti-etching pattern is formed on the surface, and a conductor pattern and a through-hole conductor are formed as the inner layer circuit 12 by etching, and a hole-filling resin such as epoxy is filled in the hollow part of the through-hole conductor for planarization.

[0058] Before laminating the insulating layer 14 and the electrolytic copper foil 15 on the inner layer substrate 13 , it is preferable that the surface of the inner layer substrate 13 , specifically, the surface of the inner layer circuit 12 is roughened by etching or the like, for example.

[0059] The multilayer board 16 can be formed, for example, as follows: an insulating prepreg or resin sheet is stacked on the inner substrate 13 as an insulating layer 14, and an electrolytic copper foil 15 is stacked thereon and crimped to form. As a prepreg, for example, a prepreg in which a thermosetting resin mixed with additives such as a curing agent and a coloring material is impregnated in a fibrous reinforcing material such as glass cloth or carbon fiber and made into a semi-cured state can be cited. As a resin sheet, for example, a resin sheet in which a thermosetting resin mixed with additives such as a curing agent and a coloring material is made into a semi-cured state can be cited. As a thermosetting resin used for a prepreg or a resin sheet, for example, polyimide resin, liquid crystal polyester, epoxy compound, cyanate compound, maleimide compound, phenol compound, polyphenylene ether compound, benzoxazine compound, organic group modified silicone compound and a compound having a polymerizable unsaturated group can be cited. The electrolytic copper foil 15 can be stacked, for example, by using an electrolytic copper foil with a carrier and stacking the electrolytic copper foil side as one side of the insulating layer 14, peeling off the carrier, and thus stacking.

[0060] In addition, the multilayer board 16 can also be formed, for example, as follows: a copper foil with a resin layer having an insulating resin layer formed on an electrolytic copper foil 15 is used, the resin layer is used as the insulating layer 14, the resin layer is abutted against the inner substrate 13 and laminated, and crimped to form. As the material constituting the resin layer, for example, the same material as the above-mentioned prepreg or resin sheet can be cited. Furthermore, the multilayer board 16 can also be formed, for example, as follows: after applying an insulating liquid resin such as an epoxy system on the inner substrate 13 by a spin coater or the like, it is thermally cured to form the insulating layer 14, and the electrolytic copper foil 15 is laminated thereon, and crimped to form.

[0061] The thickness of the insulating layer 14 is preferably, for example, 1 μm to 40 μm. The thickness of the electrolytic copper foil 15 is preferably, for example, 0.5 μm to 20 μm.

[0062] Then, for example Figure 1As shown in (B), the surface of the electrolytic copper foil 15 of the multilayer board 16 is roughened by etching or the like (electrolytic copper foil roughening step). For the roughening, for example, a micro-roughening etchant is preferably used.

[0063] Then, for example Figure 1 As shown in (C), a dry film resist is laminated on the electrolytic copper foil 15 to form a resist layer 17 (resist layer forming step). At this time, it is desirable that the lamination of the resist layer is set at 50°C to 140°C and the pressing pressure is set at 1 kgf / cm 2 ~15kgf / cm 2 The crimping time is set to 5 seconds to 300 seconds. Figure 1 (D) and Figure 1 As shown in (E), the resist layer 17 is sequentially exposed in such a manner that only the portion other than the via hole 14A to be formed in the subsequent process is left ( Figure 1 (D)) and development ( Figure 1 (E)), a resist pattern 17B is formed from a portion 17A for forming the via hole 14A (via hole forming portion) removed (resist pattern forming step).

[0064] Exposure refers to irradiating a predetermined portion of the anti-etching layer 17 with active energy rays to cure the irradiated portion. The irradiation with active energy rays may be performed through a mask pattern or by a direct drawing method in which active energy rays are directly irradiated. Examples of active energy rays include ultraviolet rays, visible rays, electron beams, and X-rays, and ultraviolet rays are particularly preferred. The exposure amount of ultraviolet rays is approximately 10 mJ / cm 2 ~1000mJ / cm 2 In addition, for example, by reducing the design value of the aperture of the resist pattern 17B, the opening diameter of the resist pattern 17B can be reduced.

[0065] There are no particular limitations on the development as long as the unexposed portion is dissolved out in a limited manner, and a developer such as an alkaline aqueous solution, an aqueous developer, or an organic solvent may be used. The development method may be, for example, spraying, shaking immersion, brushing, or scraping.

[0066] After forming the resist pattern 17B, for example, Figure 2 As shown in (F), it is preferred to remove scum (resist residue) by plasma cleaning (scum removal process). This is because in the resist pattern forming process, if the exposure conditions are adjusted in a manner to further reduce the opening diameter of the resist pattern 17B, in the subsequent process, when the electrolytic copper foil 15 is etched to form the via hole forming mask 18, the influence of the scum on the aperture deviation of the via hole forming mask 18 will become greater.

[0067] After removing the scum, e.g. Figure 2 As shown in (G), the electrolytic copper foil 15 is etched using the resist pattern 17B as a resist to form a mask 18 for forming a via hole (a mask forming step for forming a via hole). As an etching method, it can be carried out by a known method such as spraying, shaking and dipping. The etching solution preferably uses an etching solution containing sulfuric acid and hydrogen peroxide. This is because the etching rate of the etching solution using sulfuric acid and hydrogen peroxide is lower than that of the copper chloride aqueous solution, and the etching amount is small, so it is easily affected by the opening diameter of the resist pattern 17B, and the opening diameter of the mask 18 for forming a via hole can be reduced.

[0068] The etching solution for the electrolytic copper foil 15 preferably contains sulfuric acid and hydrogen peroxide as main active ingredients in water. For example, the content of sulfuric acid and hydrogen peroxide is preferably 0.1 w / v% (mass volume %) to 10 w / v% hydrogen peroxide and 0.5 w / v% to 9 w / v% sulfuric acid, more preferably 0.15 w / v% to 6.00 w / v% hydrogen peroxide and 0.75 w / v% to 8.50 w / v sulfuric acid, and further preferably 0.20 w / v% to 3.00 w / v% hydrogen peroxide and 1.00 w / v% to 8.00 w / v sulfuric acid. This is because a higher effect can be obtained within this range. The etching solution for the electrolytic copper foil 15 also preferably contains 0.1 w / v% to 5 w / v% alcohol as an auxiliary agent. This is because it also has the function of a stabilizer for hydrogen peroxide and a glossing agent for copper. As alcohol, for example, monohydric alcohols such as methanol, ethanol, propanol, and butanol, dihydric alcohols such as ethylene glycol, propylene glycol, butanediol, and pentanediol, or trihydric alcohols such as glycerol and pentaerythritol can be cited. One of these can be used, or two or more can be mixed and used. The etching solution for the electrolytic copper foil 15 can be prepared by a known method, or a commercial product can be used. As a commercial product of the etching solution for the electrolytic copper foil 15, for example, etching solutions manufactured by Mitsubishi Gas Chemical Co., Ltd. such as SE-07, CPE-770, CPE-770D, and CPE-800 can be cited.

[0069] The etching rate of the etching solution for the electrolytic copper foil 15 is preferably 0.5 to 20 μm·m / min, more preferably 0.6 to 17 μm·m / min, and further preferably 0.7 to 15 μm·m / min. This is because a higher effect can be obtained within this range.

[0070] In addition, the etching solution of the electrolytic copper foil 15 preferably contains azoles or their salts in addition to sulfuric acid and hydrogen peroxide. This is because it has the function of reducing the difference in width between the top and bottom of the opening of the mask 18 for forming the via hole by adsorbing on the surface of the electrolytic copper foil 15. As azoles, it is preferred to have a heterocyclic compound having a five-membered heterocyclic ring or a condensed heterocyclic ring having two nitrogen atoms. As azoles, for example, it is preferred to cite at least one selected from the group consisting of pyrazoles, imidazoles and benzimidazoles, and more specifically, it is preferred to cite at least one selected from the group consisting of compounds represented by the following general formula (1), (2) or (3). The content of azoles is preferably in the range of 0.01 to 0.5 mass % (100 to 5000 ppm) based on the total amount of the etching solution (mass basis), more preferably 0.05 to 0.4 mass % (500 to 4000 ppm), further preferably 0.1 to 0.3 mass % (1000 to 3000 ppm), and particularly preferably 0.15 to 0.25 mass % (1500 to 2500 ppm). By making the content of azoles within the above range, the difference in width between the top and bottom of the opening of the via hole forming mask 18 can be further reduced. It should be noted that when using a salt of an azole, the content of the azole is calculated by converting it into the content of the azole without the salt.

[0071] When two or more components are used, the total amount of the azoles contained therein may be within the above range.

[0072]

[0073] In the above general formula (1), (2) or (3), R 1 , R 2 , R 3 , R 4 , R 5 and R 6 Each independently is a hydrogen atom, C 1 ~C 6 Alkyl, C 6 ~C 10 Aryl, Carboxyl, Carboxyl C 1 ~C 6 Alkyl, nitro, hydroxyl, C 2 ~C 7 carboxylate or a halogen atom.

[0074] Furthermore, the etching solution of the electrolytic copper foil 15 preferably contains glycol ethers in addition to sulfuric acid and hydrogen peroxide. It can have the effect of making the amount of dissolution of the electrolytic copper foil 15 in the etching process uniform. Specifically, it can have the effect of making the etching speed and etching amount of the electrolytic copper foil 15 in the etching process uniform. Therefore, it can have the effect of making the opening shape of the mask 18 for via formation uniform. As glycol ethers, for example, at least one selected from the group consisting of ethylene glycol monobutyl ether, diethylene glycol monomethyl ether, diethylene glycol monophenyl ether and dipropylene glycol monomethyl ether can be listed. The content of glycol ethers is preferably in the range of 0.01 to 1 mass % (100 to 10000 ppm) based on the total amount of the etching solution (mass basis), more preferably 0.05 to 0.75 mass % (500 to 7500 ppm), and further preferably 0.1 to 0.5 mass % (1000 to 5000 ppm). By making the content within the above range, the etching speed and etching amount of the electrolytic copper foil 15 can be made more uniform. In addition, according to a preferred embodiment of the present invention, by making the content within the above range, it is not easily affected by physical conditions such as spray pressure during etching. When two or more components are used, their total amount can be within the above range.

[0075] In addition, the etching solution of the electrolytic copper foil 15 preferably contains halide ions in addition to sulfuric acid and hydrogen peroxide. This is because it has the effect of stabilizing the etching rate. As halide ions, chloride ions are preferred, for example. The content of halide ions is, for example, in the range of 0.01 to 3 ppm based on the total amount of the etching solution (mass basis), preferably in the range of 0.05 to 2 ppm, and more preferably in the range of 0.1 to 1 ppm. By making the content within the above range, the etching rate can be further stabilized. When using two or more halide ions, the total amount of their components can be within the above range.

[0076] After forming the via hole forming mask 18, for example, Figure 2 As shown in (H), the resist pattern 17B is removed (resist pattern removal step). After removing the resist pattern 17B, for example, Figure 2 As shown in (I), through CO 2 The portion of the insulating layer 14 not covered by the via hole forming mask 18 is removed by laser or the like to form the via hole 14A (via hole forming step). The laser processing of the via hole 14A is performed until the conductor pattern under the insulating layer 14 is exposed.

[0077] After forming the via hole 14A, for example, Figure 3 As shown in (J), the smear (resin residue) in the via hole 14A is removed (smear removal process). After the smear is removed, for example, Figure 3As shown in (K), via conductor 19 is formed in via hole 14A, and conductor pattern 20 is formed on insulating layer 14 (via conductor / conductor pattern forming step). Specifically, via conductor 19 and conductor pattern 20 are formed on via hole forming mask 18 and via hole 14A by chemical copper plating and hole-filling copper plating, for example.

[0078] Thereafter, when further lamination is performed, the above-mentioned steps from the multilayer board forming step to the via conductor / conductor pattern forming step are repeated to form multiple layers until the desired number of layers is reached.

[0079] Thus, according to the present embodiment, when the electrolytic copper foil 15 is etched to form the via hole forming mask 18, an etching solution containing sulfuric acid and hydrogen peroxide is used, so that the etching amount can be reduced. Therefore, the opening diameter of the via hole forming mask 18 can be reduced, which is easily affected by the opening diameter of the resist pattern 17B, and the aperture of the via hole 14A can be reduced.

[0080] Furthermore, since the scum is removed after the resist pattern 17B is formed, the opening diameter of the resist pattern 17B can be further reduced, and the opening diameter of the via hole forming mask 18 and the hole diameter of the via hole 14A can be further reduced.

[0081] [Second embodiment]

[0082] In the first embodiment, a descumming step is performed after forming the resist pattern 17B (see Figure 2 (F)), but when the resist layer 17 is exposed in the resist pattern forming process, for example, the design value of the aperture of the resist pattern 17B can be adjusted to set a condition that enables the resist pattern 17B to be stably opened, and the descumming process after forming the resist pattern 17B is deleted. The rest is the same as the first embodiment, so refer to Figures 1 to 3 , the same reference numerals are given to corresponding components, and detailed description of the same parts is omitted. In the second embodiment, similarly to the first embodiment, since an etching solution containing sulfuric acid and hydrogen peroxide is used when etching the electrolytic copper foil 15 in the via hole forming mask forming step, the opening diameter of the via hole forming mask 18 can be reduced, and the aperture of the via hole 14A can be reduced.

[0083] [Third embodiment]

[0084] In the via hole forming mask forming step of the first embodiment (see Figure 2In (G)), the electrolytic copper foil 15 is etched using an etching solution containing sulfuric acid and hydrogen peroxide, but other etching solutions may also be used. As other etching solutions, for example, there may be mentioned an etching solution containing hydrochloric acid and cupric chloride, a persulfate-based etching solution (an etching solution using a persulfate such as ammonium persulfate or sodium persulfate as an oxidant), or an organic acid-based etching solution (an etching solution containing an organic acid such as formic acid and a weak chelating agent). The rest is the same as the first embodiment, so refer to Figures 1 to 3 The same reference numerals are used for corresponding components, and detailed description of the same parts is omitted. In the third embodiment, similarly to the first embodiment, since a descumming process is performed after the resist pattern 17B is formed, the opening diameter of the resist pattern 17B can be further reduced.

[0085] Example

[0086] (Example 1)

[0087] The printed wiring board was produced as follows (see Figures 1 to 3 ).

[0088] [Multilayer board forming process] (refer to Figure 1 (A)

[0089] As the inner substrate 13, a glass cloth substrate BT resin copper-clad laminate (conductor thickness 12 μm, thickness 0.1 mm, manufactured by Mitsubishi Gas Chemical Co., Ltd., HL832 NS) was prepared, and the surface was roughened. Specifically, first, as a pretreatment, the inner substrate 13 was cleaned with a residue remover (CA5330, manufactured by MEC Co., Ltd.), and after water washing, the copper surface was roughened with a microetchant (CZ8101, manufactured by MEC Co., Ltd.), and after water washing, rust prevention was performed with a rust preventer (CL8300, manufactured by MEC Co., Ltd.), and then washed and dried. The etching amount based on the microetchant was set to 1 μm. A horizontal line spray device was used for roughening.

[0090] After the surface of the inner layer substrate 13 is roughened, a copper foil with a resin layer (CRS381NSI, manufactured by Mitsubishi Gas Chemical Co., Ltd.) prepared by coating a thermosetting resin on a 1.5 μm ultra-thin electrolytic copper foil with an 18 μm carrier copper foil is arranged on the inner layer substrate 13 (both the front and back sides). The laminated molding is performed at a pressure of 3.0 MPa and a temperature of 220°C for 60 minutes, and the carrier copper foil of the ultra-thin electrolytic copper foil with the carrier copper foil is peeled off to form a multilayer board 16 in which an insulating layer 14 and an electrolytic copper foil 15 are sequentially laminated on the inner layer substrate 13.

[0091] [Electrolytic copper foil roughening process] (refer to Figure 1 (B)

[0092] After the multilayer board 16 was produced, the surface of the electrolytic copper foil 15 was roughened with a micro-roughening etchant (EMR-2000, manufactured by Mitsubishi Gas Chemical Co., Ltd.) The roughening conditions were a temperature of 30° C. and a copper foil etching amount of 0.5 μm.

[0093] [Resist layer forming step] (refer to Figure 1 (C)

[0094] After roughening the multilayer board 16, a dry film resist (RY-5107, manufactured by Showa Denko Materials Co., Ltd., thickness 7 μm) was laminated on the electrolytic copper foil 15 to form a resist layer 17. Lamination was performed using an apparatus manufactured by ONC Co., Ltd. at a lamination pressure of 0.4 MPa and a lamination temperature of 110°C.

[0095] [Resist pattern forming step] (refer to Figure 1 (D)(E)

[0096] After the resist layer 17 is set, the resist layer 17 is exposed. The exposure machine uses INPREX3650 (manufactured by ADTEC Engineering Co., Ltd.), and the exposure is performed under the conditions of the design value of the resist pattern aperture 9μm and the exposure amount 250mJ. The design value of the resist pattern aperture at this time is adjusted so that when the descum process is performed after the resist pattern forming process, the opening diameter of the resist pattern 17B becomes the minimum processable diameter. After exposure, the unexposed part is dissolved by a developer to form a resist pattern 17B. The developer uses a 1% by mass sodium carbonate aqueous solution, and the development is performed under the conditions of a temperature of 30°C and a time of 30 seconds.

[0097] [Descum removal process] (refer to Figure 2 (F)

[0098] After the resist pattern 17B is formed, scum is removed by plasma cleaning. The plasma processing apparatus PCB1600E (manufactured by Nordson Advanced Technology Co., Ltd.) is used as an apparatus, and argon, nitrogen, oxygen, and tetrafluoromethane are used as a gas.

[0099] [Mask formation step for via hole formation] (refer to Figure 2 (G)

[0100] After removing the scum, the resist pattern 17B is used as a resist, and the electrolytic copper foil 15 of the multilayer board 16 is removed by an etching solution, and then washed and dried to form a mask 18 for forming a via hole. The etching solution used is CPE-770D (manufactured by Mitsubishi Gas Chemical Co., Ltd.), and copper etching is performed under the condition of a liquid temperature of 35°C. The device uses a horizontal line spray type device (manufactured by Tokyo Chemical Industry Co., Ltd.). The liquid composition of the etching solution CPE-770D includes water, hydrogen peroxide 2.1w / v%, and sulfuric acid 4w / v%.

[0101] [Resist pattern removal step] (refer to Figure 2 (H)

[0102] After forming the via hole forming mask 18, the resist pattern 17B is removed. The etching liquid used is R-100S (manufactured by Mitsubishi Gas Chemical Co., Ltd.), and the liquid temperature is set to 48° C. The apparatus used is a spray type apparatus (manufactured by Tokyo Kakoki Co., Ltd.).

[0103] [Conduction hole forming process] (refer to Figure 2 (I)

[0104] After removing the resist pattern 17B, the 2 The portion of the insulating layer 14 not covered by the via hole forming mask 18 is removed by laser to form the via hole 14A. The laser hole processing was performed using an apparatus of ML605GTW4(-P)5350U (manufactured by Mitsubishi Electric Corporation).

[0105] [Desmear process] (refer to Figure 3 (J)

[0106] After forming the via hole 14A, the multilayer board 16 is racked on the plating fixture, and the board is immersed and shaken in the swelling tank, etching tank, and neutralization tank to remove the smear. The device manufactured by ALMEX Technology Co., Ltd. is used for the immersion and shaking. The chemical solution uses the APPDES process (manufactured by Uemura Industry Co., Ltd.). APPDES MDS-37 is used as the swelling solution, a mixed solution of MDE-40 and ELC-SH is used as the etching solution, and APPDES MDN-62 is used for neutralization. The temperature of the etching tank is set to 80°C, and the immersion is performed for 10 minutes.

[0107] [Via conductor / conductor pattern forming process] (refer to Figure 3 (K)

[0108] After removing the smear, the multilayer board 16 is placed on the plating fixture, and chemical copper plating is performed using a device manufactured by ALMEX Technology Co., Ltd. that can be immersed and shaken in a chemical copper plating tank. The chemical solution used is a chemical solution obtained by mixing THRU-CUP PEA (manufactured by Uemura Industry Co., Ltd.) and formaldehyde. The chemical solution temperature for chemical copper plating is 36°C, and the treatment time is set to 10 minutes to form a chemical copper plating with a thickness of 0.4μm. Next, as a hole filling plating, an immersion-type device (manufactured by ALMEX Technology Co., Ltd.) is used, using a phosphorus-containing copper anode with a soluble anode, and a direct current of 1A / dm 2 Plating was performed to a thickness of 15 μm to form via conductors 19 and conductor patterns 20. The copper plating bath temperature was set at 22° C. and a leveling agent, brightener, and polymer additive of through-hole filling liquid CU-BRITE TF4 (manufactured by JCU Corporation) was used. A mixed solution of copper sulfate, sulfuric acid, and hydrochloric acid was used as the copper plating bath.

[0109] (Example 2)

[0110] The multilayer board forming process, the electrolytic copper foil roughening process and the resist layer forming process were performed in the same manner as in Example 1. Next, the resist pattern forming process was performed in the same manner as in Example 1 except that the exposure conditions were changed. The exposure conditions were the same as in Example 1 except that the design value of the resist pattern aperture was set to 11 μm, the exposure amount was set to 250 mJ, and the opening diameter of the resist pattern 17B was adjusted to the minimum processable diameter. Next, the descumming process was not performed, and the mask forming process for via hole formation, the resist pattern removal process, the via hole forming process, the descumming process, and the via conductor / conductor pattern forming process were performed in the same manner as in Example 1.

[0111] (Example 3)

[0112] The multilayer board forming step, the electrolytic copper foil roughening step, the resist layer forming step, the resist pattern forming step, and the descumming step were performed in the same manner as in Example 1. Next, the mask forming step for via hole formation was performed in the same manner as in Example 1 except that the etching solution was changed. The etching solution used was a hydrochloric acid and cupric chloride aqueous solution. Next, the resist pattern removal step, the via hole forming step, the descumming step, and the via conductor / conductor pattern forming step were performed in the same manner as in Example 1.

[0113] (Comparative Example 1)

[0114] The multilayer board forming process, the electrolytic copper foil roughening process and the anti-etching layer forming process are carried out in the same manner as in Example 1. Next, the exposure conditions are changed, and the anti-etching pattern forming process is carried out in the same manner as in Example 1 except that the design value of the anti-etching pattern aperture is set to 11μm, the exposure amount is set to 250mJ, and the opening diameter of the anti-etching pattern 17B is adjusted to the minimum processable diameter. The exposure conditions are the same as in Example 1 except that the descumming process is not carried out, the etching liquid is changed, and the mask forming process for via hole formation is carried out in the same manner as in Example 1. The etching liquid uses hydrochloric acid and cupric chloride aqueous solution. Next, the anti-etching pattern removal process, the via hole forming process, the descumming process and the via conductor / conductor pattern forming process are carried out in the same manner as in Example 1.

[0115] (Characteristics evaluation)

[0116] The properties of Examples 1 to 3 and Comparative Example 1 were measured by the following methods.

[0117] [Evaluation of Opening Diameter of Resist Pattern]

[0118] After the resist pattern 17B was formed, the opening diameter was observed by electron microscopy. VE-7800 (manufactured by KEYENCE Co., Ltd.) was used for observation, and the magnification was adjusted to 5000 times, and the average value and deviation of the opening diameter were obtained for 10 locations of the sample. The obtained results are shown in Table 1. The average value of the opening diameter of the resist pattern 17B was 6.8 μm in Example 1, 8.7 μm in Example 2, 6.8 μm in Example 3, and 8.7 μm in Comparative Example 1.

[0119] [Evaluation of the Opening Diameter of the Via-Hole Forming Mask]

[0120] After forming the via hole forming mask 18, the opening diameter was observed by electron microscope in the same manner as the evaluation of the opening diameter of the resist pattern. The obtained results are shown in Table 1. The average value of the opening diameter of the via hole forming mask 18 was 8.3 μm in Example 1, 11.4 μm in Example 2, 17.8 μm in Example 3, and 17.5 μm in Comparative Example 1. In addition, the deviation 3σ of the opening diameter of the via hole forming mask 18 was 1.8 in Example 1, 2.1 in Example 2, 1.2 in Example 3, and 5.1 in Comparative Example 1.

[0121] [Evaluation of via hole top diameter]

[0122] After forming the via hole 14A, the top diameter was observed by electron microscopy in the same manner as the evaluation of the opening diameter of the resist pattern. The obtained results are shown in Table 1. The average value of the top diameter of the via hole 14A was 16.8 μm in Example 1, 17.4 μm in Example 2, 21.4 μm in Example 3, and 21.7 μm in Comparative Example 1.

[0123] [Table 1]

[0124]

[0125] As shown in Table 1, in the via hole forming mask forming step, compared with Comparative Example 1 in which the etching solution was hydrochloric acid and cupric chloride aqueous solution, according to Examples 1 and 2 using etching solutions containing sulfuric acid and hydrogen peroxide as main active ingredients, the opening diameter and degree of deviation of the via hole forming mask can be reduced, and the top diameter of the via hole 14A can also be reduced. Furthermore, compared with Example 2 in which the descumming step was not performed, according to Example 1 in which the descumming step was performed after the resist pattern 17B was formed, the opening diameter and degree of deviation of the via hole forming mask can be further reduced, and the top diameter and degree of deviation of the via hole 14A can also be further reduced.

[0126] Furthermore, compared with Comparative Example 1 in which the descumming step was not performed, Example 3 in which the descumming step was performed after the resist pattern 17B was formed can reduce the opening diameter of the resist pattern and reduce the degree of variation in the opening diameter of the via hole forming mask.

[0127] Industrial Applicability

[0128] It can be used in the manufacture of printed wiring boards.

[0129] Description of Reference Numerals

[0130] 11... insulating substrate, 12... inner layer circuit, 13... inner layer substrate, 14... insulating layer, 14A... via hole, 15... electrolytic copper foil, 16... multilayer board, 17... resist layer, 17A... via hole forming portion, 17B... resist pattern, 18... via hole forming mask, 19... via conductor, 20... conductor pattern

Claims

1. A method for manufacturing a printed wiring board, characterized in that: include: A step of sequentially laminating an insulating layer and an electrolytic copper foil on an inner layer substrate having an inner layer circuit formed thereon to form a multilayer board; A process of providing an anti-etching layer on the electrolytic copper foil, exposing and developing the layer, and forming an anti-etching pattern from which a portion for forming a via hole is removed; After forming the resist pattern, the electrolytic copper foil is etched using an etching solution containing sulfuric acid and hydrogen peroxide using the resist pattern as a resist to form a mask for forming a via hole; After forming the via hole forming mask, removing the resist pattern; and A step of removing the resist pattern and then removing the portion of the insulating layer not covered by the via hole forming mask by laser to form a via hole.

2. The method for manufacturing a printed wiring board according to claim 1, wherein: The method includes a step of removing scum after forming the resist pattern and before forming the via hole forming mask.

3. The method for manufacturing a printed wiring board according to claim 1, wherein: The etching rate of the etching solution is 0.5 μm·m / min to 20 μm·m / min.

4. The method for manufacturing a printed wiring board according to claim 1, wherein: The etching solution contains 0.1 w / v% to 10 w / v% of hydrogen peroxide and 0.5 w / v% to 9 w / v% of sulfuric acid.

5. The method for manufacturing a printed wiring board according to claim 1, wherein: The etching solution contains 0.1 w / v% to 5 w / v% of alcohol.

6. The method for manufacturing a printed wiring board according to claim 1, wherein: The etching solution contains azoles or salts thereof.

7. The method for manufacturing a printed wiring board according to claim 6, wherein: The azoles are heterocyclic compounds having a five-membered heterocyclic ring or a condensed heterocyclic ring thereof having two nitrogen atoms.

8. The method for manufacturing a printed wiring board according to claim 7, wherein: The azole is at least one selected from the group consisting of pyrazoles, imidazoles and benzimidazoles.

9. The method for manufacturing a printed wiring board according to claim 8, wherein: The azole is at least one selected from the group consisting of compounds represented by the following general formula (1), (2) or (3), In the above general formula (1), (2) or (3), R 1 , R 2 , R 3 , R 4 , R 5 and R 6 are independently a hydrogen atom, a C1-C6 alkyl group, a C6-C 10 Aryl, carboxyl, carboxyl C1-C6 alkyl, nitro, hydroxyl, C2-C7 carboxylate or halogen atom.

10. The method for manufacturing a printed wiring board according to claim 1, wherein: The etching solution contains glycol ethers.

11. The method for manufacturing a printed wiring board according to claim 1, wherein: The etching solution contains halide ions.

12. The method for manufacturing a printed wiring board according to claim 11, wherein: The halide ions are chloride ions.

13. A method for manufacturing a printed wiring board, characterized in that: include: A step of sequentially laminating an insulating layer and an electrolytic copper foil on an inner layer substrate having an inner layer circuit formed thereon to form a multilayer board; A process of providing an anti-etching layer on the electrolytic copper foil, exposing and developing the layer, and forming an anti-etching pattern from which a portion for forming a via hole is removed; After forming the resist pattern, removing scum; After removing the scum, the electrolytic copper foil is etched using an etching solution using the resist pattern as a resist to form a mask for forming a via hole; After forming the via hole forming mask, removing the resist pattern; and A step of removing the resist pattern and then removing the portion of the insulating layer not covered by the mask by laser to form a via hole.

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