Method for detecting internal cavity defect of MOSFET

Abstract

The invention relates to the technical field of defect detection, and provides an MOSFET internal cavity defect detection method, which comprises the following steps: acquiring an X-ray image of an MOSFET; detecting a vertex position of a transistor in the X-ray image, and determining a transistor region based on the vertex position; dividing the transistor region into a plurality of partitions, calculating the similarity between the gray distribution of each partition and the fitting Gaussian distribution, judging whether the similarity is smaller than a preset similarity threshold value or not, and if yes, determining that the partition corresponding to the similarity contains a cavity defect; otherwise, based on pixel gray value calculation, searching the pixel with the maximum gray value in the partition corresponding to the similarity; judging whether the pixel with the maximum gray value is a void defect pixel or not, if yes, determining that the partition contains void defects, and if not, determining that the partition does not contain void defects; positioning the void defects of the partitions containing the void defects; the defect detection method is good in result accuracy and calculation robustness.

Description

Technical Field

[0001] The present invention relates to the technical field of defect detection, and more specifically, to a method for detecting internal void defects of MOSFET. Background Art

[0002] Internal void defects may be caused by a variety of factors such as material purity problems and process errors in the manufacturing process. These void defects will increase the resistance in the electronic channel, increase the leakage current, and shorten the device life, which in turn affects the performance and reliability of the device. Moreover, the higher the proportion of void defects, the worse the performance of the device and the shorter the life. Based on X-ray technology, the manual detection of voids is prone to missed detection and false detection. Therefore, for the design of electronic components such as MOSFET, the importance of automatic void defect detection algorithms is self-evident. Timely detection and resolution of internal void defects can improve the reliability and performance of the device and ensure its stable operation in various applications.

[0003] Unlike other electronic components, MOSFET is attached to the substrate by welding materials. To obtain the percentage of void defects, it is necessary to calculate the area of ​​transistors and void defects in turn, and finally obtain the percentage of void defects. The X-ray image of MOSFET has the problem of uneven grayscale distribution, and some void defects show weak edges, which makes it difficult for the global threshold or edge detection algorithm to accurately locate the void defects at the pixel level. If the deep learning method is used, a large number of manually labeled samples are required, which will greatly increase the cost. In addition, if new samples appear, the model needs to be retrained, which is time-consuming and labor-intensive.

[0004] In order to overcome the defects of the defect detection method based on deep learning, the prior art proposes a MOSFET etching defect detection method based on machine vision. The method is based on the grayscale image of the MOSFET etching defect. According to the grayscale information of the pixels in the eight neighborhoods around each pixel, the significant progressive trend of each pixel can be derived. Subsequently, by analyzing the pixel progressive trend in the neighborhood window of each pixel, it can be inferred whether the pixel is in the notch area, and the suspicion of its notch area can be calculated. Considering the suspicion of the notch area of ​​each pixel, the suspicion of the notch defect of each pixel is obtained. Furthermore, the severity of the MOSFET etching defect is evaluated according to the suspicion of the notch defect. Finally, combined with the preset defect threshold, the detection task of MOSFET etching defects is completed.

[0005] However, the method of the prior art detects etching defects of MOSFETs, and converts the defect detection problem into a pixel grayscale change trend analysis problem. However, the image of MOSFET may be interfered by noise, and the grayscale information derivation method will lead to unstable detection results. In addition, it is necessary to pre-set a defect threshold for separating the transistor area from the cavity defect, and the selection of the threshold is affected by human subjective factors, resulting in insufficient accuracy and robustness of defect detection. Summary of the invention

[0006] In order to overcome the defects of the above-mentioned prior art that a defect threshold needs to be set in advance, resulting in insufficient defect detection accuracy and robustness, the present invention provides a MOSFET internal void defect detection method capable of adaptively locating void defects.

[0007] In order to solve the above technical problems, the technical solution of the present invention is as follows:

[0008] Get an X-ray image of the MOSFET;

[0009] detecting a vertex position of a transistor in the X-ray image, and determining a transistor region based on the vertex position;

[0010] The transistor region is divided into a plurality of partitions, and for each partition, the similarity between the grayscale distribution of the partition and the fitted Gaussian distribution is calculated, and it is determined whether the similarity is less than a preset similarity threshold value. If so, the partition corresponding to the similarity is considered to contain a hole defect; otherwise, based on the pixel grayscale value calculation, the pixel with the largest grayscale value in the partition corresponding to the similarity is found; it is determined whether the pixel with the largest grayscale value is a hole defect pixel, and if so, the partition is considered to contain a hole defect, otherwise, the partition is considered not to contain a hole defect;

[0011] Locate the void defects in the partition containing the void defects.

[0012] The present invention also proposes a MOSFET internal void defect detection system for implementing the above-mentioned MOSFET internal void defect detection method, the system comprising:

[0013] An image acquisition module, which acquires an X-ray image of the MOSFET;

[0014] A vertex detection module, used to detect the vertex position of the transistor in the X-ray image, and determine the transistor area based on the vertex position;

[0015] A void defect partition detection module is used to divide the transistor area into a plurality of partitions, calculate the similarity between the partition grayscale distribution and the fitted Gaussian distribution for each partition, and determine whether the similarity is less than a preset similarity threshold. If so, the partition corresponding to the similarity is considered to contain a void defect; otherwise, based on the pixel grayscale value calculation, find the pixel with the largest grayscale value in the partition corresponding to the similarity; determine whether the pixel with the largest grayscale value is a void defect pixel. If so, the partition is considered to contain a void defect, otherwise, the partition is considered not to contain a void defect;

[0016] The void defect positioning module locates the void defects in the partition containing the void defects.

[0017] The present invention also proposes a computer device, including a memory and a processor, wherein the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the processor executes the steps of the above-mentioned MOSFET internal void defect detection method.

[0018] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0019] The present invention determines the transistor area based on the position of the transistor vertex, can accurately locate the vertex, and overcomes the disadvantages that the edge detection algorithm cannot identify the boundary of the transistor because it is a weak edge, or can identify it but incompletely; and divides the transistor area into a plurality of partitions, and preliminarily screens out the partitions with obvious hole defects through the characteristic that the grayscale distribution of the partition without hole defects is close to the fitted Gaussian distribution, and for the partitions with a large similarity between the grayscale distribution of the partition and the fitted Gaussian distribution, determines whether the partition has a hole defect by judging whether the pixel with the largest grayscale value in the partition is a hole defect pixel; overcomes the defect that the global threshold segmentation algorithm easily misjudges non-hole defect pixels as hole defect pixels; after determining the partition with hole defects, the hole defects are located for all partitions with hole defects, thereby improving the efficiency of hole defect detection and achieving a high pixel-level positioning accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of a first flow chart of the internal void defect detection method for MOSFET proposed in Example 1;

[0021] Figure 2 A second flow chart of the internal void defect detection method for MOSFET proposed in Example 2;

[0022] Figure 3 This is a schematic diagram of the vertex detection algorithm proposed in Example 2;

[0023] Figure 4 This is a schematic diagram of the partitioning and preprocessing process proposed in Example 2. DETAILED DESCRIPTION

[0024] The accompanying drawings are only used for illustrative purposes and should not be construed as limiting the present embodiment;

[0025] In order to better illustrate the present embodiment, some parts in the drawings may be omitted, enlarged or reduced, and do not represent the size of the actual product;

[0026] It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0027] The technical solution of the present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0028] Example 1

[0029] This embodiment provides a method for detecting internal void defects of MOSFET. Figure 1 A schematic diagram of a first flow chart of the internal void defect detection method for MOSFET of the present embodiment;

[0030] A method for detecting internal void defects of a MOSFET proposed in this embodiment includes the following steps:

[0031] S1: Acquire an X-ray image of MOSFET;

[0032] S2: Detecting the vertex position of the transistor in the X-ray image, and determining the transistor area based on the vertex position;

[0033] S3: Divide the transistor region into a plurality of partitions, calculate the similarity between the grayscale distribution of the partition and the fitted Gaussian distribution for each partition, and determine whether the similarity is less than a preset similarity threshold. If so, the partition corresponding to the similarity is considered to contain a hole defect; otherwise, based on the pixel grayscale value calculation, find the pixel with the largest grayscale value in the partition corresponding to the similarity; determine whether the pixel with the largest grayscale value is a hole defect pixel. If so, the partition is considered to contain a hole defect, otherwise, the partition is considered not to contain a hole defect;

[0034] S4: Positioning the void defects in the partition containing the void defects.

[0035] In the specific implementation process, the transistor area is determined based on the position of the transistor vertex, and the vertex can be accurately located, which overcomes the shortcomings of the edge detection algorithm that the boundary of the transistor cannot be recognized due to the weak edge, or the boundary can be recognized but incomplete; and the transistor area is divided into several partitions, and the partitions with obvious hole defects are preliminarily screened out through the characteristic that the grayscale distribution of the partition without hole defects tends to the fitted Gaussian distribution. For the partitions with a large similarity between the grayscale distribution of the partition and the fitted Gaussian distribution, it is determined whether the partition has a hole defect by judging whether the pixel with the largest grayscale value in the partition is a hole defect pixel; the defect that the global threshold segmentation algorithm easily misjudges non-hole defect pixels as hole defect pixels is overcome; after determining the partition with hole defects, the hole defects are located for all partitions with hole defects, so as to improve the efficiency of hole defect detection and achieve a high pixel-level positioning accuracy.

[0036] In an optional embodiment, the step of detecting the vertex position of the transistor in the X-ray image comprises:

[0037] The sliding window technique is used to find the vertex of the transistor from the X-ray image, and the rough positioning coordinates (x c1， y c1 ), the rough positioning coordinates of the lower left vertex (x c， y c2 ), upper right coarse positioning coordinate (x c3 ,y c3 ) and the lower right coarse positioning coordinate (x c4， y c4 );

[0038] The transistor vertex is roughly positioned at the coordinate (x ci ,y ci ) is the sliding window w centered on i Divided into two parts, one part is w 1i , and the other part is w 2i , where i = 1, 2, 3, 4. When i = 1, w 1i is the sliding window w i The lower right 1 / 4 part, when i = 2, w 1i is the sliding window w i The upper right 1 / 4 part, when i = 3, w 1i is the sliding window w i The lower left 1 / 4 part, when i = 4, w 1i is the sliding window w i The upper left 1 / 4 part;

[0039] Based on w 1i 、w 2i The coordinates (x ci,y ci ) is iteratively optimized to obtain the vertex position coordinates (x vi ,y vi ), where i = 1, 2, 3, 4. When i = 1, (x vi ,y vi ) represents the coordinates of the upper left vertex of the transistor. When i=2, (x vi ,y vi ) represents the coordinates of the lower left vertex of the transistor. When i=3, (x vi ,y vi ) represents the coordinates of the upper right vertex of the transistor. When i=4, (x vi ,y vi ) represents the coordinates of the lower right vertex position of the transistor;

[0040] The vertex position coordinates (x vi ,y vi ) include:

[0041] (x vi ,y vi ) = argminJ(x ci ,y ci )

[0042]

[0043] In the formula, and Respectively represent w 1i 、w 2i and w i The variance of and Respectively represent w 1i and w 2i The mean of , α represents the balance coefficient;

[0044] The vertex position coordinates of the transistor (x vi ,y vi ) is the transistor area.

[0045] As an example, the vertex position coordinates (x ci ,y vi ) is subject to constraints, the expressions of which include:

[0046]

[0047] Where N I Indicates the width of the X-ray image, N w represents the sliding window w i The width of the window.

[0048] In an optional embodiment, before dividing the transistor region into a plurality of partitions, the image in the transistor region is preprocessed by mean filtering and adaptive histogram equalization to obtain a preprocessed transistor region image;

[0049] Based on the preprocessed transistor area image, the transistor area is divided into a plurality of partitions based on grayscale values ​​using linear space transformation, wherein the difference between the minimum grayscale value and the maximum grayscale value of pixels in the same partition does not exceed a preset difference.

[0050] In an optional embodiment, the calculation expression for calculating the similarity between the grayscale distribution of each partition and the fitted Gaussian distribution includes:

[0051] G Coarse (P 1 ) = k co ×D KL (R P ||Q P )+b co

[0052]

[0053] Where P 1 Represents any partition, G Coarse (P 1 ) represents partition P 1 Similarity to the fitted Gaussian distribution, R P Represents partition P 1 Grayscale distribution, Q P Represents the grayscale distribution R P The maximum likelihood fitting distribution of is, ρ represents the proportional coefficient, τ represents the smoothing factor, and p Hf Represents partition P 1 The gray value corresponding to the maximum gray frequency, μ represents the partition P 1 The grayscale mean of , |·| represents the absolute value operation.

[0054] In an optional embodiment, when determining whether the pixel with the largest grayscale value is a hole defect pixel, the maximum grayscale difference G between two adjacent pixel value neighborhoods corresponding to the pixel with the largest grayscale value is calculated. Fine (P 2 ), if the grayscale difference maximum value G Fine (P 2 ) exceeds a preset grayscale difference threshold, the pixel with the largest grayscale value is regarded as a hole defect pixel, otherwise, there is no hole defect in the partition corresponding to the pixel with the largest grayscale value;

[0055] Assume that the size of the first pixel value neighborhood of the two adjacent pixel value neighborhoods corresponding to the pixel with the largest grayscale value is (N×l+1)×(N×l+1), and the size of the second pixel value neighborhood is ((N-1)×l+1)×((N-1)×l+1), then the maximum grayscale difference G Fine (P 2 ) include:

[0056]

[0057] Δ(D P (N))=D P (N)-D P (N-1)

[0058]

[0059] m=[M P (N), -M P (N-1)] T

[0060] n=[(N×l+1) 2 , ((N-1)×l+1) 2 ] T

[0061] Where P 2 Indicates the partition where the pixel with the largest gray value is located, G Fine (P 2 ) represents partition P 2 The maximum grayscale difference value within, N represents the neighborhood expansion coefficient, l represents the step length of neighborhood expansion, N d represents the maximum neighborhood expansion coefficient, |·| represents the absolute value operation, T represents the transposition sign, M P (N) represents the mean function of the first pixel value neighborhood, M P (N-1) represents the mean function of the second pixel value neighborhood.

[0062] In an optional embodiment, after locating the void defect in the partition containing the void defect, a void defect pixel level positioning map P is obtained. seg (x, y), the positioning map P seg Expressions for (x, y) include:

[0063]

[0064] (u opt , v opt ) = arg minθ(u, V)

[0065] st(k ref -δ)≤u,v≤(kref +δ)

[0066]

[0067] stk peak <k<L

[0068] k peak = arg max F(k)

[0069]

[0070] Wherein, P represents the partition where the hole defect pixel is located, P n represents the pixel-by-pixel neighborhood mean of partition P, P(x, y) and P n (x, y) represent P and P respectively n The gray value at coordinate (x, y), u opt The horizontal coordinate of the segmentation threshold coordinate of partition P, v opt represents the ordinate of the segmentation threshold coordinate of partition P, u represents the abscissa of the boundary threshold coordinate of partition P, v represents the ordinate of the boundary threshold coordinate of partition P, δ represents the size of the traversal window, represents a set of positive integers, L represents the maximum grayscale value that can be obtained in the partition, f(i, j) represents the joint probability density distribution of the partition P, i and j both represent random variables of f(i, j), λ represents the stop condition of the search, and γ represents the correction factor; G r represents the preset grayscale value; θ(u, v) represents the void defect threshold discrimination vector.

[0071] As an example, G r The larger the value of seg In order to highlight the void defect as much as possible, this optional embodiment selects the maximum gray value of 255 as G r The value of .

[0072] In an optional embodiment, the expression of the void defect threshold discrimination vector θ(u, v) includes:

[0073]

[0074] In the formula, AMD intra (u, v) represents the intra-class aggregation coefficient of the void defect and transistor region class pixels, AMD intra The smaller (u, v) is, the better the intra-class aggregation of void defects and transistor area pixels is; AMD inter (u, v) represents the inter-class difference coefficient between the void defect and the transistor region class pixel, AMD interThe larger (u, v) is, the greater the difference between the void defect and the transistor area pixel; ω void (u, v) represents the weight of the void defect area, ω tran (u, v) represents the weight of the transistor region, and |·| represents an absolute value operation.

[0075] In an optional embodiment, the intra-class aggregation coefficient AMD of the void defect and transistor region class pixels is intra (u, v) and inter-class difference coefficient AMD inter The expressions for (u, v) include:

[0076] AMD intra (u, v) = ω tran (u,v)×d tran (u,v)+ω void (u,v)×d void (u, v)

[0077]

[0078] In the formula, AMD intra The smaller (u, v) is, the better the intra-class aggregation of void defects and transistor area pixels is; AMD inter The larger (u, v) is, the greater the difference between the void defect and the transistor area pixel; d tran (u, v) represents the average absolute value difference of the class of pixels in the transistor area; d void (u, v) represents the average absolute value difference of the pixels in the hole defect area class; μ(u, v) 1 and μ(u,v) 2 Represent the first and second elements of μ(u, v) respectively.

[0079] Example 2

[0080] This embodiment is based on the internal void defect detection method of MOSFET proposed in Embodiment 1, and proposes the following specific implementation examples:

[0081] Figure 2 FIG. 1 is a schematic diagram of a second flow chart of the method for detecting internal void defects of MOSFET of the present embodiment. Figure 2As shown, the method mainly includes three stages: transistor area detection, void defect detection, and void defect ratio calculation. In the transistor area detection stage, a custom position sensing algorithm is used to obtain the vertex position of the transistor and the area of ​​the transistor area. In the void defect detection stage, a custom coarse-fine patch-level void defect discrimination framework is used to screen out the void defect-containing patch, and the void defect is located at the pixel level for the void defect-containing patch. In the void defect ratio calculation stage, the void defect ratio is calculated using the obtained areas of the transistor and void defect areas to achieve void defect detection of MOSFET.

[0082] The steps for transistor area detection are as follows:

[0083] Since the boundary of the transistor area is a weak edge and its grayscale gradient is not obvious, if the edge detection algorithm is used, it is easy to find the problem of not being able to find a suitable boundary, and the internal void defects are easy to cause interference, resulting in incomplete edge extraction. Therefore, we proposed a vertex positioning algorithm based on position perception, constructed an optimization function through the data features of the window, and obtained the vertices of the transistor area through iterative optimization. Then, the obtained vertices are connected in sequence to calculate the area of ​​the transistor area.

[0084] The steps for void defect detection are as follows:

[0085] Partitioning and preprocessing: Since the MOSFET image has noise interference, the image is first mean filtered to complete the preliminary denoising. In order to solve the problem of weak contrast between some defects and the background, the image is adaptively histogram equalized. In order to solve the problem of uneven grayscale distribution in the transistor area, the transistor area is divided into several different patches. Finally, each patch is linearly transformed to further enhance the contrast.

[0086] Rough discrimination: For the divided patches, a patch-level discrimination algorithm for void defects is used to screen out patches containing void defects. The grayscale distribution of each patch is fitted, and the similarity between the fitted distribution and the original distribution is evaluated. Finally, the proposed discriminant function combining weights and bias terms is used to determine whether the patch contains void defects.

[0087] Fine discrimination: Since tiny void defects do not have much impact on the grayscale distribution within the patch, patches containing only a small number of tiny void defects are easily misjudged as patches without void defects by the coarse discrimination module. Therefore, we propose a fine discrimination module to perform secondary discrimination on the patch. This method uses a set function to evaluate the difference in grayscale distribution of different neighborhoods, thereby determining whether there are tiny void defects in a patch.

[0088] Since the MOSFET image itself has noise interference and noise is introduced in the adaptive histogram equalization stage, the common threshold algorithm relies too much on grayscale features and fails to fully exploit the grayscale distribution information, which easily causes pixel-level discrimination errors. In order to reduce the detection time and make full use of the grayscale distribution information, we propose an adaptive threshold algorithm to locate the void defect at the pixel level. The algorithm first narrows the optional threshold range, and finally uses the proposed threshold decision function to determine the segmentation threshold to complete the pixel-level positioning of the void defect.

[0089] The steps for calculating the void defect ratio are as follows:

[0090] After obtaining the transistor and void defect area areas through the above steps, the void defect ratio can be calculated to complete the final MOSFET void defect detection.

[0091] Specifically, the shape of the MOSFET transistor part is similar to a quadrilateral, so the area of ​​the part can be obtained by locating the vertices of the transistor area. We propose a vertex detection algorithm based on position awareness, and now take solving the upper left vertex of the transistor area as an example to summarize the algorithm.

[0092] Let the coordinates of the point be (x c ,y c ), Figure 3 This is a schematic diagram of the vertex detection algorithm proposed in this embodiment.

[0093] like Figure 3 As shown, (x c ,y c ) is some distance from the vertex, let (x c ,y c ) is the lower right 1 / 4 (dashed box) of the window w centered at 1 , the other part is w 2 When (x c ,y c ) is a vertex, w 1 The gray value of w is low. 2 The grayscale value is high, and the grayscale difference in each part is not large. c ,y c ) to perform iterative optimization and find the coordinates of the vertex. The vertex coordinates (x v ,y v )for:

[0094] (x v ,y v )=arg minJ(x c ,y c )

[0095]

[0096] Where N I Indicates the width and height of the image, N w Represents the width and height of the window. Based on the vertex neighborhood window grayscale features described above, the function J(x c ,y c ) can be expressed as:

[0097]

[0098] in and Respectively represent w 1 , w 2 and the variance of w, and Respectively represent w 1 and w 2 is the mean of , and α is the balance coefficient.

[0099] The other three vertices can be located in the same way. After all vertices are located, the transistor area can be detected and its area can be calculated.

[0100] In order to facilitate the subsequent void defect detection, the detected transistor area is first partitioned and preprocessed. Figure 4 This is a schematic diagram of the partitioning and preprocessing process proposed in this embodiment.

[0101] like Figure 4 As shown in the figure, since the X-ray image of MOSFET is interfered by noise, mean filtering is first performed to suppress the noise and smooth the image. In order to enhance the contrast of the void defect, the image is processed using the contrast-limited adaptive histogram equalization algorithm (CLAHE). Since the grayscale of the transistor area is uneven, it is not conducive to the subsequent void defect detection, so the transistor area is divided into several different patches. Finally, the divided patches are subjected to linear space transformation to further enhance the contrast.

[0102] In order to filter out patches containing void defects, we proposed a coarse-fine patch-level void defect discrimination framework. First, the coarse discrimination module completes the preliminary discrimination, but patches containing only small void defects are easily misjudged as patches without void defects. Therefore, for patches judged as void-free by the coarse discrimination module, the fine discrimination module is used for secondary discrimination.

[0103] Since the grayscale distribution of the patch without hole defects is close to Gaussian distribution, the distribution R of each image patch (P) PPerform maximum likelihood estimation, calculate the mean and standard deviation within P, perform distribution fitting, obtain the fitting distribution QP, and convert R P KL divergence is calculated with QP to measure the similarity of the two distributions. The formula is:

[0104]

[0105] The smaller the value of KL divergence, the closer Rp is to Gaussian distribution, and the more likely P is to have no void defects. However, if P has a large area of ​​void defects, KL divergence is prone to offset effect, and its value will be relatively low. Therefore, the discriminant function of the coarse discrimination module is defined as:

[0106] G coarse (P) = k co ×D KL (R P ||Q P )+b co

[0107]

[0108] where p Hf is the gray value corresponding to the maximum gray frequency of P, p max is the maximum grayscale value of the pixel of P, μ is the grayscale mean of P, and L is the upper limit of the grayscale value, that is, 255. The discriminant function value is obtained. If the discriminant function value is greater than or equal to the preset threshold, it is judged as a patch containing a void defect, otherwise it is judged as a patch without a void defect, specifically:

[0109]

[0110] After the patch-level coarse discrimination of void defects, the patches containing void defects have been preliminarily screened. However, for patches containing only tiny void defects, the coarse discrimination module can easily misjudge them as patches without void defects, resulting in precision loss. Therefore, we propose a patch-level fine discrimination algorithm for void defects to perform secondary discrimination on patches that have been judged as free of void defects by the coarse discrimination module.

[0111] If P contains a hole defect, then the pixel with the maximum grayscale is likely to be a hole defect pixel. Let (N×l+1)×(N×l+1) be the size of the pixel value neighborhood, and the mean function of the neighborhood is M P (N), where N is the expansion factor of the neighborhood and l is the step size of the expansion. In order to measure the grayscale difference between two adjacent neighborhoods, the weighted difference function can be defined as:

[0112]

[0113] m=[MP (N), -M P (N-1)] T

[0114] n=[(N×l+1) 2 , ((N-1)×l+1) 2 ] T

[0115] Where T represents transpose, D P The difference function of (N) can be expressed as:

[0116] Δ(D P (N))=D P (N)-D P (N-1)

[0117] Afterwards, the discriminant function of the fine discriminant module is defined as:

[0118]

[0119] Where |·| represents absolute value calculation, Nd represents the maximum expansion coefficient, and if the discriminant function value is greater than or equal to the set threshold, it is judged as a patch containing void defects, otherwise it is judged as a patch without void defects. Specifically:

[0120]

[0121] Among them fi Represents the threshold of the fine discrimination module.

[0122] After the coarse-fine patch-level void defect discrimination module, the void defect patches are obtained. The void defects of these patches are now located at the pixel level. The traditional adaptive threshold algorithm fails to fully exploit the grayscale distribution and takes a long time to traverse. Therefore, we propose an adaptive threshold algorithm to complete the pixel-level positioning of void defects.

[0123] First, solve the pixel-by-pixel neighborhood mean of the image block P to be detected and get P n , then the joint probability density distribution f(i, j) can be solved. The pixels of P are concentrated on the diagonal of the probability distribution graph, and the rest are mainly noise and edges. The weights of the void defect and the transistor area can be expressed as:

[0124]

[0125] Where (u, v) is the threshold of the patch to be segmented, and the specific value needs to be solved in an adaptive way. In general, the ratio of noise to edge is small, so it can be considered that ω void (u,V)+ω tran(u, v) approaches 1. After obtaining the ratio of void defects and transistor areas to the total pixel ratio, the mean vectors of the two categories can be calculated respectively:

[0126]

[0127] The overall mean vector in the region is:

[0128]

[0129] In order to fully consider the aggregation of void defects and transistor-type pixels in threshold segmentation, it is necessary to reduce the intra-class absolute difference between pixels of the same type. The intra-class average absolute value difference of void defects and transistor-type pixels can be expressed as:

[0130]

[0131] According to the obtained weights of void defects and transistor-type pixels, the overall intra-class average absolute value difference can be calculated as:

[0132] AMD intra (u, v) = ω tran (u,v)×d tran (u,v)+ω void (u,v)×d void (u, v)

[0133] AMD intra The smaller (u, v) is, the better the intra-class aggregation of the void defects and transistor area class pixels is.

[0134] In order to distinguish between void defects and transistor-like pixels, the method of solving the mean absolute difference between classes is adopted:

[0135]

[0136] When AMD inter The larger the (u, v) is, the greater the difference between the void defect and the transistor area pixel.

[0137] In order to fully consider the intra-class aggregation and inter-class differences of the void defects and transistor area pixels, and to ensure that the sum of the two parts is close to 1, the threshold discriminant vector is set to:

[0138]

[0139] In order to reduce the range of (u, V) traversal and thus reduce processing time, we propose a solution to reduce the optional threshold. First, find the center of the maximum value of the cumulative frequency of the interval within f(i, j), specifically:

[0140] kpeak=argmaxF(k)

[0141]

[0142] Where δ is the size of the window. After solving kpeak, it can be used for subsequent optimization by solving the reference point. The reference point can be expressed as:

[0143]

[0144] stk peak <k<L

[0145] Where λ represents the stop condition of the search and γ represents the correction factor. Afterwards, the optimal threshold can be calculated based on the reference point k ref In the interval, the segmentation threshold (u opt , v opt ), specifically:

[0146] (u opt , v opt ) = arg minθ(u, v)

[0147] st(k ref -δ)≤u,v≤(k ref +δ)

[0148] Through the calculation of the threshold, the final pixel-level localization map of the hole defect can be expressed as:

[0149]

[0150] Where P(x, y) and P n (x, y) represent P and P respectively n Grayscale value at (x, y).

[0151] After detecting the transistor area and the void defect area, the void defect ratio can be calculated as follows:

[0152]

[0153] Where S void and S tran represent the areas of transistor region and void defect region respectively.

[0154] This application proposes for the first time an integrated algorithm framework for calculating the void defect ratio inside MOSFET, which is divided into three stages: transistor area detection, void defect detection, and void defect ratio calculation. First, the four vertices of the transistor area are obtained through the vertex detection algorithm to detect the transistor area. Then, the transistor area is divided into different patches, and the patches containing void defects are screened out through the coarse-fine patch-level void defect discrimination framework. Finally, the void defects are located at the pixel level and the void defect ratio is calculated.

[0155] The present application utilizes the neighborhood grayscale features of the MOSFET transistor vertices, designs an optimization function, locates the vertices of the transistor region through iterative optimization, and completes the detection of the transistor region.

[0156] This application also proposes a coarse-fine patch-level void defect discrimination framework. For the coarse / fine discrimination modules, discrimination functions are defined respectively to screen out patches containing void defects for subsequent pixel-level positioning of void defects.

[0157] This application also proposes an adaptive threshold algorithm to locate the void defect at the pixel level, using the interval cumulative frequency to narrow the threshold range, reduce the processing time, and fully exploit the grayscale features to complete accurate pixel-level positioning.

[0158] The MOSFET void defect detection framework proposed in this application avoids the problem that deep learning algorithms require a large amount of manual pixel-level annotation and lengthy training time, greatly reducing the development cost of void defect detection algorithms.

[0159] In summary, in order to improve the detection accuracy, we proposed a vertex detection algorithm based on position perception to locate the vertices of the transistor area, so as to determine the area of ​​the area. First, we proposed an optimization function to obtain the position of the vertices of the transistor area through iterative optimization. Since the grayscale distribution of the transistor area in the X-ray image of MOSFET is uneven, it is difficult for the global threshold algorithm to find a suitable threshold for pixel-level positioning of void defects. We divide the transistor area into patches and screen out the patches containing void defects through the coarse-to-fine void defect discrimination module. Since the traditional threshold algorithm is overly dependent on grayscale features, we proposed an adaptive threshold segmentation algorithm for the patches containing void defects to locate the void defects at the pixel level. Finally, the area of ​​the obtained transistor area and the void defect area is used to calculate the void defect ratio.

[0160] Example 3

[0161] This embodiment provides a MOSFET internal void defect detection system, which is used to implement a MOSFET internal void defect detection method provided in Embodiment 1.

[0162] The internal void defect detection system of the MOSFET comprises:

[0163] An image acquisition module, which acquires an X-ray image of the MOSFET;

[0164] A vertex detection module, used to detect the vertex position of the transistor in the X-ray image, and determine the transistor area based on the vertex position;

[0165] A void defect partition detection module is used to divide the transistor area into a plurality of partitions, calculate the similarity between the partition grayscale distribution and the fitted Gaussian distribution for each partition, and determine whether the similarity is less than a preset similarity threshold. If so, the partition corresponding to the similarity is considered to contain a void defect; otherwise, based on the pixel grayscale value calculation, find the pixel with the largest grayscale value in the partition corresponding to the similarity; determine whether the pixel with the largest grayscale value is a void defect pixel. If so, the partition is considered to contain a void defect, otherwise, the partition is considered not to contain a void defect;

[0166] The void defect positioning module locates the void defects in the partition containing the void defects.

[0167] This embodiment provides a computer device, including a memory and a processor, wherein the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the processor executes the steps of the internal void defect detection method of the MOSFET described in Example 1.

[0168] It can be understood that the internal void defect detection system and computer equipment of the MOSFET of this embodiment improve the method of Example 1. The options in the above-mentioned Example 1 are also applicable to this embodiment, so they will not be repeated here.

[0169] The same or similar reference numerals correspond to the same or similar components;

[0170] The terms used to describe the positional relationship in the drawings are only used for illustrative purposes and should not be construed as limiting the present embodiment;

[0171] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A method for detecting internal void defects of MOSFET, characterized in that: The following steps are involved: Get an X-ray image of the MOSFET; detecting a vertex position of a transistor in the X-ray image, and determining a transistor region based on the vertex position; The transistor region is divided into a plurality of partitions, and for each partition, the similarity between the grayscale distribution of the partition and the fitted Gaussian distribution is calculated, and it is determined whether the similarity is less than a preset similarity threshold value. If so, the partition corresponding to the similarity is considered to contain a hole defect; otherwise, based on the pixel grayscale value calculation, the pixel with the largest grayscale value in the partition corresponding to the similarity is found; it is determined whether the pixel with the largest grayscale value is a hole defect pixel, and if so, the partition is considered to contain a hole defect, otherwise, the partition is considered not to contain a hole defect; Locate the void defects in the partition containing the void defects.

2. The method for detecting internal void defects of MOSFET according to claim 1, characterized in that: The step of detecting the vertex position of the transistor in the X-ray image comprises: The sliding window technique is used to find the vertex of the transistor from the X-ray image, and the rough positioning coordinates (x c1 ,y c1 ), the rough positioning coordinates of the lower left vertex (x c2 ,y c2 ), upper right coarse positioning coordinate (x c3 ,y c3 ) and the lower right coarse positioning coordinate (x c4 ,y c4 ); The transistor vertex is roughly positioned at the coordinate (x ci ,y ci ) is the sliding window w centered on i Divided into two parts, one part is w 1i , and the other part is w 2i , where i = 1, 2, 3, 4. When i = 1, w 1i is the sliding window w i The lower right 1 / 4 part, when i = 2, w 1i is the sliding window w i The upper right 1 / 4 part, when i = 3, w 1i is the sliding window w i The lower left 1 / 4 part, when i = 4, w 1i is the sliding window w i The upper left 1 / 4 part; Based on w 1i 、w 2i The coordinates (x ci ,y ci ) is iteratively optimized to obtain the vertex position coordinates (x vi ,y vi ), where i = 1, 2, 3, 4. When i = 1, (x vi ,y vi ) represents the coordinates of the upper left vertex of the transistor. When i=2, (x vi ,y vi ) represents the coordinates of the lower left vertex of the transistor. When i=3, (x vi ,y vi ) represents the coordinates of the upper right vertex of the transistor. When i=4, (x vi ,y vi ) represents the coordinates of the lower right vertex position of the transistor; The vertex position coordinates (x vi ,y vi ) include: (x vi ,y vi )=arg min J(x ci ,y ci ) In the formula, and Respectively represent w 1i 、w 2i and w i The variance of and Respectively represent w 1i and w 2i The mean of , α represents the balance coefficient; The vertex position coordinates of the transistor (x vi ,y vi ) is the transistor area.

3. The method for detecting internal void defects of MOSFET according to claim 1, characterized in that: Before dividing the transistor region into a plurality of partitions, preprocessing the image in the transistor region by means of mean filtering and adaptive histogram equalization to obtain a preprocessed transistor region image; Based on the preprocessed transistor area image, the transistor area is divided into a plurality of partitions based on grayscale values ​​using linear space transformation, wherein the difference between the minimum grayscale value and the maximum grayscale value of pixels in the same partition does not exceed a preset difference.

4. The method for detecting internal void defects of MOSFET according to claim 1, characterized in that: For each partition, the calculation expression for calculating the similarity between the partition grayscale distribution and the fitted Gaussian distribution includes: G Coarse (P1)=k co ×D KL (R P ||Q P )+b co In the formula, P1 represents any partition, G Coarse (P1) represents the similarity between partition P1 and the fitted Gaussian distribution, R P represents the grayscale distribution of partition P1, Q P Represents the grayscale distribution R P The maximum likelihood fitting distribution of is, ρ represents the proportional coefficient, τ represents the smoothing factor, and p Hf represents the gray value corresponding to the maximum gray frequency value of partition P1, μ represents the gray mean of partition P1, and |·| represents the absolute value operation.

5. The method for detecting internal void defects of MOSFET according to claim 1, characterized in that: When determining whether the pixel with the largest grayscale value is a hole defect pixel, the maximum grayscale difference G between the two adjacent pixel value neighborhoods corresponding to the pixel with the largest grayscale value is calculated. Fine (P2), if the maximum grayscale difference G Fine (P2) if the grayscale difference exceeds a preset threshold, the pixel with the largest grayscale value is regarded as a hole defect pixel; otherwise, the partition corresponding to the pixel with the largest grayscale value does not contain a hole defect; Assume that the size of the first pixel value neighborhood of the two adjacent pixel value neighborhoods corresponding to the pixel with the largest grayscale value is (N×l+1)×(N×l+1), and the size of the second pixel value neighborhood is ((N-1)×l+1)×((N-1)×l+1), then the maximum grayscale difference G Fine The expressions for (P2) include: Δ(D P (N))=D P (N)-D P (N-1) m=[M P (N),-M P (N-1)] T n=[(N×l+1) 2 ,((N-1)×l+1) 2 ] T Where P2 represents the partition where the pixel with the largest gray value is located, G Fine (P2) represents the maximum grayscale difference value in partition P2, N represents the neighborhood expansion coefficient, l represents the step length of neighborhood expansion, N d represents the maximum neighborhood expansion coefficient, |·| represents the absolute value operation, T represents the transposition sign, M P (N) represents the mean function of the first pixel value neighborhood, M P (N-1) represents the mean function of the second pixel value neighborhood.

6. The method for detecting internal void defects of MOSFET according to any one of claims 1 to 5, characterized in that: After locating the void defects in the partition containing void defects, the void defect pixel-level positioning map p is obtained. seg (x, y), the positioning map P seg Expressions for (x,y) include: (he opt ,v opt )=arg min θ(u,v) st(k ref -δ)≤u,v≤(k ref +d) s.t.k peak <k<L k peak =arg max F(k) Wherein, P represents the partition where the hole defect pixel is located, P n represents the pixel-by-pixel neighborhood mean of partition P, P(x,y) and P n (x,y) represent P and P respectively n The gray value at coordinate (x, y), u opt The horizontal coordinate of the segmentation threshold coordinate of partition P, v opt represents the ordinate of the segmentation threshold coordinate of partition P, u represents the abscissa of the boundary threshold coordinate of partition P, v represents the ordinate of the boundary threshold coordinate of partition P, δ represents the size of the traversal window, represents a set of positive integers, L represents the maximum grayscale value that can be obtained in the partition, f(i,j) represents the joint probability density distribution of the partition P, i and j both represent random variables of f(i,j), λ represents the stop condition of the search, and γ represents the correction factor; G r represents the preset grayscale value; θ(u,v) represents the void defect threshold discrimination vector.

7. The method for detecting internal void defects of MOSFET according to claim 6, characterized in that: The expression of the void defect threshold discrimination vector θ(u,v) includes: In the formula, AMD intra (u,v) represents the intra-class aggregation coefficient of the void defect and transistor region class pixels, AMD intra The smaller (u,v) is, the better the intra-class aggregation of void defects and transistor area pixels is; AMD inter (u,v) represents the inter-class difference coefficient between the void defect and the transistor region class pixel, AMD inter The larger (u,v) is, the greater the difference between the void defect and the transistor area pixel; ω void (u,v) represents the weight of the void defect area, ω tran (u,v) represents the weight of the transistor region, and |·| represents the absolute value operation.

8. The method for detecting internal void defects of MOSFET according to claim 7, characterized in that: The intra-class aggregation coefficient AMD of the void defect and transistor region class pixels intra (u,v) and inter-class difference coefficient AMD inter The expression of (u,v) include: AMD intra (u,v)=ω tran (u,v)×d tran (u,v)+ω void (u,v)×d void (u,v) In the formula, AMD intra The smaller (u,v) is, the better the intra-class aggregation of void defects and transistor area pixels is; AMD inter The larger (u,v) is, the greater the difference between the void defect and the transistor area pixel; d tran (u,v) represents the intra-class mean absolute value difference of the pixels in the transistor area; d void (u,v) represents the intra-class mean absolute value difference of the pixels in the hole defect area; μ(u,v)1 and μ(u,v)2 represent the first and second elements of μ(u,v), respectively.

9. A MOSFET internal void defect detection system, used to implement the MOSFET internal void defect detection method according to any one of claims 1 to 8, characterized in that: include: An image acquisition module, which acquires an X-ray image of the MOSFET; A vertex detection module, used to detect the vertex position of the transistor in the X-ray image, and determine the transistor area based on the vertex position; A void defect partition detection module is used to divide the transistor area into a plurality of partitions, calculate the similarity between the partition grayscale distribution and the fitted Gaussian distribution for each partition, and determine whether the similarity is less than a preset similarity threshold. If so, the partition corresponding to the similarity is considered to contain a void defect; otherwise, based on the pixel grayscale value calculation, find the pixel with the largest grayscale value in the partition corresponding to the similarity; determine whether the pixel with the largest grayscale value is a void defect pixel. If so, the partition is considered to contain a void defect, otherwise, the partition is considered not to contain a void defect; The void defect positioning module locates the void defects in the partition containing the void defects.

10. A computer device comprising a memory and a processor, wherein the memory stores computer-readable instructions, characterized in that: When the computer-readable instructions are executed by the processor, the processor executes the steps of the internal void defect detection method of MOSFET according to any one of claims 1 to 8.

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