Multi-channel real-time synchronous acquisition system and method based on FPGA (Field Programmable Gate Array)

Abstract

The multichannel real-time synchronous acquisition system comprises an isolation acquisition input circuit, an Ethernet circuit and an FPGA synchronous detection circuit serving as a state machine, the input end of the isolation acquisition input circuit is connected with an acquisition object, and the input end of the Ethernet circuit is connected with an external connector; the output end of the isolation acquisition input circuit and the output end of the Ethernet circuit are connected with the FPGA synchronous detection circuit, during operation, the FPGA achieves high-speed synchronous acquisition according to the time sequence of a state machine, meanwhile, based on the high-speed and synchronous performance of the FPGA, synchronous acquisition and diagnosis self-inspection based on the same clock source can be achieved, and precise time synchronization can be achieved by adopting a software mode of a time beacon. Through the mode, the multi-channel real-time synchronous acquisition system and method based on the FPGA can effectively solve the technical problem of time offset during high-speed multi-channel synchronous acquisition, and greatly ensure the time synchronization, data real-time performance and reliability of acquired data through the high synchronization performance of the FPGA.

Description

Technical Field

[0001] The present invention relates to the field of rail transportation technology, and in particular to a multi-channel real-time synchronous acquisition system and method based on FPGA. Background Art

[0002] Intelligence is one of the themes of the 21st century. The development of intelligence has been integrated into all walks of life. With the advent of the digital age, artificial intelligence has been widely used. It has been fully implemented in many fields such as manufacturing, finance, medical care, security, transportation, retail, education and logistics. In the field of security of intelligent equipment investment, higher requirements are put forward for safety redundancy technology, which is more prominent in the fields of unmanned driving technology of automobiles / rail transportation, aerospace technology, and military defense technology.

[0003] At present, data acquisition in rail transit control systems is usually completed using single-chip microcomputers and DSPs. Even though the processing frequency and clock frequency of the MCU processor are already extremely high, the MCU time slice operation mechanism cannot be changed. Concurrent processing such as multi-channel acquisition and communication is affected by the time slice, and there is a phenomenon of acquisition asynchrony to varying degrees.

[0004] Currently, the timing and clock synchronization based on the RTC real-time clock and NTP network clock protocol only have the entry clock, and due to the influence of the time slice, there are clock errors to varying degrees.

[0005] Therefore, building a system that can still ensure clock synchronization under multi-channel acquisition mode is not only more reliable in data storage, but also can provide application data that better meets the actual status in data analysis and data application, which is also of positive significance to improving data reliability and big data analysis capabilities. Summary of the invention

[0006] The main technical problem solved by the present invention is to provide a multi-channel real-time synchronous acquisition system and method based on FPGA. The main controller FPGA realizes high-speed synchronous acquisition according to the state machine timing. At the same time, based on the high-speed and synchronous performance of FPGA, synchronous acquisition and diagnostic self-test based on the same clock source can be realized, and precise time synchronization can be achieved by using the software method of time beacon.

[0007] In order to solve the above technical problems, a technical solution adopted by the present invention is: to provide a multi-channel real-time synchronous acquisition system based on FPGA, characterized in that it includes: an isolated acquisition input circuit, an Ethernet circuit and an FPGA synchronization detection circuit as a state machine, the FPGA synchronization detection circuit includes a main controller FPGA, the input end of the isolated acquisition input circuit is connected to the acquisition object, wherein the input ends A_CH and B_CH are a group of isolated loops formed with a common ground COM_A, the output ends V1P and V2P of the isolated acquisition input circuit are respectively connected to the input ends CH1_IN and CH2_IN of the main controller FPGA, the input end of the Ethernet circuit is connected to an external connector, and the output end of the Ethernet circuit is connected to the PHY interface of the main controller FPGA.

[0008] In a preferred embodiment of the present invention, the isolated acquisition input circuit includes a plurality of acquisition channels capable of synchronous acquisition, and the plurality of acquisition channels are isolated from different sources.

[0009] In a preferred embodiment of the present invention, the isolated acquisition input circuit may further include input terminals C_CH and D_CH, and C_CH and D_CH are a group that can form an isolated loop with the common ground COM_B.

[0010] In a preferred embodiment of the present invention, the isolation acquisition input circuit It includes: a varistor RV27, a fuse FB32 of a common line, a current limiting resistor R686, and a sampling bridge 1 composed of precision sampling resistors R680, R681, R682 and R685, a voltage regulator tube D127 is arranged behind the sampling bridge 1, and a back-stage anti-reverse diode bridge stack D125, D126, D128 and D129 is arranged behind the voltage regulator tube D127; It also includes: a varistor RV28, a fuse FB32 of a common line, a current limiting resistor R686, and a sampling bridge 2 composed of precision sampling resistors R689, R690, R692 and R688. A voltage regulator tube D132 is arranged behind the sampling bridge 2, and an anti-reverse diode bridge stack D130, D131, D133 and D134 are arranged at the rear stage of the voltage regulator tube D132.

[0011] In a preferred embodiment of the present invention, the varistor RV27 is connected in parallel between the positive terminal A_CH and the common terminal COM_CH of the sampling circuit, and the varistor RV28 is connected in parallel between the positive terminal B_CH and the common terminal COM_CH of the sampling circuit.

[0012] In a preferred embodiment of the present invention, one end of the fuse FB32 is connected to the common terminal COM_CH, and the other end is connected to the current limiting resistor R686. The other end of the current limiting resistor R686 is respectively connected to the sampling resistor R687 and the capacitor C694. The other ends of the sampling resistor R687 and the capacitor C694 lead to the output common terminal of the sampling circuit.

[0013] In a preferred embodiment of the present invention, the Ethernet circuit includes: an Ethernet chip PHY1, a network transformer TR2, a pull-up resistor, a voltage regulator tube and a filter circuit. The input end of the Ethernet chip PHY1 is connected to an external connector, and the TXD_P end, TXD_N end, RXD_P end, and RXD_N end of the Ethernet chip PHY1 are connected to the network transformer TR2 and then connected to the PHY interface of the main controller FPGA. The TXD_P terminal, TXD_N terminal, RXD_P terminal, and RXD_N terminal of the Ethernet chip PHY1 are also connected to a pull-up resistor, a power supply Vcc, and a voltage regulator tube, and a filter circuit is connected to the network transformer TR2.

[0014] In a preferred embodiment of the present invention, the Ethernet circuit of the master controller FPGA uses the PTP protocol standard to perform Ethernet time synchronization, wherein the timestamp is derived from the Ethernet reference absolute time, the clock frequency of the crystal oscillator and the clock frequency of the state machine.

[0015] In order to solve the above technical problems, another technical solution adopted by the present invention is: to provide a multi-channel real-time synchronous acquisition method based on FPGA, using the multi-channel real-time synchronous acquisition system based on FPGA, the steps are as follows: S1, when the Ethernet circuit uses the PTP protocol for time synchronization, the master controller FPGA records the time t1, which contains the original clock timestamp; S2, the main controller FPGA has a crystal oscillator inside, and the tick count is performed according to the crystal oscillator frequency. S3, the master controller FPGA adds the t1+tick1 count to the returned PTP time message and records it as t2; S4, the master controller FPGA receives the next PTP message and records it as t3; S5, the master controller FPGA calculates the link delay by comparing the time difference between timestamps t3 and t2; S6, captures the interaction messages between the master and slave clocks through Ethernet packet capture software, calculates the time difference from the messages, and then applies the time difference to the clock synchronization correction process, completing the continuous optimization of link calculation time and finally achieving time synchronization.

[0016] The beneficial effects of the present invention are: it can effectively solve the problem of time deviation caused by acquisition time error and synchronization deviation in the process of multi-channel acquisition and data storage. When the above deviation occurs, the high synchronization of FPGA and the software clock algorithm can greatly ensure the time synchronization of the acquired data and the real-time and reliability of the data, and complete the upgrade under the condition of relatively small increase in hardware investment. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work, among which: Figure 1 It is a structural schematic diagram of a preferred embodiment of the FPGA-based multi-channel real-time synchronous acquisition system of the present invention; Figure 2 It is a structural schematic diagram of a preferred embodiment of the isolation acquisition input circuit of the present invention; Figure 3 It is a structural schematic diagram of a preferred embodiment of the Ethernet circuit of the present invention; Figure 4 It is a schematic diagram of the clock algorithm mechanism of the present invention; DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0019] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] Example 1: Please refer to Figure 1This embodiment provides a multi-channel real-time synchronous acquisition system based on FPGA, which can realize high-speed synchronous acquisition, and includes: an isolated acquisition input circuit, an Ethernet circuit and an FPGA synchronous detection circuit as a state machine, wherein the input end of the isolated acquisition input circuit is connected to the acquisition object, the input end of the Ethernet circuit is connected to the external connector, and the output ends of the isolated acquisition input circuit and the Ethernet circuit are connected to the FPGA synchronous detection circuit.

[0021] In an exemplary embodiment, the FPGA synchronization detection circuit includes a main controller FPGA, the input terminals A_CH and B_CH of the isolated acquisition input circuit form an isolation loop with a common ground COM_A, the output terminals V1P and V2P of the isolated acquisition input circuit are respectively connected to the input terminals CH1_IN and CH2_IN of the main controller FPGA, and the output terminal of the Ethernet circuit is connected to the PHY interface of the main controller FPGA.

[0022] In this embodiment, the isolated acquisition input circuit may be provided with multiple acquisition channels capable of synchronous acquisition. The multiple acquisition channels isolate different sources from each other, thereby preventing mutual influence between different signal sources and ensuring the accuracy of measurement data and the stability of the system.

[0023] For example, the isolation acquisition input circuit may further include input terminals C_CH and D_CH. The input terminals C_CH and D_CH are a group that can form another isolation loop with the common ground COM_B.

[0024] In an exemplary embodiment, if Figure 2 As shown, the isolated acquisition input circuit includes: a varistor RV27, a varistor RV28, an acquisition loop 1, an acquisition loop 2, and a fuse FB32 and a current limiting resistor R686 of a common line: Specifically, first, the varistor RV27 is connected in parallel between the positive terminal A_CH and the common terminal COM_CH of the sampling circuit, and the varistor RV28 is connected in parallel between the positive terminal B_CH and the common terminal COM_CH of the sampling circuit.

[0025] Secondly, the acquisition circuit 1 includes a sampling bridge 1 composed of precision sampling resistors R680, R681, R682 and R685, a voltage regulator D127, and an anti-reverse diode bridge stack D125, D126, D128, and D129 arranged at the rear stage of the voltage regulator D127.

[0026] In addition, the acquisition loop 2 includes a sampling bridge composed of precision sampling resistors R689, R690, R692 and R688, a voltage regulator D132, and an anti-reverse diode bridge stack D130, D131, D133, and D134 arranged at the rear stage of the voltage regulator D132.

[0027] Based on the above situation, the varistor RV27 is connected in parallel between the positive terminal A_CH and the common terminal COM_CH of the sampling circuit, the varistor RV28 is connected in parallel between the positive terminal B_CH and the common terminal COM_CH of the sampling circuit, one end of the fuse FB32 is connected to the common terminal COM_CH, and the other end is connected to the current limiting resistor R686, the other end of the current limiting resistor R686 is respectively connected to the sampling resistor R687 and the capacitor C694, and the other ends of the sampling resistor R687 and the capacitor C694 are led to the output common terminal of the sampling circuit.

[0028] In more detail, the precision sampling resistors R680, R681 and R682 are connected in series in sequence, and the other end of the precision sampling resistor R682 is respectively connected to the precision sampling resistor R685, the capacitor C693, the voltage regulator D127, the positive electrode of the anti-reverse diode D125, the negative electrode of the anti-reverse diode D126 and the sampling resistor R679. The precision sampling resistor R685, the capacitor C693, and the other end of the voltage regulator tube D127 are connected between the current limiting resistor R686 and the sampling resistor R687, the anti-reverse diodes D125 and D128 are connected in series, the anti-reverse diodes D129 and D126 are connected in series, the anti-reverse diodes D125, D126, D128, and D129 are connected to the output common end respectively, and the other end of the sampling resistor R679 is connected to the output end V1P; Furthermore, the precision sampling resistors R689, R690 and R692 are connected in series in sequence, and the other end of the precision sampling resistor R692 is respectively connected to the precision sampling resistor R688, the capacitor C696, the voltage regulator tube D132, the cathode of the anti-reverse diode D133, the anode of the anti-reverse diode D134 and the sampling resistor R693. The other end of the precision sampling resistor R688, the capacitor C696, and the voltage regulator D132 are connected between the current limiting resistor R686 and the sampling resistor R687, the anti-reverse diodes D130 and D133 are connected in series, the anti-reverse diodes D131 and D134 are connected in series, the anti-reverse diodes D130, D131, D133, and D134 are respectively connected to the output common end, and the other end of the sampling resistor R693 is connected to the output end V2P.

[0029] In this embodiment, the isolated acquisition input circuit may further include a safety capacitor Y1 for electrostatic protection and voltage resistance, which can ensure circuit protection with high reliability and safety.

[0030] In an exemplary embodiment, if Figure 3As shown, the Ethernet circuit includes: an Ethernet chip PHY1, a network transformer TR2, a pull-up resistor, a voltage regulator and a filter circuit. The input end of the Ethernet chip PHY1 is connected to an external connector. The TXD_P end, TXD_N end, RXD_P end and RXD_N end of the Ethernet chip PHY1 are connected to the network transformer TR2 and then connected to the PHY interface of the main controller FPGA. The TXD_P end, TXD_N end, RXD_P end and RXD_N end of the Ethernet chip PHY1 are also connected to a pull-up resistor, a power supply Vcc and a voltage regulator. The network transformer TR2 is connected to a filter circuit.

[0031] Specifically, first, the TXD_P and TXD_N terminals of the Ethernet chip PHY1 are respectively connected to the TD+ and TD- terminals of the network transformer TR2, and then output through the TX+ and TX- terminals of the network transformer TR2; the output terminals RXD_P and RXD_N of the Ethernet chip PHY1 are respectively connected to the RD+ and RD- terminals of the network transformer TR2, and then output through the RX+ and RX- terminals of the network transformer TR2.

[0032] Secondly, the pull-up resistors include resistors R215, R231, R233, and R235. One ends of the resistors R215, R231, R233, and R235 are respectively connected to the output ends TXD_P, TXD_N, RXD_P, and RXD_N of the Ethernet chip PHY1, and the other ends of the resistors R215, R231, R233, and R235 are connected to the power supply Vcc to ensure that the differential output and input signals of the Ethernet chip PHY1 can be maintained within a stable voltage range, thereby improving the reliability and stability of communication.

[0033] The voltage regulator tubes include voltage regulator tubes D21 and D22. The voltage regulator tube D21 is connected in parallel between the output end TXD_P and the output end TXD_N of the Ethernet chip PHY1, and the voltage regulator tube D22 is connected in parallel between the output end RXD_P and the output end RXD_N of the Ethernet chip PHY1, so as to protect the differential output signal pair of the Ethernet chip PHY1 from damage by overvoltage and improve the reliability and stability of communication.

[0034] In addition, the filter circuit includes filter inductors FB51, FB50, FB7, FB12, a varistor RV5 and a filter capacitor C439: One end of the filter inductor FB50 and FB51 is connected to the 2nd and 7th pins of the network transformer TR2 respectively, and the other end of the filter inductor FB50 and FB51 is connected to the power supply Vcc. One end of the filter inductor FB7 and FB12 is connected to the 10th and 15th pins of the network transformer TR2 respectively, and the other end of the filter inductor FB7 and FB12 is connected to the power supply Vcc. The varistor RV5 is connected in series with the filter inductor FB7, and the filter capacitor C439 is connected in series with the filter inductor FB12.

[0035] The configuration of the above-mentioned filter circuit reduces the noise and interference on the power line, ensuring that the network transformer TR2 can work stably. The addition of the varistor RV5 and the filter capacitor C439 can further enhance the anti-interference ability of the circuit.

[0036] The synchronous acquisition system of the present invention requires differential impedance matching for Ethernet circuits based on time synchronization requirements, which can reduce signal reflection, improve signal anti-interference ability and ensure time synchronization accuracy.

[0037] During operation, the main controller FPGA realizes high-speed synchronous acquisition according to the state machine timing. At the same time, based on the high-speed and synchronous performance of FPGA, on the one hand, it can realize synchronous acquisition and diagnostic self-test based on the same clock source, and on the other hand, it can adopt the software method of time beacon to realize precise time synchronization.

[0038] Furthermore, the Ethernet circuit of the main controller FPGA adopts the PTP protocol standard to perform Ethernet time synchronization, wherein the timestamp is derived from the Ethernet reference absolute time, the clock frequency of the crystal oscillator and the clock frequency of the state machine, and the timestamp superimposed in a counting manner is used as the relative time, which is used as the counting reference to achieve multi-channel clock synchronization.

[0039] In the Ethernet circuit of FPGA, the master controller FPGA is the core processing unit, responsible for implementing the relevant functions of the PTP protocol. The master controller FPGA can complete the generation and recording of timestamps, the transmission of timestamps and time synchronization calculations.

[0040] The master controller FPGA can receive the records of two timestamps, calculate the time difference between the two timestamps, capture the interaction messages between the master and slave clocks through the Ethernet packet capture software, calculate the time difference from the messages, and then apply the time difference to the clock synchronization correction process, making the clock synchronization much higher than the traditional timing system.

[0041] Embodiment 2: Based on the FPGA-based multi-channel real-time synchronous acquisition system of embodiment 1, this embodiment provides a FPGA-based multi-channel real-time synchronous acquisition method, including the following steps: S1, receives the PTP synchronization message and records the timestamp t1: When the master controller FPGA receives a PTP synchronization message, it first records an original clock timestamp t1, which represents the physical time point when the message arrives at the FPGA.

[0042] S2, internal tick count: The master controller FPGA uses a high-precision crystal oscillator to generate a clock signal, and counts ticks based on this clock signal to calculate the time interval. Starting from time t1, the FPGA continuously records the number of ticks (tick1) to track the passage of time.

[0043] S3, sends a PTP response message and adds the updated timestamp t2: When the master controller FPGA is ready to send a PTP response message, it calculates t1 plus the number of ticks that have passed since t1 (tick1) to obtain t2. This t2 is the current time when the FPGA sends the message and is included in the PTP response message as a timestamp and sent to the peer device.

[0044] S4, receive the next PTP message and record the timestamp (t3): When the master controller FPGA receives the next PTP message, it records the timestamp t3 again. After the master clock device or other slave devices receive this message, they can calculate the link delay by comparing the time difference between t3 and t2.

[0045] S5, calculate the link delay: The master controller FPGA calculates the link delay by comparing the timestamp t3 with the previously sent timestamp t2 (actually t1+tick1); Because t2 and t3 represent the time points when the PTP response message is sent and the next PTP message is received, respectively, the difference between them (t3 - (t1 + tick1)) can be used to estimate half of the round-trip delay (assuming the link is symmetrical). The accuracy of the delay estimate can be further improved by multiple measurements and averaging.

[0046] S6, Optimize and Sync: The interactive messages between the master and slave clocks are captured through Ethernet packet capture software, and the timestamp information is extracted from the messages. The time difference is calculated by comparing the timestamps of the master and slave clocks. The time difference obtained through the calculation of the master controller FPGA and the analysis of the packet capture software is then applied to the correction of clock synchronization. The local clock of the FPGA is continuously adjusted according to the measurement results to achieve high-precision time synchronization.

[0047] This embodiment applies the time difference obtained through FPGA calculation and packet capture software analysis to the clock synchronization correction process. Through this correction process, the accuracy of clock synchronization can be significantly improved, with higher flexibility and accuracy, and can monitor and correct clock deviations in real time, ensuring that the synchronization between various clock sources reaches a higher level.

[0048] The beneficial effects of the multi-channel real-time synchronous acquisition system and method based on FPGA of the present invention are: Improve synchronization accuracy: Through accurate time difference measurement and dynamic correction algorithm, the accuracy of clock synchronization can be significantly improved; Enhanced flexibility and accuracy: FPGA programmability allows synchronization correction algorithms to be optimized and dynamically adjusted according to specific needs; Real-time monitoring and correction: The real-time monitoring function can detect and correct clock deviation in time, ensure that the system is always in a synchronized state, reduce errors and failures, and be more credible in data storage. It can solve the problem of time deviation in multi-channel acquisition and data storage, and ensure the time synchronization and real-time nature of the acquired data; Lower hardware investment cost: Compared with traditional clock synchronization solutions, this solution has relatively small hardware investment. The flexibility and reusability of FPGA make system upgrades and expansions easier and more economical.

[0049] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A multi-channel real-time synchronous acquisition system based on FPGA, characterized in that: include: An isolation acquisition input circuit, an Ethernet circuit and an FPGA synchronization detection circuit as a state machine, wherein the FPGA synchronization detection circuit includes a main controller FPGA, The input end of the isolation acquisition input circuit is connected to the acquisition object, wherein the input ends A_CH and B_CH form a group with the common ground COM_A to form an isolation loop. The output terminals V1P and V2P of the isolation acquisition input circuit are connected to the input terminals CH1_IN and CH2_IN of the main controller FPGA respectively. The input end of the Ethernet circuit is connected to an external connector, and the output end of the Ethernet circuit is connected to a PHY interface of the main controller FPGA.

2. The FPGA-based multi-channel real-time synchronous acquisition system according to claim 1, characterized in that: The isolated acquisition input circuit includes a plurality of acquisition channels capable of synchronous acquisition, and the plurality of acquisition channels are isolated from different sources.

3. The FPGA-based multi-channel real-time synchronous acquisition system according to claim 2, characterized in that: The isolated acquisition input circuit may further include input terminals C_CH and D_CH, where C_CH and D_CH form a group and may form an isolated loop with a common ground COM_B.

4. The FPGA-based multi-channel real-time synchronous acquisition system according to claim 1, characterized in that: The isolation acquisition input circuit It includes: a varistor RV27, a fuse FB32 of a common line, a current limiting resistor R686, and a sampling bridge 1 composed of precision sampling resistors R680, R681, R682 and R685, a voltage regulator tube D127 is arranged behind the sampling bridge 1, and a back-stage anti-reverse diode bridge stack D125, D126, D128 and D129 is arranged behind the voltage regulator tube D127; It also includes: a varistor RV28, a fuse FB32 of a common line, a current limiting resistor R686, and a sampling bridge 2 composed of precision sampling resistors R689, R690, R692 and R688. A voltage regulator tube D132 is arranged behind the sampling bridge 2, and an anti-reverse diode bridge stack D130, D131, D133 and D134 are arranged at the rear stage of the voltage regulator tube D132.

5. The FPGA-based multi-channel real-time synchronous acquisition system according to claim 4, characterized in that: The varistor RV27 is connected in parallel between the positive terminal A_CH and the common terminal COM_CH of the sampling circuit, and the varistor RV28 is connected in parallel between the positive terminal B_CH and the common terminal COM_CH of the sampling circuit.

6. The FPGA-based multi-channel real-time synchronous acquisition system according to claim 5, characterized in that: One end of the fuse FB32 is connected to the common terminal COM_CH, and the other end is connected to the current limiting resistor R686. The other end of the current limiting resistor R686 is respectively connected to the sampling resistor R687 and the capacitor C694. The other ends of the sampling resistor R687 and the capacitor C694 lead to the output common terminal of the sampling circuit.

7. The FPGA-based multi-channel real-time synchronous acquisition system according to claim 1, characterized in that: The Ethernet circuit includes: an Ethernet chip PHY1, a network transformer TR2, a pull-up resistor, a voltage regulator tube and a filter circuit. The input end of the Ethernet chip PHY1 is connected to an external connector, and the TXD_P end, TXD_N end, RXD_P end, and RXD_N end of the Ethernet chip PHY1 are connected to the network transformer TR2 and then connected to the PHY interface of the main controller FPGA. The TXD_P terminal, TXD_N terminal, RXD_P terminal, and RXD_N terminal of the Ethernet chip PHY1 are also connected to a pull-up resistor, a power supply Vcc, and a voltage regulator tube, and a filter circuit is connected to the network transformer TR2.

8. The FPGA-based multi-channel real-time synchronous acquisition system according to claim 1, characterized in that: The Ethernet circuit of the master controller FPGA adopts the PTP protocol standard to perform Ethernet time synchronization, wherein the timestamp is derived from the reference absolute time of the Ethernet, the clock frequency of the crystal oscillator and the clock frequency of the state machine.

9. A multi-channel real-time synchronous acquisition method based on FPGA, characterized in that: Using the FPGA-based multi-channel real-time synchronous acquisition system as described in any one of claims 1 to 8, the steps are as follows: S1, when the Ethernet circuit uses the PTP protocol for time synchronization, the master controller FPGA records the time t1, which contains the original clock timestamp; S2, the main controller FPGA has a crystal oscillator inside, and the tick count is performed according to the crystal oscillator frequency. S3, the master controller FPGA adds the t1+tick1 count to the returned PTP time message and records it as t2; S4, the master controller FPGA receives the next PTP message and records it as t3; S5, the master controller FPGA calculates the link delay by comparing the time difference between timestamps t3 and t2; S6, captures the interaction messages between the master and slave clocks through Ethernet packet capture software, calculates the time difference from the messages, and then applies the time difference to the clock synchronization correction process, completing the continuous optimization of link calculation time and finally achieving time synchronization.

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