High-precision band-gap reference circuit with offset elimination function

Abstract

The invention provides a high-precision band-gap reference circuit with an offset elimination function. The high-precision band-gap reference circuit comprises a band-gap reference amplifier A1; the band-gap reference amplifier A1 comprises a square wave generator circuit, a clock circuit and an offset elimination circuit; the square wave generator circuit, the clock circuit and the offset cancellation circuit are connected in sequence; the square wave generator circuit generates a clock signal and transmits the clock signal to the clock circuit; the clock circuit comprises a first NOR gate and a second NOR gate, and capacitors are additionally arranged at the output ends of the first NOR gate and the second NOR gate respectively; and a capacitor is additionally arranged in a feedback path of the offset elimination circuit and is used for storing the offset quantity. When a square wave generator and a two-phase non-overlapping clock control single-end input in the circuit are zero, offset is measured, and the offset amount is stored on a capacitor at an output end, so that the influence of input offset is counteracted at the output end.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a high-precision bandgap reference circuit with an offset elimination function. Background Art

[0002] The bandgap reference can provide a clear, stable voltage that is insensitive to power supply voltage and temperature changes. It is widely used in pure analog and mixed analog and digital circuits. The accuracy and stability of this type of reference plays an important role in the performance of subsequent circuits. The bandgap reference voltage with a zero temperature coefficient is composed of a device voltage that is negatively correlated with temperature and a device voltage that is positively correlated with temperature, which can eliminate the effect of temperature on the output voltage. The traditional first-order bandgap reference circuit is composed of a transistor, an amplifier, and a resistor. The zero-temperature bandgap reference voltage is obtained by adding the weighted sum of the emitter-base voltage VBE with a negative temperature coefficient and the thermal voltage VT with a positive temperature coefficient.

[0003] In conventional bandgap reference sources, due to the asymmetry caused by device mismatch, there is a certain input offset voltage Vos in the main amplifier of the bandgap reference. In actual circuits, some non-ideal characteristics introduced in the process manufacturing circuit will reduce the accuracy of the bandgap reference. These non-ideal characteristics include random factors such as device mismatch, absolute value deviation and package stress. In addition, if over-etching occurs, the length of all transistors will be less than the standard length. These process manufacturing errors will cause device mismatch, which is mainly reflected in the input offset voltage Vos of the amplifier. All of the above non-ideal characteristics will cause errors in the bandgap reference temperature coefficient and output voltage. This will introduce errors in the output voltage. Summary of the invention

[0004] In order to solve the above technical problems, the present application proposes a high-precision bandgap reference circuit with an offset elimination function, comprising: a bandgap reference amplifier A1; the bandgap reference amplifier A1 comprises a square wave generator circuit, a clock circuit and an offset elimination circuit; the square wave generator circuit, the clock circuit and the offset elimination circuit are connected in sequence; the square wave generator circuit generates a clock signal and transmits it to the clock circuit; the clock circuit comprises a first NOR gate and a second NOR gate, and capacitors are respectively added to the output ends of the first NOR gate and the second NOR gate; a capacitor is added in the feedback path of the offset elimination circuit, and the capacitor is used to store the offset.

[0005] Specifically, it also includes: a startup circuit; the startup circuit includes a comparator A2; a compensation voltage V is applied to the non-inverting input terminal of the comparator A2 COMP The output terminal of comparator A2 outputs a start voltage V in response to the comparison result between the non-inverting input terminal and the inverting input terminal of comparator A2. start ; Among them, when V COMP >V反相输入端 Time V star t outputs high level, otherwise it outputs low level.

[0006] Specifically, it includes: MOS tube M2, MOS tube M3, MOS tube M4, resistor R1, resistor R2, resistor R3, resistor R4, transistor Q1, transistor Q2 and transistor Q3; the in-phase input end of the bandgap reference amplifier A1 is simultaneously connected to one end of the resistor R3 and the emitter of the transistor Q2, and the base of the transistor Q2 is connected to the collector and grounded; the inverting input end of the bandgap reference amplifier A1 is simultaneously connected to one end of the resistor R2 and one end of the resistor R1, the other end of the resistor R1 is connected to the emitter of the transistor Q1, and the base of the transistor Q1 is connected to the collector and grounded; the output end of the bandgap reference amplifier A1 is simultaneously connected to the start The gate of MOS tube M4 and the gate of MOS tube M5 are connected; the source of MOS tube M4 is connected to the startup circuit, the other end of resistor R3 and the other end of resistor R2 at the same time; one end of resistor R4 is connected to the emitter of transistor Q3, and the other end is connected to the source of MOS tube M5, the base of transistor Q3 is connected to the collector and grounded; the gate of MOS tube M3 is connected to the gate of MOS tube M2, and the source of MOS tube M3 is connected to the drain of MOS tube M5; the startup circuit, the drain of MOS tube M2 and the drain of MOS tube M3 are all connected to VCC; and the gate of MOS tube M2 and the gate of MOS tube M3 are both applied with control voltage V B1 .

[0007] Specifically, the startup circuit includes: a comparator A2 and a MOS tube M1; the gate of the MOS tube M1 is connected to the output end of the comparator A2, the drain is connected to VCC, and the source is simultaneously connected to the gate of the MOS tube M4, the gate of the MOS tube M5 and the output end of the bandgap reference amplifier A1; the inverting input end of the comparator A2 is simultaneously connected to the source of the MOS tube M4, the resistor R2 and the resistor R3, and the control voltage V is applied to the in-phase input end. comp .

[0008] Specifically, the square wave generator circuit includes: MOS tube M6, MOS tube M7, MOS tube M8, MOS tube M9, MOS tube M10, MOS tube M11, MOS tube M12, resistor R5, resistor R6, resistor R7, current source, capacitor C1 and a first NOT gate; the input end of the first NOT gate is simultaneously connected to the source of the MOS tube M6 and the drain of the MOS tube M9, and the output end is simultaneously connected to the gate of the MOS tube M7 and the gate of the MOS tube M8; the source of the MOS tube M7 is connected to the gate of the MOS tube M6, and the drain is connected to one end of the resistor R5; The other end of the resistor R5 is connected to one end of the resistors R6 and R7 at the same time; the source of the MOS tube M8 is grounded, and the drain is connected to the other end of the resistor R6; the gate of the MOS tube M9 is connected to the capacitor C1 and the other end of the resistor R7 at the same time, and the source is connected to the drain of the MOS tube M10 and the source of the MOS tube M12 at the same time; the gate of the MOS tube M10 is connected to the drains of the MOS tube M11 and the MOS tube M12 at the same time, and the source of the MOS tube M10 is grounded; the current source is connected to the drain of the MOS tube M6, the gate of the MOS tube M11, and the gate of the MOS tube M12 at the same time.

[0009] Specifically, the clock circuit includes: a capacitor C2, a capacitor C3, a second NOT gate, a third NOT gate, a fourth NOT gate, a fifth NOT gate, a sixth NOT gate, a seventh NOT gate, a first NOR gate and a second NOR gate; the output end of the second NOR gate is simultaneously connected to the first input end of the first NOR gate and the input end of the third NOR gate; the output end of the third NOR gate is connected to the second input end of the second NOR gate; the second input end of the first NOR gate is simultaneously connected to the output end of the second NOR gate and the input end of the sixth NOR gate, and is grounded through the capacitor C3; the output end of the first NOR gate is simultaneously connected to the first input end of the second NOR gate and the input end of the fourth NOR gate, and is grounded through the capacitor C2; the output end of the fourth NOR gate outputs a second level signal, and outputs a first level signal via the output end of the fifth NOR gate; the output end of the sixth NOR gate outputs a fourth level signal, and outputs a third level signal via the output end of the seventh NOR gate.

[0010] By using two non-overlapping clocks, the output of the clock is used to control the offset cancellation circuit in the bandgap reference amplifier A1.

[0011] Specifically, the offset elimination circuit includes: switch S0, switch S1, switch S2, switch S3, switch S4, capacitor C4, capacitor C5, amplifier Gm1, amplifier Gm2, amplifier R1, amplifier R2 and offset voltage Vos1; switch S0, offset voltage Vos1 and the non-inverting input terminal of amplifier Gm1 are connected in sequence; switch S1 is simultaneously connected to the non-inverting input terminal and the inverting input terminal of amplifier Gm1; the output terminal of amplifier Gm1 is connected to the input terminal of amplifier R1; the output of amplifier R1 is simultaneously connected to the switch S2, switch S3 and switch S4, and receives the feedback signal output by amplifier R2; the inverting input terminal of amplifier Gm2 is simultaneously connected to switch S3 and capacitor C4, the non-inverting input terminal is simultaneously connected to switch S4 and capacitor C5, and the output terminal is connected to the input terminal of amplifier R2.

[0012] By means of the above technical means, the offset circuit can reduce the A1 equivalent total offset voltage of the bandgap reference, thereby improving the accuracy of the bandgap reference output voltage.

[0013] Specifically, the size ratio of the transistors Q1 , Q2 and Q3 is 7:1:1.

[0014] Specifically, the switch S0 and the switch S2 are in the same state; the switches S1, S3 and the switch S4 are in the same state, and the state of the switch S0 is complementary to the state of the switch S1.

[0015] Specifically, the switch S0 responds to the third level signal; the switch S1 responds to the first level signal; the switch S2 responds to the second level signal; the switch S3 responds to the fourth level signal; and the switch S4 responds to the third level signal.

[0016] Specifically, the resistance value of the resistor R2 is the same as the resistance value of the resistor R3.

[0017] Compared with the prior art, the beneficial results of this application are:

[0018] By eliminating the offset of the input voltage of the bandgap reference main amplifier. Using a square wave generator and a two-phase non-overlapping clock, the offset storage circuit can be turned on after the bandgap reference main amplifier circuit is turned off, and turned off before the bandgap reference main amplifier circuit is turned on, so as to ensure the accuracy of the offset voltage storage. By eliminating the offset problem of the bandgap reference amplifier, the accuracy of the output voltage can be improved, and its temperature stability can be improved, thereby effectively improving the reliability of the bandgap reference. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate the embodiments and are used together with the description to explain the principles of the present application. It will be easy to recognize other embodiments and many expected advantages of the embodiments because they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale with each other. The same reference numerals refer to corresponding similar parts.

[0020] Figure 1 This is a conventional bandgap reference circuit diagram;

[0021] Figure 2 is a circuit diagram of a high-precision bandgap reference circuit with an offset elimination function according to an embodiment of the present application;

[0022] Figure 3 is a circuit diagram of a bandgap reference amplifier A1 of a high-precision bandgap reference circuit with an offset cancellation function according to an embodiment of the present application;

[0023] Figure 4 is a circuit diagram of a square wave generator circuit of a high-precision bandgap reference circuit with an offset elimination function according to an embodiment of the present application;

[0024] Figure 5 is a circuit diagram of a clock circuit of a high-precision bandgap reference circuit with an offset elimination function according to an embodiment of the present application;

[0025] Figure 6 4 is a circuit diagram of an offset cancellation circuit of a high-precision bandgap reference circuit with an offset cancellation function according to an embodiment of the present application.

[0027] 1. First NOT gate; 2. Second NOT gate; 3. Third NOT gate; 4. Fourth NOT gate; 5. Fifth NOT gate; 6. Sixth NOT gate; 7. Seventh NOT gate; 8. First OR NOT gate; 9. Second OR NOT gate. DETAILED DESCRIPTION

[0028] In the following detailed description, reference is made to the accompanying drawings, which form a part of the detailed description and are shown by illustrative specific embodiments in which the present application can be practiced. To this end, directional terms, such as "top", "bottom", "left", "right", "up", "down", etc., are used with reference to the orientation of the figures described. Because the components of the embodiments can be positioned in several different orientations, directional terms are used for the purpose of illustration and are by no means limiting. It should be understood that other embodiments may be utilized or logical changes may be made without departing from the scope of the present application. Therefore, the following detailed description should not be adopted in a limiting sense, and the scope of the present application is defined by the appended claims.

[0029] Figure 1 It is a traditional bandgap reference circuit diagram, such as Figure 1 As shown in the figure, the traditional bandgap reference voltage source is composed of an operational amplifier A1, field effect transistors M1 to M3, resistors R1, R2 and PNP tubes Q1 to Q3. The M1 to M3 transistors have the same width-to-length ratio. Since the operational amplifier A1 has a high gain, the voltages at points X and Y can be clamped to make them equal. When the area of ​​Q1 tube is N times that of Q2 tube, the current I with a positive temperature coefficient is PTAT The expression is:

[0030]

[0031] Where k is the Boltzmann constant, T is the absolute temperature (°C), and q is the electron charge (C);

[0032] The traditional first-order bandgap reference voltage V REF The expression is:

[0033]

[0034] It can be seen that as long as the parameters such as VBE3, resistors R1, R2 and transistor area ratio coefficient N are adjusted, a zero temperature coefficient voltage can be obtained.

[0035] When the operational amplifier generates an input offset voltage VOS, the offset voltage is taken into account in the bandgap reference output voltage, and equation (-2) is modified to obtain the traditional first-order bandgap reference output voltage:

[0036]

[0037] It can be seen that the input offset voltage VOS of the operational amplifier will be amplified by R2 / R1, which will increase the output error of the bandgap reference voltage and reduce the accuracy of the bandgap reference, thereby affecting the performance of subsequent circuits.

[0038] like Figures 2 to 3 As shown, a high-precision bandgap reference circuit with an offset elimination function includes: a startup circuit, a bandgap reference amplifier A1 and a plurality of triodes, resistors and MOS tubes; the bandgap reference amplifier A1 includes a square wave generator circuit, a clock circuit and an offset elimination circuit; the square wave generator circuit, the clock circuit and the offset elimination circuit are connected in sequence; the square wave generator circuit generates a clock signal and transmits it to the clock circuit; the clock circuit uses a two-phase non-overlapping clock to control the use of the clock in the offset elimination circuit; the offset elimination circuit stores the offset amount on a capacitor at the output end of the offset elimination circuit.

[0039] Specifically include: MOS tube M2, MOS tube M3, MOS tube M4, MOS tube M5, resistor R1, resistor R2, resistor R3, resistor R4, transistor Q1, transistor Q2 and transistor Q3; the in-phase input end of the bandgap reference amplifier A1 is simultaneously connected to one end of the resistor R3 and the emitter of the transistor Q2, and the base of the transistor Q2 is connected to the collector and grounded; the inverting input end of the bandgap reference amplifier A1 is simultaneously connected to one end of the resistor R2 and one end of the resistor R1, the other end of the resistor R1 is connected to the emitter of the transistor Q1, and the base of the transistor Q1 is connected to the collector and grounded; the output end of the bandgap reference amplifier A1 is simultaneously connected to one end of the resistor R2 and one end of the resistor R1 The starting circuit, the gate of MOS tube M4 and the gate of MOS tube M5 are connected; the source of MOS tube M4 is simultaneously connected to the starting circuit, the other end of resistor R3 and the other end of resistor R2; one end of resistor R4 is connected to the emitter of transistor Q3, and the other end is connected to the source of MOS tube M5, the base of transistor Q3 is connected to the collector and grounded; the gate of MOS tube M3 is connected to the gate of MOS tube M2, and the source of MOS tube M3 is connected to the drain of MOS tube M5; the starting circuit, the drain of MOS tube M2 and the drain of MOS tube M3 are all connected to VCC; and the gate of MOS tube M2 and the gate of MOS tube M3 are both applied with control voltage V B1 .

[0040] The startup circuit includes: a comparator A2 and a MOS tube M1; the gate of the MOS tube M1 is connected to the output end of the comparator A2, the drain is connected to VCC, and the source is simultaneously connected to the gate of the MOS tube M4, the gate of the MOS tube M5 and the output end of the bandgap reference amplifier A1; the inverting input end of the comparator A2 is simultaneously connected to the source of the MOS tube M4, the resistor R2 and the resistor R3, and the control voltage V is applied to the in-phase input end. comp .

[0041] It can be seen that the bandgap reference startup circuit is mainly composed of a comparator, which uses the positive and negative input voltages of comparator A2 for comparison. COMP >V1, comparator output voltage V start is high, M1 is turned on, and the gates of M4 and M5 are charged instantaneously, so that the bandgap reference circuit can escape the zero-solution steady state. COMP <V1, comparator output voltage V start It is low level, M1 tube is turned off, the startup circuit is turned off, and the normal operation of the bandgap reference is not affected.

[0042] In some specific embodiments, the size ratio of the transistors Q1 , Q2 and Q3 is 7:1:1.

[0043] Then when the bandgap reference is working normally, the circuit is through a voltage △V with a positive temperature coefficient BE With a voltage V with a negative temperature coefficient BE3Superposition, forming a zero-temperature bandgap reference voltage value V REF . Wherein, R2=R3, and the size ratio of Q1, Q2, and Q3 is 7:1:1. The voltage value expression of the bandgap reference of the present invention is as follows:

[0044]

[0045]

[0046] like Figure 4 As shown, the square wave generator circuit includes: MOS tube M6, MOS tube M7, MOS tube M8, MOS tube M9, MOS tube M10, MOS tube M11, MOS tube M12, resistor R5, resistor R6, resistor R7, current source, capacitor C1 and a first NOT gate; the input end of the first NOT gate is simultaneously connected to the source of the MOS tube M6 and the drain of the MOS tube M9, and the output end is simultaneously connected to the gate of the MOS tube M7 and the gate of the MOS tube M8; the source of the MOS tube M7 is connected to the gate of the MOS tube M6, and the drain is connected to one end of the resistor R5; the capacitor C1 is connected to the gate of the MOS tube M6 and the drain of the MOS tube M9 ... The other end of the resistor R5 is connected to one end of the resistors R6 and R7 at the same time; the source of the MOS tube M8 is grounded, and the drain is connected to the other end of the resistor R6; the gate of the MOS tube M9 is connected to the capacitor C1 and the other end of the resistor R7 at the same time, and the source is connected to the drain of the MOS tube M10 and the source of the MOS tube M12 at the same time; the gate of the MOS tube M10 is connected to the drains of the MOS tube M11 and the MOS tube M12 at the same time, and the source of the MOS tube M10 is grounded; the current source is connected to the drain of the MOS tube M6, the gate of the MOS tube M11 and the gate of the MOS tube M12 at the same time.

[0047] Furthermore, when CLK outputs a high level, that is, D is high, the gate voltage of M10 is equal to the voltage at point A. This connection method makes its internal resistance very large and makes the voltage at point A instantly high. B =V A +V GS9 , so the voltage at point B will also become higher. Due to capacitor C1, the voltage at point B will not change suddenly, so the voltage at point B is slowly raised by charging capacitor C1 through M7, R5 and R7. Since the gate voltage of M9 is raised, that is, M9 is turned on, the voltages at points C and D drop rapidly. When the voltage at point D drops to the flip voltage of the gates of M11 and M12, the gate voltage of M10 suddenly changes to VB3 and enters the next state. The full response formula of the first-order circuit is as follows:

[0048]

[0049] During the voltage rise at point B, f(∝) is the maximum voltage at point B, which is affected by V B2 The voltage value affects τ = 1 / (R5+R7)C1. Therefore, the oscillation frequency formula of its state is as follows:

[0050]

[0051] When CLK output is low level, that is, D is low level, the gate voltage of M10 is VB3, making its internal resistance very small, the voltage at point A decreases transiently, so the voltage at point B also decreases. Capacitor C1 is discharged through R7, R6, and M8, so that the voltage at point B decreases slowly. Since the gate voltage of M9 drops to the point where the tube is turned off, the voltages at points C and D rise rapidly, causing the circuit to return to the previous state, and thus a periodic clock CLK square wave is obtained in this cycle.

[0052] During the voltage drop at point B, the voltage at point B is the lowest, i.e., the ground voltage, τ = 1 / (R6+R7)C1. Therefore, the oscillation frequency formula of its state is as follows:

[0053]

[0054] like Figure 5 As shown, the clock circuit includes: a capacitor C2, a capacitor C3, a second NOT gate 2, a third NOT gate 3, a fourth NOT gate 4, a fifth NOT gate 5, a sixth NOT gate 6, a seventh NOT gate 7, a first NOR gate 8 and a second NOR gate; the output end of the second NOR gate 2 is simultaneously connected to the first input end of the first NOR gate 8 and the input end of the third NOR gate 3; the output end of the third NOR gate 3 is connected to the second input end of the second NOR gate; the second input end of the first NOR gate 8 is simultaneously connected to the output end of the second NOR gate and the input end of the sixth NOR gate 6, and is grounded through the capacitor C3; the output end of the first NOR gate 8 is simultaneously connected to the first input end of the second NOR gate and the input end of the fourth NOR gate 4, and is grounded through the capacitor C2; the output end of the fourth NOR gate 4 outputs a second level signal, and outputs a first level signal via the output end of the fifth NOR gate 5; the output end of the sixth NOR gate 6 outputs a fourth level signal, and outputs a third level signal via the output end of the seventh NOR gate 7.

[0055] In traditional clock design, the clock signal is usually a periodic square wave model, and the circuit is triggered by its rising edge and falling edge. However, the rising edge and falling edge of the traditional clock will overlap at the same time, resulting in one switch failing to completely close and the other switch being turned on, causing circuit errors. Therefore, the present invention adopts a two-phase non-overlapping clock, whose output controls the offset elimination circuit clock in the bandgap reference amplifier A1.

[0056] Assume that all devices have a propagation delay T d When the oscillator signal changes from low to high, that is, CLK is high, the voltage at point J is high, that is, the voltage at the input of NOR2 is high, then the output point H is low. is low level, CK2 is high level. At the same time, point K is delayed by T compared to point H. dOutput high level, then CK1 Delay T d After that, it is high level. When the oscillator signal changes from low to high, that is, CLK is low and the voltage at point F is high, then the output point K is low and CK1 is low. At the same time, point K outputs a high level after a delay of Td compared to point H. Delayed by T compared to CK1 d After that, CK2 is high level and CK2 is low level. In order to make the output signal have a longer rise time, two capacitors are added at K and H respectively to further increase the conversion time.

[0057] like Figure 6 As shown, the offset cancellation circuit includes: switch S0, switch S1, switch S2, switch S3, switch S4, capacitor C4, capacitor C5, amplifier Gm1, amplifier Gm2, amplifier R1, amplifier R2 and offset voltage Vos1; switch S0, offset voltage Vos1 and the non-inverting input terminal of amplifier Gm1 are connected in sequence; switch S1 is simultaneously connected to the non-inverting input terminal and the inverting input terminal of amplifier Gm1; the output terminal of amplifier Gm1 is connected to the input terminal of amplifier R1; the output of amplifier R1 is simultaneously connected to the switch S2, switch S3 and switch S4, and receives the feedback signal output by amplifier R2; the inverting input terminal of amplifier Gm2 is simultaneously connected to switch S3 and capacitor C4, the non-inverting input terminal is simultaneously connected to switch S4 and capacitor C5, and the output terminal is connected to the input terminal of amplifier R2.

[0058] The circuit "measures" the offset by setting the single-ended input to zero, and stores the offset on the capacitor at the output end, thereby canceling the effect of the input offset at the output end. This process requires a dedicated offset cancellation cycle to isolate the actual input state, that is, the input of the BG main amplifier circuit is invalid during this cycle. In addition, in order to avoid introducing capacitance in the signal path and causing problems such as slow circuit response speed, the present invention introduces capacitance into the feedback path.

[0059] The offset elimination is characterized in that the states of switch S0 and switch S2 are the same, the states of switch S1, switch S3 and switch S4 are the same, and the states of switch S0 and switch S1 are complementary. The oscillator and the two-phase non-overlapping clock circuit work cyclically according to the working cycle T, and the control instructions of the five switches are respectively executed in the two stages of each working cycle T: switch S0 and switch S2 are closed, switch S1, switch S3 and switch S4 are opened; switch S0 and switch S2 are opened, switch S1, switch S3 and switch S4 are closed.

[0060] When CK1=CK2=1, Switches S0 and S2 are opened, and switches S1, S3, and S4 are closed. Points X and Y are disconnected, and capacitors C4 and C5 in the feedback loop are connected respectively. Capacitor C4 begins to store the output voltage V of the bandgap reference main amplifier A1 during this cycle. OUT1 , capacitor C5 starts to store the output voltage V of the bandgap reference main amplifier A1 in the previous cycle OUT0 , at this time the bandgap reference main amplifier A1 is in an abnormal working state. When it reaches the steady state, there is:

[0061] V OUT1 =G m1 R1·V OS1 +G m2 R2·(V OUT0 -V OUT1 )

[0062]

[0063] V OUT1 Follow V OUT0 That is, the output of the bandgap reference main amplifier A1 in this cycle is the output of the previous cycle.

[0064] Within the offset cancellation adjustment range, V OUT1 It will reach steady state under the negative feedback regulation of amplifier Gm2 and R2, and the relationship is as follows:

[0065]

[0066] G m2 R2>>1

[0067] Then the input offset voltage V OS1 Stored on capacitors C4 and C5, when the input offset voltage remains unchanged V OS unchanged, then V OUT1 -V OUT0 The difference is a constant value.

[0068] When CK1=CK2=0, Switch S0 and switch S2 are closed, and switches S1, S3 and S4 are open. At this time, the offset storage circuit is closed: the bandgap reference main amplifier A1 works normally. The amplifier Gm2 and R2 in the feedback loop outputs a cancellation voltage (VOUT1-VOUT0) Gm2R2 through the voltage difference VOUT1-VOUT0 stored by C4 and C5 to eliminate the influence of the input offset voltage VOS1 of the bandgap reference main amplifier A1. At this time, the differential voltage at the input of the bandgap reference main amplifier A1 is VIN2.

[0069] When reaching steady state:

[0070] VOUT2 =G m1 R1·(V IN2 +V OS1 )+G m2 R2·(V OUT0 -V OUT1 )

[0071] When CK1=CK2=1, At this time, the offset storage circuit is started, and the bandgap reference main amplifier A1 is in an abnormal working state. At this time, the voltage is redistributed.

[0072]

[0073] If V OUT2 >V OUT0 , then V OUT3 value increases; if V OUT2 <V OUT0 , then V OUT3 The value decreases.

[0074] V OUT4 =V OUT3 -V OUT1 +V OUT0

[0075] Therefore, when the steady state is reached,

[0076]

[0077] When CK1=CK2=0, At this time, the offset storage circuit is turned off and the BG main amplifier works normally. The differential voltage at the input of the bandgap reference main amplifier A1 is VIN4, so:

[0078] V OUT5 =G m1 R1·(V IN4 +V OS1 )+G m2 R2·(V OUT4 -V OUT3 )

[0079] Then the next cycle repeats the above two moments. When the offset is eliminated and reaches the steady state, there is:

[0080] V OUT(N+1) =V OUT(N)

[0081]

[0082] At this time, the total offset voltage of the bandgap reference main amplifier A1 equivalent to the input terminal of A1 is:

[0083]

[0084] In summary, the offset circuit can reduce the A1 equivalent total offset voltage of the bandgap reference, thereby improving the accuracy of the bandgap reference output voltage.

[0085] Obviously, those skilled in the art can make various modifications and changes to the embodiments of the present application without departing from the spirit and scope of the present application. In this way, if these modifications and changes are within the scope of the claims of the present application and their equivalents, the present application is also intended to cover these modifications and changes. The word "comprising" does not exclude the presence of other elements or steps not listed in the claims. The simple fact that certain measures are recorded in mutually different dependent claims does not indicate that the combination of these measures cannot be used to profit. Any figure mark in the claims should not be considered to limit the scope.

Claims

1. A high-precision bandgap reference circuit with offset cancellation function, characterized in that: include: Bandgap reference amplifier A1; the bandgap reference amplifier A1 comprises a square wave generator circuit, a clock circuit and an offset elimination circuit; the square wave generator circuit, the clock circuit and the offset elimination circuit are connected in sequence; the square wave generator circuit generates a clock signal and transmits it to the clock circuit; the clock circuit comprises a first NOR gate and a second NOR gate, and capacitors are respectively added to the output ends of the first NOR gate and the second NOR gate; a capacitor is added in the feedback path of the offset elimination circuit, and the capacitor is used to store the offset.

2. The high-precision bandgap reference circuit with offset elimination function according to claim 1, characterized in that: Also includes: Start circuit; The startup circuit includes a comparator A2; a compensation voltage V is applied to the non-inverting input terminal of the comparator A2. COMP The output terminal of the comparator A2 outputs a start voltage V in response to the comparison result between the non-inverting input terminal and the inverting input terminal of the comparator A2. start ; Among them, when V COMP >V 反相输入端 Time V star t outputs high level, otherwise it outputs low level.

3. The high-precision bandgap reference circuit with offset elimination function according to claim 2, characterized in that: include: MOS tube M2, MOS tube M3, MOS tube M4, MOS tube M5, resistor R1, resistor R2, resistor R3, resistor R4, transistor Q1, transistor Q2 and transistor Q3; the in-phase input end of the bandgap reference amplifier A1 is simultaneously connected to one end of the resistor R3 and the emitter of the transistor Q2, and the base of the transistor Q2 is connected to the collector and grounded; the inverting input end of the bandgap reference amplifier A1 is simultaneously connected to one end of the resistor R2 and one end of the resistor R1, the other end of the resistor R1 is connected to the emitter of the transistor Q1, and the base of the transistor Q1 is connected to the collector and grounded; the output end of the bandgap reference amplifier A1 is simultaneously connected to the start-up circuit, the M The gate of the MOS tube M4 and the gate of the MOS tube M5; the source of the MOS tube M4 is simultaneously connected to the startup circuit, the other end of the resistor R3 and the other end of the resistor R2; one end of the resistor R4 is connected to the emitter of the triode Q3, and the other end is connected to the source of the MOS tube M5, the base of the triode Q3 is connected to the collector and grounded; the gate of the MOS tube M3 is connected to the gate of the MOS tube M2, and the source of the MOS tube M3 is connected to the drain of the MOS tube M5; the startup circuit, the drain of the MOS tube M2 and the drain of the MOS tube M3 are all connected to VCC; and the gate of the MOS tube M2 and the gate of the MOS tube M3 are both applied with a control voltage V B1 .

4. The high-precision bandgap reference circuit with offset elimination function according to claim 3, characterized in that: The startup circuit also includes: a MOS tube M1; the gate of the MOS tube M1 is connected to the output end of the comparator A2, the drain is connected to VCC, and the source is simultaneously connected to the gate of the MOS tube M4, the gate of the MOS tube M5 and the output end of the bandgap reference amplifier A1; the inverting input end of the comparator A2 is simultaneously connected to the source of the MOS tube M4, the resistor R2 and the resistor R3, and the control voltage V is applied to the in-phase input end. comp .

5. The high-precision bandgap reference circuit with offset elimination function according to claim 4, characterized in that: The square wave generator circuit includes: MOS tube M6, MOS tube M7, MOS tube M8, MOS tube M9, MOS tube M10, MOS tube M11, MOS tube M12, resistor R5, resistor R6, resistor R7, current source, capacitor C1 and a first NOT gate; the input end of the first NOT gate is simultaneously connected to the source of the MOS tube M6 and the drain of the MOS tube M9, and the output end is simultaneously connected to the gate of the MOS tube M7 and the gate of the MOS tube M8; the source of the MOS tube M7 is connected to the gate of the MOS tube M6, and the drain is connected to one end of the resistor R5; the other end of the resistor R5 The MOS tube M8 is connected to one end of the resistor R6 and R7 at the same time; the source of the MOS tube M8 is grounded, and the drain is connected to the other end of the resistor R6; the gate of the MOS tube M9 is connected to the capacitor C1 and the other end of the resistor R7 at the same time, and the source is connected to the drain of the MOS tube M10 and the source of the MOS tube M12 at the same time; the gate of the MOS tube M10 is connected to the drain of the MOS tube M11 and the drain of the MOS tube M12 at the same time, and the source of the MOS tube M10 is grounded; the current source is connected to the drain of the MOS tube M6, the gate of the MOS tube M11 and the gate of the MOS tube M12 at the same time.

6. The high-precision bandgap reference circuit with offset elimination function according to claim 4, characterized in that: The clock circuit includes: a capacitor C2, a capacitor C3, a second NOT gate, a third NOT gate, a fourth NOT gate, a fifth NOT gate, a sixth NOT gate, a seventh NOT gate, a first NOR gate and a second NOR gate; the output end of the second NOR gate is simultaneously connected to the first input end of the first NOR gate and the input end of the third NOR gate; the output end of the third NOR gate is connected to the second input end of the second NOR gate; the second input end of the first NOR gate is simultaneously connected to the output end of the second NOR gate and the input end of the sixth NOR gate, and is grounded through the capacitor C3; the output end of the first NOR gate is simultaneously connected to the first input end of the second NOR gate and the input end of the fourth NOR gate, and is grounded through the capacitor C2; the output end of the fourth NOR gate outputs a second level signal, and outputs a first level signal via the output end of the fifth NOR gate; the output end of the sixth NOR gate outputs a fourth level signal, and outputs a third level signal via the output end of the seventh NOR gate.

7. The high-precision bandgap reference circuit with offset cancellation function according to claim 6, characterized in that: The offset cancellation circuit includes: a switch S0, a switch S1, a switch S2, a switch S3, a switch S4, a capacitor C4, a capacitor C5, an amplifier Gm1, an amplifier Gm2, an amplifier R1, an amplifier R2 and an offset voltage Vos1; the switch S0, the offset voltage Vos1 and the non-inverting input terminal of the amplifier Gm1 are connected in sequence; the switch S1 is simultaneously connected to the non-inverting input terminal and the inverting input terminal of the amplifier Gm1; the output terminal of the amplifier Gm1 is connected to the input terminal of the amplifier R1; the output terminal of the amplifier R1 is simultaneously connected to the switch S2, the switch S3 and the switch S4, and receives a feedback signal from the output terminal of the amplifier R2; the inverting input terminal of the amplifier Gm2 is simultaneously connected to the switch S3 and the capacitor C4, the non-inverting input terminal is simultaneously connected to the switch S4 and the capacitor C5, and the output terminal is connected to the input terminal of the amplifier R2.

8. The high-precision bandgap reference circuit with offset elimination function according to claim 3, characterized in that: The size ratio of the transistors Q1 , Q2 and Q3 is 7:1:1; the resistance value of the resistor R2 is the same as the resistance value of the resistor R3 .

9. The high-precision bandgap reference circuit with offset elimination function according to claim 7, characterized in that: The switch S0 and the switch S2 are in the same state; the switches S1, S3 and the switch S4 are in the same state, and the state of the switch S0 is complementary to the state of the switch S1.

10. The high-precision bandgap reference circuit with offset elimination function according to claim 7, characterized in that: The switch S0 responds to the third level signal; the switch S1 responds to the first level signal; the switch S2 responds to the second level signal; the switch S3 and the switch S4 respond to the fourth level signal.

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