SRAM compiler design method and device capable of resisting single event latch-up effect

Abstract

The invention relates to a method and a device for designing an SRAM (Static Random Access Memory) compiler capable of resisting a single event latch-up effect. The method comprises the following steps: performing device-level single-particle latch-up effect simulation on a bottom-layer sub-module of the SRAM compiler; formulating a reinforcement design rule of the bottom layer sub-module according to a simulation result; optimizing and improving the bottom layer sub-module according to a reinforcement design rule, and making the bottom layer sub-module into an anti-latch reinforcement database; acquiring a splicing rule of the anti-latch reinforced database in the memories with different capacities, and describing the splicing rule by utilizing a high-level programming language; and calling an underlying sub-module of the latch-up reinforced database by utilizing a high-level programming language so as to generate memories with different capacities. According to the method, in the initial stage of design of the SRAM compiler, the single-particle latch-up resisting reinforcement is carried out on the bottom layer submodule, so that the characteristics of low cost, short period, high efficiency and flexible configuration of the SRAM compiler are ensured, and a memory generated by the SRAM compiler has the performance of resisting the single-particle latch-up effect.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit chip design, and in particular to a method and device for designing an SRAM compiler that is resistant to single-particle latch-up effects. Background Art

[0002] When SRAM memory works in harsh environments such as electromagnetic and outer space, the memory may experience single-particle latch-up, resulting in increased local current and data errors. Therefore, when designing SRAM memory for use in these harsh environments, it is necessary to perform single-particle latch-up resistance design on this type of memory.

[0003] There are two methods for designing SRAM memory: one is the full-custom design method, but this method has a long design cycle and high cost; the other is the design method of automatically generating memory using the SRAM compiler. This method has low cost, short cycle, high efficiency, and flexible configuration, making it the best custom design method for embedded memory. The SRAM compiler design method is: first design the underlying submodule of the compiler and make it into a basic database; then study the splicing rules of the basic database in memories of different capacities, and use high-level programming languages ​​to describe the splicing rules; finally use high-level programming languages ​​to call the underlying submodules of the basic database to generate memories of different capacities.

[0004] The single-particle latch-up effect is caused by high-energy particles incident on the internal parasitic PNPN structure in the CMOS integrated circuit, and its effect mechanism is well known in the field. Document 1 (publication number CN103886158A document) discloses a standard cell design method that is resistant to single-particle latch-up effects. Through certain reasonable reinforcement measures, the standard cell's anti-single-particle latch-up effect reinforcement design is achieved. Similar to the CMOS standard cell circuit, the underlying submodule in the SRAM compiler also has a parasitic PNPN structure. If reasonable reinforcement measures are not adopted, the memory generated by the SRAM compiler will also be at risk of single-particle latch-up effects. Summary of the invention

[0005] Based on this, it is necessary to provide a SRAM compiler design method and device that is resistant to single-particle latch-up effects in order to address the above technical issues.

[0006] A method for designing an SRAM compiler resistant to single-particle latch-up effects, the method comprising: Perform device-level single-event latch-up simulation on low-level submodules of the SRAM compiler.

[0007] According to the simulation results, the reinforcement design rules of the bottom-level sub-modules are formulated.

[0008] The underlying submodules are optimized and improved according to the reinforcement design rules and made into an anti-latch reinforcement database.

[0009] The splicing rules of anti-latch hardening databases in memories of different capacities are obtained and described in a high-level programming language.

[0010] The bottom submodule of the anti-latching hardening database is called by a high-level programming language to generate an anti-latching hardening SRAM memory of corresponding capacity.

[0011] In one embodiment, a device-level single event latch-up simulation is performed on a low-level submodule of an SRAM compiler, including: Get the process parameter information of the MOS tube used by the underlying submodule of the SRAM compiler.

[0012] According to the process parameter information, the MOS tube used in the bottom sub-module is modeled at the device level to obtain the MOS tube model.

[0013] A first distance between the MOS tube and the adjacent well contact and a second distance between the MOS tube and the adjacent well are determined according to the MOS tube model.

[0014] The first distance and the second distance are adjusted to perform device-level single-particle latch effect simulation on the MOS tube model.

[0015] Obtain the maximum and minimum critical distances for determining whether a single-particle latch-up effect occurs in the MOS tube model.

[0016] In one embodiment, the maximum value of the first distance between the MOS transistor and the adjacent well contact is the maximum critical distance, and the minimum value of the distance between the MOS transistor and the adjacent well is the minimum critical distance.

[0017] In one embodiment, the splicing rules include: the names, call times and call locations of different underlying sub-modules in different capacity memories.

[0018] A SRAM compiler design device for resisting single-particle latch effect, the device comprising: The device-level single-particle latch-up effect simulation module is used to perform device-level single-particle latch-up effect simulation on the underlying submodules of the SRAM compiler.

[0019] The reinforcement design rule determination module is used to formulate the reinforcement design rules of the underlying sub-modules according to the simulation results.

[0020] The anti-latching reinforcement database production module is used to optimize and improve the underlying sub-modules according to the reinforcement design rules, and produce them into an anti-latching reinforcement database; obtain the splicing rules of the anti-latching reinforcement database in storage devices of different capacities, and use a high-level programming language to describe the splicing rules.

[0021] The anti-latch reinforcement SRAM memory design module is used to call the bottom submodule of the anti-latch reinforcement database by using a high-level programming language to generate an anti-latch reinforcement SRAM memory of corresponding capacity.

[0022] In one of the embodiments, the device-level single-particle latch-up effect simulation module is also used to obtain process parameter information of the MOS tube used by the bottom sub-module of the SRAM compiler; perform device-level modeling on the MOS tube used by the bottom sub-module according to the process parameter information to obtain a MOS tube model; determine a first distance between the MOS tube and the adjacent well contact and a second distance between the MOS tube and the adjacent well according to the MOS tube model; adjust the first distance and the second distance to perform device-level single-particle latch-up effect simulation on the MOS tube model; and obtain a maximum value and a minimum value of a critical distance for determining whether the MOS tube model has a single-particle latch-up effect.

[0023] In one embodiment, the maximum value of the first distance between the MOS transistor and the adjacent well contact is the maximum critical distance, and the minimum value of the distance between the MOS transistor and the adjacent well is the minimum critical distance.

[0024] In one of the embodiments, the splicing rules in the anti-latch reinforcement database production module include: the names, call times and call locations of different underlying sub-modules under different capacity memories.

[0025] The above-mentioned SRAM compiler design method and device for resisting single-particle latching effect, the method includes: performing device-level single-particle latching effect simulation on the bottom-level submodule of the SRAM compiler; formulating reinforcement design rules for the bottom-level submodule according to the simulation results; optimizing and improving the bottom-level submodule according to the reinforcement design rules, and making it into an anti-latch reinforcement database; obtaining the splicing rules of the anti-latch reinforcement database in memories of different capacities, and describing the splicing rules using a high-level programming language; using a high-level programming language to call the bottom-level submodule of the anti-latch reinforcement database, thereby generating memories of different capacities. This method performs anti-single-particle latching reinforcement on the bottom-level submodule in the early stage of SRAM compiler design, which not only ensures the characteristics of the SRAM compiler with low cost, short cycle, high efficiency, and flexible configuration, but also enables the memory generated by the SRAM compiler to have the performance of resisting single-particle latching effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 An application scenario diagram of a method for designing an SRAM compiler that resists single-particle latch-up effect in one embodiment; Figure 2 A schematic diagram of C module composition with different capacities in another embodiment; Figure 3A schematic diagram of a MOS tube model in another embodiment; Figure 4 A structural block diagram of a SRAM compiler design device that is resistant to single event latch-up effects in one embodiment. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0028] In one embodiment, Figure 1 As shown, a method for designing an SRAM compiler resistant to single-particle latch-up effect is provided, the method comprising the following steps: Step 100: Perform device-level single-event latch-up simulation on the underlying submodule of the SRAM compiler.

[0029] Specifically, a device-level single-particle latch-up effect simulation is performed on the underlying submodule of the SRAM compiler to obtain the minimum requirement for avoiding the single-particle latch-up effect from occurring in the submodule.

[0030] Step 102: Formulate reinforcement design rules for the bottom submodules based on the simulation results.

[0031] Specifically, the simulation results formulate the anti-latch reinforcement design rules of the bottom submodule. The reinforcement design rules are described as follows: the maximum distance between the MOS tube and the adjacent well contact is the critical distance L1 max , the minimum distance between the MOS tube and the adjacent well is the critical distance L2 min .

[0032] Step 104: Optimize and improve the underlying submodules according to the reinforcement design rules, and make them into an anti-latch reinforcement database.

[0033] Specifically, the bottom-level sub-modules are optimized and improved one by one until all MOS tubes in all bottom-level sub-modules meet the above reinforcement design rules.

[0034] In a specific embodiment, if the distance between the MOS transistor A and the adjacent well is less than the critical distance L2 min , then it is necessary to translate the MOS tube A as a whole in a direction away from the adjacent well, so that the distance between the MOS tube A and the adjacent well is greater than or equal to the critical distance L2 min .

[0035] If the distance between MOS tube B and L1 max If there is no well contact within the MOS tube B, the distance L1 max At least one well contact is added within.

[0036] Step 106: Obtain the splicing rules of the anti-latch reinforcement database in the storage devices of different capacities, and describe the splicing rules using a high-level programming language.

[0037] Specifically, different capacity memories are composed of different types and numbers of modules, but a specific capacity memory must be composed of a specific type and number of modules. The anti-latch hardening database needs to include bottom-level submodules that can be spliced ​​into the full capacity memory. The anti-latch bottom-level submodules are spliced ​​into the sub-bottom-level modules, and the lower-level modules are spliced ​​into the upper-level modules step by step until the top-level module, which is the anti-latch memory. The specific splicing rules are described by high-level programming languages.

[0038] like Figure 2 As shown, in a specific embodiment, the C module with a memory capacity of S1 is composed of module A and module B; the C module with a memory capacity of S2 is composed of module A, module A and module B; the C module with a memory capacity of S3 is composed of module A, module A, module A and module B.

[0039] In a high-level programming language, you need to define the following: When the memory capacity is S2, the memory is composed of modules spliced ​​together step by step, where module C calls module A and module B. The coordinates of the first module A are (xa1, ya1), the coordinates of the second module A are (xa2, ya2), and the coordinates of module B are (xb1, yb1). Similarly, except for the anti-latch bottom submodule, each module of different capacity memory needs to be defined in this way.

[0040] Step 108: Use a high-level programming language to call the bottom-level submodule of the anti-latching hardening database to generate an anti-latching hardening SRAM memory of corresponding capacity.

[0041] Specifically, when it is necessary to generate an anti-latching reinforced SRAM memory with a capacity of S2, the high-level programming language will call the lower-level modules step by step according to the above-mentioned splicing rules. The lowest-level module is the underlying sub-module of the anti-latching reinforced database, thereby generating an anti-latching reinforced memory of the corresponding capacity.

[0042] In a specific embodiment, for ease of understanding, assume that different types of underlying submodules are different types of "building blocks", and the anti-latching hardened SRAM memory is a "building block house". Then, the anti-latching hardened database is all types of "building blocks", the high-level programming language is the "rule description" of the building blocks to assemble the building block house, and the anti-latching hardened SRAM memories of different capacities are "building block houses of different sizes".

[0043] The anti-latch hardened SRAM compiler designed by this method can generate anti-latch hardened SRAM memories of different capacities, greatly reducing the research and development cost of anti-latch hardened memories. This design method is low-cost and easy to implement, and can generate anti-latch hardened SRAM memories of different capacities, greatly reducing the research and development cost of anti-latch hardened memories.

[0044] In the above-mentioned SRAM compiler design method for resisting single-particle latch effects, the method includes: performing device-level single-particle latch effect simulation on the underlying submodule of the SRAM compiler; formulating reinforcement design rules for the underlying submodule according to the simulation results; optimizing and improving the underlying submodule according to the reinforcement design rules, and making it into an anti-latch reinforcement database; obtaining the splicing rules of the anti-latch reinforcement database in memories of different capacities, and describing the splicing rules using a high-level programming language; using a high-level programming language to call the underlying submodule of the anti-latch reinforcement database, thereby generating memories of different capacities. This method performs anti-single-particle latch reinforcement on the underlying submodule in the early stage of SRAM compiler design, which not only ensures the characteristics of the SRAM compiler with low cost, short cycle, high efficiency, and flexible configuration, but also enables the memory generated by the SRAM compiler to have the performance of resisting single-particle latch effects.

[0045] In one embodiment, step 100 includes: obtaining process parameter information of a MOS tube used by a bottom submodule of an SRAM compiler; performing device-level modeling on the MOS tube used by the bottom submodule according to the process parameter information to obtain a MOS tube model; determining a first distance between the MOS tube and an adjacent well contact and a second distance between the MOS tube and an adjacent well according to the MOS tube model; adjusting the first distance and the second distance to perform device-level single-particle latch effect simulation on the MOS tube model; and obtaining a maximum value and a minimum value of a critical distance for determining whether a single-particle latch effect occurs in the MOS tube model.

[0046] Specifically, the process parameter information of the MOS tube used in the bottom submodule is obtained (the process parameter information of the MOS tube includes parameters such as model flag parameters (MODEL FLAG PARAMETERS), general model parameters (GENRAL MODEL PARAMETERS), and DC parameters (DC PARAMETERS). The model flag parameters define the minimum and maximum values ​​of the gate length of the MOS tube, the general model parameters define the gate oxide thickness, and the DC parameters define the polysilicon doping concentration and junction depth of the gate). According to these process parameter information, the MOS tube used in the bottom submodule is modeled at the device level. The schematic diagram of the MOS model is shown in the figure. Figure 3 As shown, Figure 3The figure also shows the distance L1 between the MOS tube (PMOS tube or NMOS tube) and the adjacent well contact, and the distance L2 between the MOS tube and the adjacent well. According to relevant literature, the single-particle latch-up effect can be reduced by reducing the distance L1 and increasing the distance L2. The distances L1 and L2 between the MOS tube and the adjacent well contact are adjusted, and the device-level single-particle latch-up effect simulation is performed on the established model.

[0047] Obtain the critical distance L1 of whether the MOS tube model has a single-particle latch effect max and critical distance L2 min .

[0048] In one embodiment, the maximum value of the first distance between the MOS transistor and the adjacent well contact is the maximum critical distance, and the minimum value of the distance between the MOS transistor and the adjacent well is the minimum critical distance.

[0049] In one embodiment, the splicing rules include: the names, call times and call locations of different underlying sub-modules in different capacity memories.

[0050] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0051] In one embodiment, Figure 4 As shown, a SRAM compiler design device for resisting single-particle latching effect is provided, comprising: a device-level single-particle latching effect simulation module, a reinforcement design rule determination module, an anti-latch reinforcement database preparation module and an anti-latch reinforcement SRAM memory design module, wherein: The device-level single-particle latch-up effect simulation module is used to perform device-level single-particle latch-up effect simulation on the underlying submodules of the SRAM compiler.

[0052] The reinforcement design rule determination module is used to formulate the reinforcement design rules of the underlying sub-modules according to the simulation results.

[0053] The anti-latching reinforcement database production module is used to optimize and improve the underlying sub-modules according to the reinforcement design rules, and produce them into an anti-latching reinforcement database; obtain the splicing rules of the anti-latching reinforcement database in storage devices of different capacities, and use a high-level programming language to describe the splicing rules.

[0054] The anti-latch reinforcement SRAM memory design module is used to call the bottom submodule of the anti-latch reinforcement database by using a high-level programming language to generate an anti-latch reinforcement SRAM memory of corresponding capacity.

[0055] In one of the embodiments, the device-level single-particle latch-up effect simulation module is also used to obtain process parameter information of the MOS tube used by the bottom sub-module of the SRAM compiler; perform device-level modeling on the MOS tube used by the bottom sub-module according to the process parameter information to obtain a MOS tube model; determine a first distance between the MOS tube and the adjacent well contact and a second distance between the MOS tube and the adjacent well according to the MOS tube model; adjust the first distance and the second distance to perform device-level single-particle latch-up effect simulation on the MOS tube model; and obtain a maximum value and a minimum value of a critical distance for determining whether the MOS tube model has a single-particle latch-up effect.

[0056] In one embodiment, the maximum value of the first distance between the MOS transistor and the adjacent well contact is the maximum critical distance, and the minimum value of the distance between the MOS transistor and the adjacent well is the minimum critical distance.

[0057] In one of the embodiments, the splicing rules in the anti-latch reinforcement database production module include: the names, call times and call locations of different underlying sub-modules under different capacity memories.

[0058] The specific definition of the SRAM compiler design device that resists the single-particle latch-up effect can be found in the definition of the SRAM compiler design method that resists the single-particle latch-up effect in the above text, and will not be repeated here. Each module in the above-mentioned SRAM compiler design device that resists the single-particle latch-up effect can be implemented in whole or in part by software, hardware, and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0059] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0060] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A method for designing an SRAM compiler resistant to single event latch-up effect, characterized in that: The method comprises: Perform device-level single-event latch-up simulation on the underlying submodules of the SRAM compiler; Formulate reinforcement design rules for underlying submodules based on simulation results; Optimizing and improving the bottom layer submodules according to the reinforcement design rules and making them into an anti-latch reinforcement database; Obtaining a splicing rule of anti-latch hardening databases in memories of different capacities, and describing the splicing rule in a high-level programming language; The bottom submodule of the anti-latch reinforcement database is called by using a high-level programming language to generate an anti-latch reinforcement SRAM memory of corresponding capacity.

2. The method for designing a SRAM compiler resistant to single event latch-up effect according to claim 1, characterized in that: Device-level single-event latch-up simulation of low-level submodules of the SRAM compiler, including: Get the process parameter information of the MOS tube used by the bottom submodule of the SRAM compiler; According to the process parameter information, device-level modeling is performed on the MOS tube used by the bottom submodule to obtain a MOS tube model; Determine a first distance between the MOS tube and the adjacent well contact and a second distance between the MOS tube and the adjacent well according to the MOS tube model; Adjusting the first distance and the second distance to perform device-level single-particle latch effect simulation on the MOS tube model; The maximum value and the minimum value of the critical distance for determining whether the single-particle latch effect occurs in the MOS tube model are obtained.

3. The method for designing a SRAM compiler resistant to single event latch-up effect according to claim 2, characterized in that: The maximum value of the first distance between the MOS tube and the adjacent well contact is the maximum critical distance, and the minimum value of the distance between the MOS tube and the adjacent well is the minimum critical distance.

4. The method for designing a SRAM compiler resistant to single event latch-up effect according to claim 1, wherein: The splicing rules include: the names, calling times and calling positions of different bottom-level submodules under different capacity memories.

5. A SRAM compiler design device resistant to single event latch-up effect, characterized in that: The device comprises: Device-level single-particle latch-up effect simulation module, used to perform device-level single-particle latch-up effect simulation on the underlying submodules of the SRAM compiler; A reinforcement design rule determination module is used to formulate reinforcement design rules for underlying submodules based on simulation results; an anti-latching reinforcement database making module, used to optimize and improve the bottom-level submodules according to the reinforcement design rules, and make them into an anti-latching reinforcement database; obtain the splicing rules of the anti-latching reinforcement databases in the storage devices of different capacities, and describe the splicing rules in a high-level programming language; The anti-latching reinforced SRAM memory design module is used to call the bottom submodule of the anti-latching reinforced database by using a high-level programming language to generate an anti-latching reinforced SRAM memory of corresponding capacity.

6. The SRAM compiler design device for resisting single event latch-up effect according to claim 5, characterized in that: The device-level single-particle latch-up effect simulation module is also used to obtain process parameter information of the MOS tube used by the bottom submodule of the SRAM compiler; perform device-level modeling on the MOS tube used by the bottom submodule according to the process parameter information to obtain a MOS tube model; determine a first distance between the MOS tube and the adjacent well contact and a second distance between the MOS tube and the adjacent well according to the MOS tube model; adjust the first distance and the second distance to perform device-level single-particle latch-up effect simulation on the MOS tube model; and obtain a maximum critical distance and a minimum critical distance for determining whether the MOS tube model has a single-particle latch-up effect.

7. The SRAM compiler design device for resisting single event latch-up effect according to claim 6, characterized in that: The maximum value of the first distance between the MOS tube and the adjacent well contact is the maximum critical distance, and the minimum value of the distance between the MOS tube and the adjacent well is the minimum critical distance.

8. The SRAM compiler design device for resisting single event latch-up effect according to claim 5, characterized in that: The splicing rules in the anti-latch reinforcement database production module include: the names, call times and call locations of different underlying sub-modules under different capacity memories.

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