Triple exposure two-end wire net wiring method and system based on state decomposition

Abstract

The invention provides a triple exposure two-end wire net wiring method and system based on state decomposition, and relates to the technical field of circuit wiring, and the method comprises the steps: obtaining wiring data; constructing a wiring diagram structure according to the wiring data; performing state decomposition on the wiring diagram structure to obtain a plurality of independent connecting edges; calculating the weight of each connecting edge; and based on the weight of each connecting edge, carrying out wiring search on the two-end wire nets, and determining a final wiring scheme. According to the method, wiring and mask states are combined, connection edge decomposition, weight calculation and dynamic search strategies are adopted, the wiring complexity can be effectively reduced, the wiring accuracy and the wiring passing rate can be improved, distribution of multiple layers of masks is fully considered in the wiring process, conflicts and process violation are reduced, the method is suitable for wiring requirements of high-density and complex circuits, and the wiring efficiency is improved. And the wiring efficiency is obviously improved.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit wiring, and in particular to a triple-exposure two-end wire mesh wiring method and system based on state decomposition. Background Art

[0002] As the feature size of integrated circuits continues to shrink and the density of layout patterns continues to increase, the multiple exposure lithography process has become a key technology to further improve the success rate of chip manufacturing. The multiple exposure lithography process is to decompose the layout pattern into multiple different mask plates, and finally form a complete silicon wafer pattern through multiple iterative processes of exposure and etching. The minimum spacing between layout patterns on different mask plates can be smaller than the minimum spacing between layout patterns on the same mask plate, thus putting forward higher and more complex requirements for integrated circuit design.

[0003] In the design of VLSI chips, wiring is the most time-consuming and important link, which has an extremely important impact on the performance, power consumption and yield of the chip. In order to meet the multiple exposure lithography process, the wiring needs to be distributed on different masks and meet the minimum distance requirements for layout patterns on different masks or the same mask.

[0004] However, with the growth of design scale and complexity, triple exposure technology has gradually become a new design trend, but the existing design methods mainly focus on double exposure technology. Usually, mask allocation is not considered during the wiring process. Instead, the layout is decomposed after the wiring is completed to determine the mask for wiring, which easily leads to a low routing rate. Summary of the invention

[0005] In order to solve the technical problem that as the design scale and complexity grow, triple exposure technology has gradually become a new design trend in the prior art, but the existing design methods mainly focus on double exposure technology, and usually do not consider mask allocation during the wiring process, but perform layout decomposition after the wiring is completed to determine the mask for wiring, which easily leads to a low wiring pass rate. The present invention provides a triple exposure two-end wire mesh wiring method and system based on state decomposition.

[0006] The technical solution provided by the embodiment of the present invention is as follows:

[0007] First aspect

[0008] An embodiment of the present invention provides a triple exposure two-end wire mesh wiring method based on state decomposition, comprising:

[0009] S1: Get wiring data;

[0010] S2: construct a wiring diagram structure according to the wiring data;

[0011] S3: Decompose the wiring diagram structure into states to obtain multiple independent connection edges;

[0012] S4: Calculate the weight of each connecting edge;

[0013] S5: Based on the weight of each connection edge, perform routing search on the two end nets to determine the final routing solution.

[0014] Second aspect

[0015] An embodiment of the present invention provides a triple exposure two-end wire mesh wiring system based on state decomposition, comprising:

[0016] processor;

[0017] A memory stores computer-readable instructions, and when the computer-readable instructions are executed by a processor, the triple-exposure two-end wire mesh wiring method based on state decomposition as described in the first aspect is implemented.

[0018] The third aspect

[0019] An embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, the state decomposition-based triple-exposure two-terminal network wiring method as described in the first aspect is implemented.

[0020] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0021] In the present invention, state decomposition is performed according to different mask conditions, which avoids conflicts between different mask layers, significantly improves the routing rate, and effectively reduces the probability of routing failure and retry. By introducing triple exposure technology, the wiring structure can be decomposed into different mask layers, which significantly improves the accuracy and resolution of wiring. By constructing a wiring diagram structure, path optimization can be flexibly performed in multi-layer wiring, making the wiring more comprehensive and accurate. By calculating the weights of the connecting edges, the possible variation risks of the wiring path in the manufacturing process can be evaluated in advance, and high-risk paths can be avoided during the wiring search process, effectively improving the manufacturing yield of the wiring design, so that decisions that are more in line with the design and process requirements can be made in the optimization. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1A schematic flow chart of a triple exposure two-end wire mesh wiring method based on state decomposition provided by an embodiment of the present invention;

[0024] Figure 2 A schematic diagram of the structure of an initial wiring diagram provided by an embodiment of the present invention;

[0025] Figure 3 A schematic diagram of the decomposition of the wiring connection edge state provided by an embodiment of the present invention;

[0026] Figure 4 A schematic diagram of the wiring diagram structure after state decomposition provided by an embodiment of the present invention;

[0027] Figure 5 A schematic diagram of a wiring result of a wiring diagram structure after state decomposition provided by an embodiment of the present invention;

[0028] Figure 6 A schematic diagram of a wiring result of a simple wire net provided in an embodiment of the present invention;

[0029] Figure 7 A schematic structural diagram of a triple exposure two-terminal wire mesh wiring system based on state decomposition provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The technical solution of the present invention is described below in conjunction with the accompanying drawings.

[0031] In the embodiments of the present invention, words such as "exemplarily" and "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of the word "example" is intended to present the concept in a specific way. In addition, in the embodiments of the present invention, the meaning expressed by "and / or" can be both, or it can be either of the two.

[0032] In order to make the technical problems, technical solutions and advantages to be solved by the present invention more clear, a detailed description will be given below with reference to the accompanying drawings and specific embodiments.

[0033] Reference Manual Attached Figure 1 , shows a schematic flow chart of a triple exposure two-end wire mesh wiring method based on state decomposition provided in an embodiment of the present invention.

[0034] The embodiment of the present invention provides a triple exposure two-end wire mesh wiring method based on state decomposition, comprising:

[0035] S1: Get wiring data.

[0036] In a possible implementation, the wiring data includes chip size information, chip layer number information, chip track distribution information, component position information, wiring network information and process constraint information.

[0037] It should be noted that by obtaining detailed wiring data, comprehensive and accurate basic information can be provided for the subsequent wiring process. The collection of such comprehensive data can not only accurately reflect the physical layout of the chip design, but also provide the key constraints required in the wiring process, ensuring that process limitations and design requirements can be fully considered during wiring, thereby optimizing the wiring path and improving the wiring success rate and design efficiency.

[0038] Reference Manual Attached Figure 2 , showing a schematic diagram of the initial wiring diagram structure provided by an embodiment of the present invention.

[0039] like Figure 2 ,In the chip area, wiring diagram nodes (black circular patterns) are added according to the ,intersections of the chip track distribution. There are wiring connection edges ,between adjacent wiring diagram nodes in the vertical or horizontal direction. There are ,wiring connection edges between nodes at the same position in adjacent layers. ,White rectangular patterns are components.

[0040] S2: Construct a wiring diagram structure according to the wiring data.

[0041] Among them, the wiring graph structure refers to abstracting the wiring problem into a graph. The nodes of the graph represent key locations in the circuit (such as starting point, end point, intersection, etc.), and the connecting edges represent possible wiring paths. The weight of the edge usually represents the cost or constraint of the wiring.

[0042] In a possible implementation, S2 specifically includes:

[0043] S201: Establish wiring diagram nodes and wiring connection edges according to chip size information, chip layer number information and chip track distribution information.

[0044] Among them, chip size information refers to the physical size of the chip, including the length, width and border position of the chip, which is used to determine the layout range of the entire chip. The chip layer number information is the number of metal layers used for wiring in the chip, usually marked as M1, M2, etc. Different metal layers can be used for different wiring paths. The chip track distribution information refers to the distribution of pre-defined available wiring tracks in each wiring layer, which is used to guide the specific path selection of wiring. The wiring diagram node is a point that represents a specific position in the wiring diagram, such as the starting point, end point, intersection, etc. of the signal. The wiring connection edge represents the path connecting two nodes in the wiring diagram. The weight of the edge usually reflects the cost or constraint of the wiring.

[0045] It should be noted that by establishing wiring diagram nodes and connection edges through chip size, number of layers and track distribution information, the starting point and potential path of each wiring can be accurately located, which can effectively define the feasible area of ​​wiring and avoid invalid search.

[0046] S202: Determine the correspondence between the component and the wiring diagram node according to the component position information.

[0047] Among them, component location information refers to the specific physical location coordinates of each component (such as transistors, resistors, capacitors, etc.) in the chip design.

[0048] It should be noted that determining the correspondence between components and wiring diagram nodes based on component position information helps to accurately define the signal starting and ending positions, ensures that the nodes in the wiring diagram can accurately reflect the actual layout of the chip, and reduces position errors in path planning, thereby improving wiring accuracy and design consistency.

[0049] S203: Constructing a wiring diagram structure by combining wiring diagram nodes, wiring connection edges, and corresponding relationships between components and wiring diagram nodes.

[0050] In a possible implementation, the wiring diagram node has a position attribute and a distance attribute.

[0051] Among them, the position attribute represents the position of the current wiring diagram node in the actual physical space, including the horizontal coordinate, the vertical coordinate, and the chip layer where it is located. The distance attribute represents the shortest distance between the wiring diagram node and the starting point, which is initially positive infinity.

[0052] It should be noted that by using wiring data to construct a wiring graph structure, complex wiring problems can be intuitively represented in the form of a graph, and the possible paths between nodes and their associated constraints can be clearly defined, so that the wiring problem can be converted into a graph search and optimization problem, which helps to improve the global planning capability of wiring and provides a standardized basis for subsequent path search and weight calculation, thereby optimizing the overall wiring efficiency.

[0053] Reference Manual Attached Figure 3 , showing a schematic diagram of the decomposition of the wiring connection edge state provided by an embodiment of the present invention.

[0054] Figure 3 In the figure, a wiring connection edge in the original wiring diagram structure is decomposed into three wiring connection edges, which respectively represent the wiring states when allocated to the first mask layer (dashed line), the second mask layer (solid line) and the third mask layer (dotted line).

[0055] S3: Decompose the wiring diagram structure into states to obtain multiple independent connection edges.

[0056] In a possible implementation, S3 is specifically:

[0057] According to the mask state, the wiring connection edge in the wiring diagram structure is decomposed into a plurality of connection edges with the same physical space, which respectively represent the connection edges under different mask states.

[0058] The mask state refers to the state of different photolithography mask layers used to achieve high-resolution wiring in a multiple exposure process, and each mask state corresponds to an independent exposure operation.

[0059] Specifically, by decomposing the wiring connection edges into multiple connection edges with the same physical space according to the mask status, the multiple exposure process can be better simulated and mask conflicts can be avoided. During the wiring process, the mutual influence between different masks can be fully considered in the design stage, the wiring results can be optimized, and the wiring success rate and the adaptability of the manufacturing process can be improved.

[0060] In a possible implementation, the number of connection edges having the same physical space is the number of masks in the wiring diagram structure.

[0061] In actual practice, the number of masks in the wiring pattern structure is three under the triple exposure process.

[0062] It should be noted that state decomposition of the wiring diagram structure can break down complex global wiring problems into multiple independent connection edges, effectively reducing the complexity of wiring optimization, so that each connection edge can be processed separately under different mask states, thereby reducing conflicts, improving wiring flexibility and routing rate, and being more efficient under multiple exposure technology.

[0063] Reference Manual Attached Figure 4 , showing a schematic diagram of the wiring diagram structure after state decomposition provided by an embodiment of the present invention.

[0064] like Figure 4 The black rectangle is the routing on the first mask layer, and the diagonal rectangle is the routing on the second mask layer. The weight of the same mask connection edge near the existing routing will be added with a preset penalty value P. The routing method will perform routing search on the wiring diagram structure after state decomposition, starting from the component.

[0065] S4: Calculate the weight of each connecting edge.

[0066] The weight of the connection edge refers to the weight of each connection edge in the wiring diagram, which represents the price or cost of passing through the edge.

[0067] In a possible implementation manner, the weight of the connection edge is calculated based on the physical length of the connection edge, the layer change routing cost, and the process constraint violation cost.

[0068] Among them, physical length refers to the actual geometric distance of the connection edge in the wiring diagram, which is usually positively correlated with signal delay and wiring resource consumption. The cost of layer switching refers to the cost or price required to switch from one layer to another in multi-layer wiring, which usually involves the use of cross-layer vias. The cost of process constraint violation refers to the penalty cost caused by violating process rules (such as minimum line width, spacing, etc.) during the wiring process, which indicates the degree of deviation between the design and process specifications.

[0069] Definition E ijk is the weight of the wiring connection edge between the i-th wiring diagram node and the j-th wiring diagram node when the k-th mask is used; if the i-th wiring diagram node and the j-th wiring diagram node are in the same layer, E ijk The initial setting is the actual length of the wiring connection edge; if the i-th wiring diagram node and the j-th wiring diagram node are laid on the same layer, E ijk The initial setting is the preset layer change cost T; according to the existing wire net and component position information, if the distance between the wiring connection edge and the wire net or component is less than the process constraint, the weight of the wiring connection edge E ijk Add the preset penalty value P.

[0070] Specifically, by defining the weight of the connection edge as the physical length, the cost of layer change routing, and the cost of process constraint violation, the true cost of each path can be fully reflected, which helps the routing algorithm to weigh multiple factors when selecting a path, optimize the routing path, reduce process conflicts and excessive layer changes, and thus improve the overall routing quality and manufacturing success rate.

[0071] It should be noted that calculating the weight of each connecting edge can quantify the comprehensive cost of each path, so that the routing algorithm can make optimal choices based on these weights, which helps to accurately evaluate the pros and cons of each path, thereby finding a routing path that better meets design rules, delay requirements, and process constraints, and improves the overall routing efficiency and effectiveness.

[0072] Reference Manual Attached Figure 5 , showing a schematic diagram of the wiring result of the wiring diagram structure after state decomposition provided by an embodiment of the present invention.

[0073] like Figure 5 , the two-end net paths fully utilize the third mask layer for routing, and do not involve the routing of other mask layers. This shows that in the design process, by selecting a suitable mask layer, the additional cost and complexity brought by mask switching can be effectively avoided. The two-end nets searched in the figure use the third mask layer for routing (dotted line), and no mask switching occurs. The corresponding path is represented by a dark gray pattern.

[0074] Reference Manual Attached Figure 6 , showing a schematic diagram of a simple wire mesh wiring result provided by an embodiment of the present invention.

[0075] like Figure 6 The black rectangle is the routing on the first mask layer. When routing, it is necessary to ensure that there will be no conflict with the routing on other layers, and at the same time, the routing resources on this layer should be used as much as possible. The oblique rectangle is the routing on the second mask layer, which is an independent routing path from the first layer. In actual design, different masks can be exposed independently to ensure that the routing on each layer does not conflict in the process. The white rectangle is the routing on the third mask layer. This layer of routing needs to be separated from the first two layers to avoid occlusion or overlap in the same physical space. Through multi-mask design, the routing of each layer can be relatively independent, which can effectively improve the routing pass rate and density. The advantage of triple exposure is that it provides more space options for high-density routing, which can reduce routing conflicts, improve routing flexibility and design success rate in complex routing scenarios.

[0076] S5: Based on the weight of each connection edge, perform routing search on the two end nets to determine the final routing solution.

[0077] Among them, the two-end wire net is one or more wiring paths with clear starting and ending points, which are used to connect specific signal points or power points.

[0078] In a possible implementation, S5 specifically includes:

[0079] S501: Initialize the starting node of the wiring diagram structure and add the starting node to a to-be-searched list.

[0080] Among them, in the wiring diagram, the starting node is a specific position (or point) indicating the beginning of wiring, usually corresponding to the starting point of the signal or power supply, and the search list is a dynamic storage structure used to store nodes that need to be further expanded and processed during the wiring search process.

[0081] Specifically, by initializing the starting node and adding it to the list to be searched, the starting point of the routing search is clarified, giving the search process a clear direction, which helps to accurately define the starting point of the path in the early stage of the routing search and ensure that the search can be systematically expanded from this point, thereby improving the effectiveness of the path search and the accuracy of the overall routing.

[0082] S502: Select a wiring diagram node with the smallest distance attribute in the to-be-searched list for expansion.

[0083] It should be noted that by selecting the wiring diagram node with the smallest distance attribute in the list to be searched for expansion, the node with the lowest cost can be processed first, ensuring that each step moves towards the optimal path, which can reduce the redundancy and invalid attempts of the search, thereby accelerating the convergence of the wiring, improving the efficiency of the path selection, and ultimately optimizing the wiring results.

[0084] S503: updating the distance attribute of the wiring diagram nodes adjacent to the selected wiring diagram node, and adding the updated wiring diagram nodes to a to-be-searched list.

[0085] It should be noted that updating the distance attributes of the adjacent nodes of the selected wiring diagram node and adding the updated nodes to the list to be searched can help dynamically adjust and optimize each possible path, and ensure that the distance information of each node is up to date during the wiring process, thereby improving the accuracy of path selection, avoiding erroneous or inefficient path selection, and ultimately finding the globally optimal wiring path.

[0086] S504: Repeat steps S502 to S503 until the selected wiring diagram node is the target end point.

[0087] Specifically, through repeated iterations, the path can be gradually expanded and optimized, and the distance attributes can be continuously updated to ensure that an optimal path from the starting node to the target end point is found. This can gradually approach the target in a complex wiring diagram and avoid missing or selecting a suboptimal path, thereby improving the overall accuracy and success rate of wiring.

[0088] S505: Backtrack the path extended to the target end point, determine the final routing plan and update the process constraint violation cost of the connection edge.

[0089] It should be noted that routing search based on the weight of each connection edge can effectively balance the length of the routing path, the cost of layer switching and process constraints, find the globally optimal routing path, and automatically select the routing solution with the lowest cost under multiple constraints, thereby improving the overall efficiency and design quality of routing while reducing the risk of conflicts and process violations.

[0090] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0091] In the present invention, state decomposition is performed according to different mask conditions, which avoids conflicts between different mask layers, significantly improves the routing rate, and effectively reduces the probability of routing failure and retry. By introducing triple exposure technology, the wiring structure can be decomposed into different mask layers, which significantly improves the accuracy and resolution of wiring. By constructing a wiring diagram structure, path optimization can be flexibly performed in multi-layer wiring, making the wiring more comprehensive and accurate. By calculating the weights of the connecting edges, the possible variation risks of the wiring path in the manufacturing process can be evaluated in advance, and high-risk paths can be avoided during the wiring search process, effectively improving the manufacturing yield of the wiring design, so that decisions that are more in line with the design and process requirements can be made in the optimization.

[0092] Reference Manual Attached Figure 7 , showing a structural schematic diagram of a triple exposure two-end wire mesh wiring system based on state decomposition provided by the present invention.

[0093] The present invention further provides a state decomposition-based triple exposure two-end wire mesh wiring system 20, which is applied to the above-mentioned state decomposition-based triple exposure two-end wire mesh wiring method, comprising:

[0094] Processor 201.

[0095] The memory 202 stores computer-readable instructions. When the computer-readable instructions are executed by the processor 201 , the state-decomposition-based triple-exposure two-end wire mesh routing method according to the method embodiment is implemented.

[0096] The state-decomposition-based triple-exposure two-end wire mesh wiring system 20 provided in the present invention can execute the above-mentioned state-decomposition-based triple-exposure two-end wire mesh wiring method and achieve the same or similar technical effects. To avoid repetition, the present invention will not be described in detail.

[0097] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0098] In the present invention, state decomposition is performed according to different mask conditions, which avoids conflicts between different mask layers, significantly improves the routing rate, and effectively reduces the probability of routing failure and retry. By introducing triple exposure technology, the wiring structure can be decomposed into different mask layers, which significantly improves the accuracy and resolution of wiring. By constructing a wiring diagram structure, path optimization can be flexibly performed in multi-layer wiring, making the wiring more comprehensive and accurate. By calculating the weights of the connecting edges, the possible variation risks of the wiring path in the manufacturing process can be evaluated in advance, and high-risk paths can be avoided during the wiring search process, effectively improving the manufacturing yield of the wiring design, so that decisions that are more in line with the design and process requirements can be made in the optimization.

[0099] It should be understood that the processor in the embodiment of the present invention may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0100] It should also be understood that the memory in the embodiments of the present invention may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0101] The above embodiments can be implemented in whole or in part by software, hardware (such as circuits), firmware or any other combination. When implemented by software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When a computer instruction or computer program is loaded or executed on a computer, a process or function according to an embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center by wired (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a tape), an optical medium (for example, a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state hard disk.

[0102] It should be understood that the term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship, but it may also indicate an "and / or" relationship. Please refer to the context for specific understanding.

[0103] In the present invention, "at least one" means one or more, and "plurality" means two or more. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0104] It should be understood that in various embodiments of the present invention, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0105] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0106] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described equipment, devices and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0107] In the several embodiments provided by the present invention, it should be understood that the disclosed devices, apparatuses and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0108] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0109] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0110] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods of various embodiments of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0111] An embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon. When the program is executed by a processor, a triple-exposure two-terminal-net wiring method based on state decomposition as described in a method embodiment is implemented.

[0112] A computer-readable storage medium provided by the present invention can implement the steps and effects of the triple exposure two-end wire mesh wiring method based on state decomposition of the above method embodiment. To avoid repetition, the present invention will not go into details.

[0113] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0114] In the present invention, state decomposition is performed according to different mask conditions, which avoids conflicts between different mask layers, significantly improves the routing rate, and effectively reduces the probability of routing failure and retry. By introducing triple exposure technology, the wiring structure can be decomposed into different mask layers, which significantly improves the accuracy and resolution of wiring. By constructing a wiring diagram structure, path optimization can be flexibly performed in multi-layer wiring, making the wiring more comprehensive and accurate. By calculating the weights of the connecting edges, the possible variation risks of the wiring path in the manufacturing process can be evaluated in advance, and high-risk paths can be avoided during the wiring search process, effectively improving the manufacturing yield of the wiring design, so that decisions that are more in line with the design and process requirements can be made in the optimization.

[0115] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

[0116] There are a few points to note:

[0117] (1) The drawings of the embodiments of the present invention only involve structures related to the embodiments of the present invention. Other structures may refer to conventional designs.

[0118] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present invention, the thickness of layers or regions is exaggerated or reduced, that is, these drawings are not drawn according to the actual scale. It is understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element or there may be intermediate elements.

[0119] (3) In the absence of conflict, the embodiments of the present invention and the features therein may be combined with each other to obtain new embodiments.

[0120] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. The protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A triple exposure two-end wire mesh wiring method based on state decomposition, characterized in that: include: S1: Get wiring data; S2: constructing a wiring diagram structure according to the wiring data; S3: performing state decomposition on the wiring diagram structure to obtain a plurality of independent connection edges; S4: Calculate the weight of each connecting edge; S5: Based on the weight of each connection edge, perform routing search on the two end nets to determine the final routing solution.

2. The triple exposure two-end wire mesh wiring method based on state decomposition according to claim 1, characterized in that: The wiring data includes chip size information, chip layer number information, chip track distribution information, component position information, wiring network information and process constraint information.

3. The triple exposure two-end wire mesh wiring method based on state decomposition according to claim 2, characterized in that: The S2 specifically includes: S201: Establishing wiring diagram nodes and wiring connection edges according to the chip size information, the chip layer number information and the chip track distribution information; S202: Determine the correspondence between the component and the wiring diagram node according to the component position information; S203: Constructing a wiring diagram structure by combining the wiring diagram nodes, the wiring connection edges, and the corresponding relationship between components and the wiring diagram nodes.

4. The triple exposure two-end wire mesh wiring method based on state decomposition according to claim 3, characterized in that: The wiring diagram node has a position attribute and a distance attribute.

5. The triple exposure two-end wire mesh wiring method based on state decomposition according to claim 1, characterized in that: The S3 is specifically: According to the mask state, the wiring connection edge in the wiring diagram structure is decomposed into a plurality of connection edges with the same physical space, which respectively represent the connection edges under different mask states.

6. The triple exposure two-end wire mesh wiring method based on state decomposition according to claim 5, characterized in that: The number of connected edges with the same physical space is the number of masks in the wiring diagram structure.

7. The triple exposure two-end wire mesh wiring method based on state decomposition according to claim 1, characterized in that: The weight of the connection edge is calculated based on the physical length of the connection edge, the cost of changing the layer routing, and the cost of violating the process constraint: Cost=Cost(length) + Cost(via) + Cost(drc) Among them, Cost represents the weight of the connection edge, Cost(length) represents the weight related to the physical length of the connection edge, Cost(via) represents the weight related to the cost of layer change routing, and Cost(drc) represents the weight related to the cost of violating the process constraint of the connection edge.

8. The triple exposure two-end wire mesh wiring method based on state decomposition according to claim 4, characterized in that: The S5 specifically includes: S501: Initialize the starting node of the wiring diagram structure, and add the starting node to a to-be-searched list; S502: Selecting a wiring diagram node with the smallest distance attribute in the list to be searched for expansion; S503: updating the distance attribute of the wiring diagram nodes adjacent to the selected wiring diagram node, and adding the updated wiring diagram nodes to the to-be-searched list; S504: repeating steps S502 to S503 until the selected wiring diagram node is the target end point; S505: Backtrack the path extended to the target endpoint, determine the final routing plan and update the process constraint violation cost of the connection edge.

9. A triple exposure two-end wire mesh wiring system based on state decomposition, characterized in that: include: processor; A memory having computer-readable instructions stored thereon, wherein when the computer-readable instructions are executed by the processor, the triple-exposure two-end wire mesh wiring method based on state decomposition as claimed in any one of claims 1 to 8 is implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the triple-exposure two-terminal-net wiring method based on state decomposition as claimed in any one of claims 1 to 8 is implemented.

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