Gate driving device and display panel

Abstract

The invention provides a gate driving device and a display panel, and belongs to the technical field of display driving, and the gate driving device comprises a signal line group and a plurality of cascaded first driving circuits. Wherein each signal line in the signal line group extends along a first direction in a plane view of the gate driving device. The first driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a first capacitor. The first transistor, the second transistor, and the third transistor are located in a first region in a plan view and arranged in a first direction. The fourth transistor and the fifth transistor are located in a second area in the plan view and arranged in the first direction. Wherein the first region, the second region and the first capacitor are sequentially arranged along a second direction intersecting with the first direction. Thus, the transistors are arranged in the first area and the second area according to functions, the layout compactness is improved, space waste is effectively avoided, and the narrow frame of the display panel is achieved.

Description

Technical Field

[0001] The present application relates to the field of display driving technology, and in particular to a gate driving device and a display panel. Background Art

[0002] In an OLED (Organic Light-Emitting Diode) display panel, a gate driver on array (GOA) is an important component, which directly affects the performance and border width of the OLED display panel.

[0003] At present, there are many types of gate drive devices for common OLED display panels. The number of thin film transistors and capacitors required for each type of gate drive device is different. Generally, the more thin film transistors there are, the better the performance of the gate drive device. However, with the demand for narrow borders, too many thin film transistors are not conducive to the realization of narrow borders for OLED display panels.

[0004] Therefore, how to achieve narrow frame of OLED display panel is a problem that needs to be solved urgently. Summary of the invention

[0005] In view of the deficiencies in the prior art, the present application provides a gate driving device and a display panel.

[0006] In a first aspect, the present application provides a gate driving device, comprising: a signal line group and a plurality of first driving circuits connected in cascade;

[0007] Each signal line in the signal line group extends along a first direction in a plan view of the gate driving device;

[0008] The first driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a first capacitor;

[0009] The first transistor, the second transistor and the third transistor are located in a first region in the plan view and are arranged along the first direction;

[0010] The fourth transistor and the fifth transistor are located in the second region in the plan view and are arranged along the first direction;

[0011] The first region, the second region, and the first capacitor are sequentially arranged along a second direction intersecting the first direction in the plan view.

[0012] Optionally, the signal line includes a clock line, a start line, a first potential line and a second potential line;

[0013] The gate of the first transistor is connected to the clock line, the first electrode is connected to the start line, and the second electrode is connected to the first node;

[0014] The second transistor has a gate connected to the first node, a first electrode connected to the first potential line, and a second electrode connected to a second node;

[0015] The gate of the third transistor is connected to the first node, the first electrode is connected to the second potential line, and the second electrode is connected to the second node;

[0016] The gate of the fourth transistor is connected to the first node, the first electrode is connected to the second potential line, and the second electrode is connected to the output end of the first driving circuit;

[0017] The gate of the fifth transistor is connected to the second node, the first electrode is connected to the first potential line, and the second electrode is connected to the output end of the first driving circuit;

[0018] One end of the first capacitor is connected to the first node, and the other end is connected to the output end of the first driving circuit;

[0019] The first potential line and the second potential line cover the fourth transistor and the fifth transistor; the clock line and the start line are located on one side of the fourth transistor and the fifth transistor in the plan view.

[0020] Optionally, when the first driving circuit is used to output a threshold compensation signal or a first reset signal, a ratio of a channel width to a channel length of the fourth transistor and the fifth transistor is greater than a preset aspect ratio; wherein the preset aspect ratio is 40:1.

[0021] Optionally, the clock line includes a first clock line, and the signal line further includes a first inverted clock line;

[0022] The first clock line and the first inverted clock line are respectively located at two sides of the first region in the plan view.

[0023] Optionally, when the first driving circuit is used to output a light emitting control signal or a second reset signal, a ratio of a channel width to a channel length of the fourth transistor and the fifth transistor is smaller than a preset aspect ratio.

[0024] Optionally, the clock line includes a second clock line, and the signal line further includes a second inverted clock line;

[0025] The second clock line, the second inverted clock line, and the start line are located on a side of the first region away from an output terminal of the first driving circuit in the plan view.

[0026] Optionally, it further comprises a plurality of second drive circuits cascaded for outputting a scanning signal, wherein the signal line comprises a third clock line, a first potential line and a second potential line;

[0027] The second driving circuit includes a first transistor group, a second transistor group and an output sub-circuit;

[0028] The first transistor group is connected to the third clock line, the second potential line and the output sub-circuit;

[0029] The second transistor group is connected to the first potential line and the output sub-circuit;

[0030] Wherein, the first transistor group includes a plurality of transistors located in the third region, and the plurality of transistors are arranged along the second direction in the plan view;

[0031] The second transistor group includes a plurality of transistors located in a fourth region, and the plurality of transistors are arranged along the second direction in the plan view; the third region and the fourth region are arranged along the first direction, and there is a gap between the third region and the fourth region.

[0032] Optionally, the signal line includes a third inverted clock line;

[0033] The first transistor group includes a sixth transistor, a seventh transistor and a ninth transistor; the second transistor group includes an eighth transistor, a tenth transistor and an eleventh transistor; the output sub-circuit includes a twelfth transistor and a thirteenth transistor;

[0034] The gate of the sixth transistor is connected to the start line, the first electrode is connected to the second potential line, and the second electrode is connected to the third node;

[0035] The gate of the seventh transistor is connected to the fourth node, the first electrode is connected to the third inverted clock line, and the second electrode is connected to the fifth node;

[0036] The gate of the eighth transistor is connected to the start line, the first electrode is connected to the first potential line, and the second electrode is connected to the fourth node;

[0037] The gate of the ninth transistor is connected to the second potential line, the first electrode is connected to the third node, and the second electrode is connected to the sixth node;

[0038] The gate of the tenth transistor is connected to the third node, the first electrode is connected to the first potential line, and the second electrode is connected to the fifth node;

[0039] The eleventh transistor has a gate connected to the fifth node, a first electrode connected to the first potential line, and a second electrode connected to the third node;

[0040] The gate of the twelfth transistor is connected to the sixth node, the first electrode is connected to the third clock line, and the second electrode is connected to the scan signal output terminal of the second driving circuit;

[0041] The gate of the thirteenth transistor is connected to the fifth node, the first electrode is connected to the second potential line, and the second electrode is connected to the scan signal output terminal;

[0042] Among them, a plurality of the third clock lines cover the first transistor group and the second transistor group, and the third clock lines are arranged in sequence at equal intervals along the second direction; and the first potential line covers the output sub-circuit.

[0043] Optionally, the ratio of the channel width to the channel length of the seventh transistor is greater than the ratio of the channel width to the channel length of the eleventh transistor.

[0044] Optionally, the tenth transistor is a dual-gate transistor.

[0045] In a second aspect, in one embodiment, the present application provides a display panel, comprising a pixel circuit and the above-mentioned gate driving device, wherein the gate driving device is used to drive the pixel circuit.

[0046] In summary, in the present application, firstly, the first transistor, the second transistor and the third transistor in the cascaded multiple first driving circuits are arranged along the first direction in the first region, and the fourth transistor and the fifth transistor are also arranged along the first direction in the second region, so that the transistors are arranged in the first region and the second region according to their functions, thereby ensuring functional integrity and making full use of the plane space. Secondly, by arranging the first region, the second region and the first capacitor in sequence along the second direction intersecting the first direction in the plane view, the compactness of the layout is further improved, effectively avoiding space waste, thereby helping to achieve a narrow frame of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0048] Figure 1 This is a schematic diagram of a display panel in one embodiment of the present application;

[0049] Figure 2 A schematic diagram of a pixel circuit in one embodiment of the present application;

[0050] Figure 3 This is a schematic diagram of the structure of a first driving circuit in one embodiment of the present application;

[0051] Figure 4 A stacking diagram of an active layer, a gate layer, and a first source and drain layer of a first driving circuit in an embodiment of the present application;

[0052] Figure 5 A stacking diagram of an active layer, a gate layer, a first source-drain electrode layer, and a second source-drain electrode layer of a first driving circuit in an embodiment of the present application;

[0053] Figure 6 A stacking diagram of an active layer and a gate layer of a first driving circuit in one embodiment of the present application;

[0054] Figure 7 A stacking diagram of an active layer, a gate layer, a first source-drain electrode layer, and a second source-drain electrode layer of a first driving circuit in another embodiment of the present application;

[0055] Figure 8 A stacking diagram of an active layer and a gate layer of a first driving circuit in another embodiment of the present application;

[0056] Fig. 9 This is a schematic structural diagram of a second driving circuit in another embodiment of the present application;

[0057] Fig.10 A stacking diagram of an active layer, a gate layer, and a first source and drain layer of a second driving circuit in one embodiment of the present application;

[0058] Fig.11 A stacking diagram of an active layer, a gate layer, a first source-drain electrode layer, and a second source-drain electrode layer of a second driving circuit in one embodiment of the present application;

[0059] Fig.12 This is a stacking diagram of the active layer and the gate layer of the second driving circuit in one embodiment of the present application.

[0060] Description of reference numerals: 100, first region; 200, second region; 300, third region; 400, fourth region; 500, output sub-circuit. DETAILED DESCRIPTION

[0061] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0062] In the description of the present application, it should be understood that the terms "first" and "second" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. In the present application, the word "exemplary" is used to mean "used as an example, illustration or description". Any embodiment described as "exemplary" in the present application is not necessarily interpreted as being more preferred or more advantageous than other embodiments. In order to enable any technician in the field to implement and use the present application, the following description is given. In the following description, details are listed for the purpose of explanation. It should be understood that a person of ordinary skill in the art can recognize that the present application can also be implemented without using these specific details. In other examples, well-known structures and processes will not be elaborated in detail to avoid unnecessary details that make the description of the present application obscure. Therefore, the present application is not intended to be limited to the embodiments shown, but is consistent with the widest range of principles and features disclosed in the present application.

[0063] The gate driving device in the embodiment of the present application is used to drive a display panel. The display panel can be a terminal with a display function, such as a mobile phone, a tablet computer, a desktop computer, an e-reader, an electronic display screen, a laptop computer, a media player, a wearable device, a digital camera, a car navigation system, etc.

[0064] Reference Figure 1 As shown, Figure 1 Schematic diagram of a display panel in an embodiment of the present application, the display panel includes a display area AA and a non-display area NA disposed adjacent to the display area AA, and the non-display area NA surrounds the display area AA. The display area AA is an area in the display panel used to perform a display function, and a plurality of display units are disposed therein to implement the display function. The non-display area NA may be a frame area of ​​the display panel, and a functional component that assists the display unit in the display area AA to perform display may be disposed therein.

[0065] A plurality of light emitting devices D1 and a pixel circuit 30 for driving the light emitting devices D1 may be arranged in an array in the display area AA. Figure 2 , Figure 2is a schematic diagram of a pixel circuit 30. The pixel circuit 30 may include a driving transistor T1A, a switching transistor T2A, a compensation transistor T3A, a first reset transistor T4A, a second reset transistor T7A, a third reset transistor T8A, a first light-emitting transistor T5A, a second light-emitting transistor T6A, a boost capacitor Cboost, and a control capacitor Cst2. Among them, the first electrode of the switching transistor T2A is connected to the data signal line Data, the second electrode of the switching transistor T2A is connected to the node A1, and the gate of the switching transistor T2A receives the scan signal Pscan1. The first electrode of the driving transistor T1A is connected to the node A1, the second electrode of the driving transistor T1A is connected to the node B1, and the gate of the driving transistor T1A is connected to the node Q1. The first electrode of the compensation transistor T3A is connected to the node Q1, the second electrode of the compensation transistor T3A is connected to the node B1, and the gate of the compensation transistor T3A receives the threshold compensation signal Nscan1. The first electrode of the first reset transistor T4A receives the first reset signal Vi1, the second electrode of the first reset transistor T4A is connected to the node Q1, and the gate of the first reset transistor T4A receives the first reset signal Nscan2. The first electrode of the second reset transistor T7A is connected to the second reset signal Vi2, the second electrode of the second reset transistor T7A is connected to the anode of the light emitting device, and the gate of the second reset transistor T7A receives the second reset signal Pscan2. The first electrode of the third reset transistor T8A receives the third reset signal Vi3, the second electrode of the third reset transistor T8A is connected to the node A1, and the gate of the third reset transistor T8A receives the third reset signal Vi3. The first electrode of the first light emitting transistor T5A is connected to the high level source VDD, the second electrode of the first light emitting transistor T5A is connected to the node A1, and the gate of the first light emitting transistor T5A receives the light emitting control signal EM. The first electrode of the second light emitting transistor T6A is connected to the second node B1, the second electrode of the second light emitting transistor T6A is connected to the anode of the light emitting device, and the gate of the second light emitting transistor T6A receives the light emitting control signal EM. One end of the boost capacitor Cboost is connected to the node Q1, and the other end of the boost capacitor Cboost is connected to the gate of the switch transistor T2A; one end of the control capacitor Cst2 is connected to the node Q1, and the other end of the control capacitor Cst2 is connected to the high level source VDD. The cathode of the light emitting device D1 is connected to the low level source VSS. In this way, the pixel circuit 30 realizes the light emission control of the light emitting device D1 based on the scanning signal Pscan1, the threshold compensation signal Nscan1, the first reset signal Nscan2, the second reset signal Pscan2 and the light emission control signal EM.

[0066] Combination Figure 1, a gate driving device is arranged in the non-display area NA. The gate driving device may include a second driving circuit 20 arranged in cascade and several groups of first driving circuits arranged in cascade; wherein the several groups of first driving circuits may be a threshold compensation circuit 11, a first reset circuit 12, a second reset circuit 13 and a light emitting control circuit 14, respectively. As an example, the threshold compensation circuit 11 is used to output a threshold compensation signal Nscan1, and the threshold compensation circuit 11 may be located on one side of the display area AA, and each threshold compensation circuit 11 drives two rows of pixel circuits 30 in the display area AA, that is, the threshold compensation circuit 11 may be a single-sided one-drive-two arrangement. The first reset circuit 12 is used to output a first reset signal Nscan2, and the first reset circuit 12 may be arranged on the other side of the display area AA, opposite to the threshold compensation circuit 11, and each first reset circuit 12 drives two rows of pixel circuits 30 in the display area AA, that is, the first reset circuit 12 may be a single-sided one-drive-two arrangement. The second reset circuit 13 is used to output the second reset signal Pscan2. The second reset circuit 13 can be located on one side of the display area AA. Each second reset circuit 13 drives two rows of pixel circuits 30 in the display area AA, that is, the second reset circuit 13 can be a single-sided one-drive-two setting. The light-emitting control circuit 14 is used to output the light-emitting control signal EM. The light-emitting control circuit 14 can be located on the other side of the display area AA, and is arranged opposite to the second reset circuit 13. As an example, each light-emitting control circuit 14 can drive two rows of pixel circuits 30 in the display area AA, and the light-emitting control circuit 14 can be a single-sided one-drive-two setting. The second drive circuit 20 is used to output the scan signal Pscan1. The second drive circuits 20 are respectively arranged on both sides of the display area AA. The two second drive circuits 20 located on both sides of the same row of pixel circuits 30 share the same row of pixel circuits 30, that is, the second drive circuit 20 can be a bilateral one-drive-one setting.

[0067] It should be noted that the structures of the above-mentioned pixel circuit 30 and the gate driving device are only examples, and the pixel circuit 30 may also be a pixel circuit such as 8T2C, 8T3C, 8T4C, etc., and this application does not impose any specific restrictions.

[0068] First, as Figure 3 and Figure 4As shown, in one embodiment, the present application provides a gate driving device, the gate driving device includes a signal line group and a plurality of first driving circuits in cascade. Wherein, each signal line in the signal line group extends along a first direction X in a plan view of the gate driving device. The first driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a first capacitor C1. The first transistor T1, the second transistor T2 and the third transistor T3 are located in a first area 100 in a plan view and are arranged along the first direction X. The fourth transistor T4 and the fifth transistor T5 are located in a second area 200 in a plan view and are arranged along the first direction X.

[0069] The first region 100, the second region 200 and the region where the first capacitor C1 is located are arranged in sequence along a second direction Y intersecting the first direction X in a plan view. In this embodiment, the second direction Y is parallel to the scan line, and the angle between the first direction X and the second direction Y is greater than 0° and less than or equal to 90°.

[0070] As an example, the non-display area NA may be provided with a base substrate and an array driving layer on the base substrate; the array driving layer may include a plurality of active layers, a plurality of gate layers and a plurality of source-drain layers; the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the first capacitor C1 may be provided in the active layer and the gate layer. The signal line group may be provided in the source-drain layer.

[0071] In the above embodiment, firstly, the first transistor T1, the second transistor T2 and the third transistor T3 are arranged along the first direction X in the first region 100, and the fourth transistor T4 and the fifth transistor T5 are also arranged along the first direction X in the second region 200, so that the transistors are arranged in the first region 100 and the second region 200 according to their functions, thereby ensuring functional integrity and making full use of the plane space. Secondly, the first region 100, the second region 200 and the first capacitor C1 are arranged in sequence along the second direction Y intersecting the first direction X in a plane view, thereby further improving the compactness of the layout, effectively avoiding space waste, and thus helping to achieve a narrow frame of the display panel.

[0072] Reference Figure 3In some embodiments, the signal line includes a clock line, a start line STV, a first potential line VGH, and a second potential line VGL. The gate of the first transistor T1 is connected to the clock line, the first electrode is connected to the start line STV, and the second electrode is connected to the first node Q1. The gate of the second transistor T2 is connected to the first node Q1, the first electrode is connected to the first potential line VGH, and the second electrode is connected to the second node P1. The gate of the third transistor T3 is connected to the first node Q1, the first electrode is connected to the second potential line VGL, and the second electrode is connected to the second node P1. The gate of the fourth transistor T4 is connected to the first node Q1, the first electrode is connected to the second potential line VGL, and the second electrode is connected to the output end of the first drive circuit. The gate of the fifth transistor T5 is connected to the second node P1, the first electrode is connected to the first potential line VGH, and the second electrode is connected to the output end of the first drive circuit. One end of the first capacitor C1 is connected to the first node Q1, and the other end is connected to the output end of the first drive circuit.

[0073] The first potential line VGH and the second potential line VGL cover the fourth transistor T4 and the fifth transistor T5. The clock line and the start line STV are located at one side of the fourth transistor T4 and the fifth transistor T5 in a plan view.

[0074] As an example, the working process of the first driving circuit is as follows: first, the start line STV inputs a start signal to the first transistor T1, and the first transistor T1 shifts the phase of the start signal by half a cycle of the clock signal under the control of the clock signal of the clock line, that is, the phase of the signal transmitted by the first node Q1 lags behind the start signal by half a cycle of the clock signal. When the signal transmitted by the first node Q1 is a high potential, the second transistor T2 and the fourth transistor T4 are turned off, the third transistor T3 is turned on, and the fifth transistor T5 is turned on under the control of the low potential signal output by the third transistor T3, and the first potential line VGH outputs a high potential signal to the output terminal NOUT of the first driving circuit. When the signal transmitted by the first node Q1 is a low potential, the second transistor T2 and the fourth transistor T4 are turned on, the third transistor T3 is turned off, and the fifth transistor T5 is turned off under the control of the high potential signal output by the second transistor T2, and the second potential line VGL outputs a low potential signal to the output terminal NOUT of the first driving circuit.

[0075] In some embodiments, the clock line includes a first clock line CK1, and the signal line further includes a first inverted clock line XCK1. The first clock line CK1 and the first inverted clock line XCK1 are respectively located at two sides of the first region 100 in a plan view.

[0076] As an example, since the first region 100 is provided with a first transistor T1, a second transistor T2 and a third transistor T3, and parasitic capacitance exists in the first transistor T1, the second transistor T2 and the third transistor T3, the first clock line CK1 and the first inverted clock line XCK1 are provided on both sides of the first region 100, and the parasitic capacitance in the first transistor T1, the second transistor T2 and the third transistor T3 is substantially consistent with the capacitance difference between the first clock line CK1 and the first inverted clock line XCK1, so that the load on the first clock line CK1 and the first inverted clock line XCK1 is balanced.

[0077] Reference Figure 4 and Figure 5 In some embodiments, when the first driving circuit is used to output the threshold compensation signal Nscan1 or the first reset signal Nscan2, the ratio of the channel width to the channel length of the fourth transistor T4 and the fifth transistor T5 is greater than the preset aspect ratio. As an example, the preset aspect ratio is 40:1. The ratio of the channel width to the channel length of the fourth transistor T4 and the ratio of the channel width to the channel length of the fifth transistor T5 may be the same or different.

[0078] When the first driving circuit is used to output the threshold compensation signal Nscan1 , the first driving circuit is used as the threshold compensation circuit 11 ; when the first driving circuit is used to output the first reset signal Nscan2 , the first driving circuit is used as the first reset circuit 12 .

[0079] Combination Figure 2 ,by Figure 2 Taking the pixel circuit 30 in the example, the threshold compensation signal Nscan1 acts on the compensation transistor T3A in the pixel circuit 30, and the first reset signal Nscan2 acts on the first reset transistor T4A. Since the compensation transistor T3A and the first reset transistor T4A are N-type transistors, in order to make the compensation transistor T3A and the first reset transistor T4A saturated and turned on, the threshold compensation signal Nscan1 and the first reset signal Nscan2 need to generate a higher step voltage (a voltage difference generated when quickly transitioning from a stable voltage level to another stable voltage level), and the ratio of the width to the channel length of the fourth transistor T4 and the fifth transistor T5 is greater than the preset aspect ratio, which can improve the current handling capacity of the fourth transistor T4 and the fifth transistor T5, so that the fourth transistor T4 and the fifth transistor T5 can respond to the change of their respective gate signals more quickly, so that the fourth transistor T4 and the fifth transistor T5 can accurately provide the threshold compensation signal Nscan1 or the first reset signal Nscan2 with a higher step voltage, which helps to improve the response speed of the output threshold compensation signal Nscan1 or the first reset signal Nscan2, and reduce the delay time.

[0080] In some embodiments, the source-drain layer in the array driving layer may include a first source-drain layer and a second source-drain layer. As an example, the gate layer may include a first gate layer, a second gate layer and a third gate layer; the active layer may include a first active layer and a second active layer.

[0081] Reference Figure 6 As an example, the first gate layer may include a gate T1G of the first transistor T1, a gate T2G of the second transistor T2, a gate T4G of the fourth transistor T4, and a gate T5G of the fifth transistor T5; the second gate layer may include a gate T3G of the third transistor T3; wherein the gate T1G of the first transistor T1, the gate T2G of the second transistor T2, and the gate T3G of the third transistor T3 may extend along the second direction Y. The gate T4G of the fourth transistor T4 and the gate T5G of the fifth transistor T5 each include a plurality of gate branches, each of which extends along the second direction Y and is arranged sequentially in the first direction X. The third gate layer may include a first plate of the first capacitor C1.

[0082] Reference Figure 6 As an example, the first transistor T1, the second transistor T2, the fourth transistor T4 and the fifth transistor T5 are P-type transistors, and the third transistor T3 is an N-type transistor. In this example, the first electrode of the first transistor T1, the second transistor T2, the fourth transistor T4 and the fifth transistor T5 can be a source electrode, the second electrode can be a drain electrode, and the first electrode of the third transistor T3 can be a drain electrode and the second electrode can be a source electrode. The first active layer includes an active portion formed by the first electrode T1S and the second electrode T1D of the first transistor T1, an active portion formed by the first electrode T2S and the second electrode T1D of the second transistor T2, an active portion formed by the first electrode T4S and the second electrode T4D of the fourth transistor T4, and an active portion formed by the first electrode T5S and the second electrode T5D of the fifth transistor T5, and a second plate of the first capacitor C1. The material of the second active layer can be an indium gallium zinc oxide semiconductor, and the second active layer includes an active portion formed by the first electrode T3D and the second electrode T3S of the third transistor T3. The active parts of the first transistor T1, the second transistor T2 and the third transistor T3 extend along the first direction X, the active parts of the fourth transistor T4 and the fifth transistor T5 extend along the first direction X, and the active parts of the fourth transistor T4 and the fifth transistor T5 are connected. At the same time, the active parts of the above transistors have overlapping parts with the gates of the corresponding transistors, and the overlapping parts are the channels of the corresponding transistors.

[0083] Combination Figure 5, the first source-drain layer includes a plurality of connectors. As an example, the first connector is connected to the gate T3G of the third transistor T3, the second electrode T1D of the first transistor T1, and the gate T4G of the fourth transistor T4 through the via hole, so that the gate T3G of the third transistor T3 located at the second gate layer, the second electrode T1D of the first transistor T1 located at the first active layer, and the gate T4G of the fourth transistor T4 located at the first gate layer are connected to the first node Q1. The second connector is connected to the second electrode T2D of the second transistor T2, the second electrode T3S of the third transistor T3, and the gate T5G of the fifth transistor T5 through the via hole, so that the second electrode T2D of the second transistor T2 located at the first active layer, the second electrode T3S of the third transistor T3, and the gate T5G of the fifth transistor T5 located at the first gate layer are connected to the second node P1.

[0084] Combination Figure 4 , the second source-drain layer includes a start line STV, a first clock line CK1, a first inverted clock line XCK1, a first potential line VGH, and a second potential line VGL; as an example, the gate T1G of the first transistor T1 extends below the first clock line CK1 along the second direction Y, and the gate T1G of the first transistor T1 is connected to the first clock line CK1 through a via. The first potential line VGH and the second potential line VGL cover the fourth transistor T4 and the fifth transistor T5, the first electrode T4S of the fourth transistor T4 is connected to the second potential line VGL through a via, and the first electrode T5S of the fifth transistor T5 is connected to the first potential line VGH through a via.

[0085] Reference Figure 7 and Figure 8 In another embodiment, when the first driving circuit is used to output the light emitting control signal EM or the second reset signal Pscan2, the ratio of the channel width to the channel length of the fourth transistor T4 and the fifth transistor T5 is less than the preset aspect ratio.

[0086] When the first driving circuit is used to output the light emitting control signal EM, the first driving circuit is used as the light emitting control circuit 14 ; when the first driving circuit is used to output the second reset signal Pscan2 , the first driving circuit is used as the second reset circuit 13 .

[0087] In another embodiment, the clock line includes a second clock line CK2, and the signal line further includes a second inverted clock line XCK2. The second clock line CK2, the second inverted clock line XCK2 and the start line STV are located on a side of the first region 100 away from the output terminal of the first driving circuit in a plan view.

[0088] Reference Figure 8As an example, when the first driving circuit is used as the light emitting control circuit 14 and the second reset circuit 13, the arrangement of the gate, the first electrode and the second electrode of each transistor (including the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5) in the active layer and the gate layer is consistent with the arrangement of the gate, the first electrode and the second electrode of each transistor in the active layer and the gate layer when the first driving circuit is used as the first reset circuit 12 and the threshold compensation circuit 11, and will not be repeated here. However, when the first driving circuit is used as the light emitting control circuit 14 and the second reset circuit 13, the area of ​​the active part of the fourth transistor T4 and the active part of the fifth transistor T5 can be smaller than the area of ​​the active part of the fourth transistor T4 and the active part of the fifth transistor T5 when the first driving circuit is used as the first reset circuit 12 and the threshold compensation circuit 11.

[0089] Combination Figure 2 ,by Figure 2 Taking the pixel circuit 30 in FIG. 3 as an example, the light emitting control signal EM acts on the first light emitting transistor T5A and the second light emitting transistor T6A in the pixel circuit 30, and the second reset signal Pscan2 acts on the second reset transistor T7A. Since the second reset transistor T7A, the first light emitting transistor T5A and the second light emitting transistor T6A are P-type transistors, the step voltage required for the light emitting control signal EM and the second reset signal Pscan2 is relatively low. Accordingly, the current handling capacity requirements for the fourth transistor T4 and the fifth transistor T5 are relatively low. Therefore, when the first driving circuit is used to output the light emitting control signal EM or the second reset signal Pscan2, the ratio of the channel width to the channel length of the fourth transistor T4 and the fifth transistor T5 is smaller than the ratio of the channel width to the channel length of the fourth transistor T4 and the fifth transistor T5 used by the first driving circuit to output the threshold compensation signal Nscan1 or the first reset signal Nscan2, which helps to further save space.

[0090] Reference Figure 7 , the first source-drain layer also includes several connectors; as an example, the first connector is connected to the gate T3G of the third transistor T3, the second electrode T1D of the first transistor T1, and the gate T4G of the fourth transistor T4 through the via hole; the second connector is connected to the second electrode T2D of the second transistor T2, the second electrode T3S of the third transistor T3, and the gate T5G of the fifth transistor T5 through the via hole. The gate T1G of the first transistor T1 extends to the bottom of the second clock line CK2 and is connected to the second clock line CK2 through the via hole.

[0091] Reference Figure 7, the first source-drain layer also includes a start line STV, a second clock line CK2, a second reverse clock line, and a second potential line VGL. The start line STV, the second clock line CK2, the second reverse clock line, and the second potential line VGL are arranged in sequence at equal intervals along the second direction Y. The second source-drain layer includes a first potential line VGH and a second potential line VGL, and the first potential line VGH and the second potential line VGL cover the top of the fourth transistor T4 and the fifth transistor T5, that is, the second potential line VGL can have two groups, which are respectively located in the first source-drain layer and the second source-drain layer. In the plan view of the gate driving device, the start line STV, the second clock line CK2, the second reverse clock line, and one of the second potential lines VGL are located on one side of the first transistor T1, the second transistor T2, and the third transistor T3, and the first potential line VGH and the other second potential line VGL are located on the other side of the first transistor T1, the second transistor T2, and the third transistor T3. Furthermore, the above signal lines are distributed in the first source-drain layer and the second source-drain layer respectively, so that the metal wiring distribution of the first source-drain layer and the second source-drain layer is more uniform, thereby optimizing the current distribution in the array driving layer and helping to improve local overheating.

[0092] Reference Fig. 9 and Fig.10 In some embodiments, the gate driving device further includes a plurality of second driving circuits 20 cascaded to output a scanning signal Pscan1, and the signal line includes a third clock line CK3, a first potential line VGH, and a second potential line VGL. The second driving circuit 20 includes a first transistor group, a second transistor group, and an output subcircuit 500. The first transistor group is connected to the third clock line CK3, the second potential line VGL, and the output subcircuit 500. The second transistor group is connected to the first potential line VGH and the output subcircuit 500. As an example, the output terminal POUT of the second driving circuit 20 is connected to the scanning line for outputting the scanning signal Pscan1 to the scanning line.

[0093] The first transistor group includes a plurality of transistors located in the third region 300, and the plurality of transistors are sequentially arranged in a plan view along a second direction Y. The second transistor group includes a plurality of transistors located in the fourth region 400, and the plurality of transistors are sequentially arranged in a plan view along a second direction Y. The third region 300 and the fourth region 400 are arranged along a first direction X, and there is a gap between the third region 300 and the fourth region 400.

[0094] Combination Fig.11, in some embodiments, the signal line includes a third inverted clock line XCK3. The first transistor group includes a sixth transistor T6, a seventh transistor T7, and a ninth transistor T9. The second transistor group includes an eighth transistor T8, a tenth transistor T10, and an eleventh transistor T11. The output sub-circuit 500 includes a twelfth transistor T12 and a thirteenth transistor T13. The gate of the sixth transistor T6 is connected to the start line STV, the first electrode is connected to the second potential line VGL, and the second electrode is connected to the third node N. The gate of the seventh transistor T7 is connected to the fourth node K, the first electrode is connected to the third inverted clock line XCK3, and the second electrode is connected to the fifth node P2. The gate of the eighth transistor T8 is connected to the start line STV, the first electrode is connected to the first potential line VGH, and the second electrode is connected to the fourth node K. The gate of the ninth transistor T9 is connected to the second potential line VGL, the first electrode is connected to the third node N, and the second electrode is connected to the sixth node Q2. The gate of the tenth transistor T10 is connected to the third node N, the first electrode is connected to the first potential line VGH, and the second electrode is connected to the fifth node P2. The gate of the eleventh transistor T11 is connected to the fifth node P2, the first electrode is connected to the first potential line VGH, and the second electrode is connected to the third node N. The gate of the twelfth transistor T12 is connected to the sixth node Q2, the first electrode is connected to the third clock line CK3, and the second electrode is connected to the scan signal Pscan1 output terminal of the second driving circuit 20. The gate of the thirteenth transistor T13 is connected to the fifth node P2, the first electrode is connected to the second potential line VGL, and the second electrode is connected to the scan signal Pscan1 output terminal.

[0095] A plurality of third clock lines CK3 cover the first transistor group and the second transistor group, and the third clock lines CK3 are arranged in sequence at equal intervals along the second direction Y. The first potential line VGH covers the output sub-circuit 500 .

[0096] As an example, a second capacitor C2 is also connected in series between the gate of the twelfth transistor T12 and the second electrode; a third capacitor C3 is also connected in series between the gate of the thirteenth transistor T13 and the second electrode; a fourth capacitor C4 is also connected in series between the gate of the seventh transistor T7 and the second electrode; the twelfth transistor T12 and the second capacitor C2 constitute a bootstrap capacitor, which converts the signal transmitted by the sixth node Q2 into an ultra-low potential lower than the potential of the low potential signal transmitted by the second potential line VGL, thereby generating a low-potential scanning signal Pscan1 and outputting it from the output terminal POUT. The ninth transistor T9 is used to shield the influence of the potential (ultra-low potential) generated by the sixth node Q2 on the potential of the signal transmitted by the third node N. The control unit composed of the sixth transistor T6 and the eleventh transistor T11 can extend the time of the low-potential scanning signal Pscan1 output by the output terminal POUT of the second driving circuit 20. The fourth capacitor C4, the eighth transistor T8 and the seventh transistor T7 constitute the inverting signal unit of the third node N, ensuring that in the stage of outputting the low-potential scanning signal Pscan1, the thirteenth transistor T13 is in a closed state, and the high-potential signal of the first potential line VGH cannot be transmitted to the output terminal POUT of the second driving circuit 20 through the thirteenth transistor T13. The tenth transistor T10 and the eleventh transistor T11 work together to make the signals transmitted by the third node N and the fifth node P2 present an inverted relationship. Specifically, when the signal transmitted by the third node N is a high-potential signal, the signal transmitted by the fifth node P2 is a low-potential signal; conversely, when the signal transmitted by the third node N is a low-potential signal, the signal transmitted by the fifth node P2 is a high-potential signal.

[0097] In some embodiments, a ratio of a channel width to a channel length of the seventh transistor T7 is greater than a ratio of a channel width to a channel length of the eleventh transistor T11 .

[0098] As an example, the channel width and channel length of the seventh transistor T7 are represented as W7 and L7 respectively, and the channel width and channel length of the eleventh transistor T11 are represented as W11 and L11 respectively, then W7 / L7 is greater than W11 / L11, for example, (W7 / L7) / (W11 / L11) can be 2:1. The manner of achieving the ratio of the channel width to the channel length of the seventh transistor T7 being greater than the ratio of the channel width to the channel length of the eleventh transistor T11 is not specifically limited. For example, the channel width of the seventh transistor T7 may be increased or the channel width of the eleventh transistor T11 may be decreased so that the channel width of the seventh transistor T7 is greater than the channel width of the eleventh transistor T11; the channel length of the eleventh transistor T11 may be increased or the channel length of the seventh transistor T7 may be decreased so that the channel length of the seventh transistor T7 is less than the channel length of the eleventh transistor T11; the ratio of the channel width to the channel length of the seventh transistor T7 may be increased while the channel length of the seventh transistor T7 is decreased, and other manners may be used. No specific limitation is made herein, as long as the ratio of the channel width to the channel length of the seventh transistor T7 is greater than the ratio of the channel width to the channel length of the eleventh transistor T11.

[0099] As an example, the ratio of the channel width to the channel length of the seventh transistor T7 is greater than the ratio of the channel width to the channel length of the eleventh transistor T11, which improves the current driving capability of the seventh transistor T7 and avoids insufficient potential writing of the fifth node P2. If the potential writing of the fifth node P2 is insufficient, on the one hand, it may cause the output of the thirteenth transistor T13 to be abnormal, and on the other hand, it may affect the on-off control of the eleventh transistor T11, so that the potential writing of the third node N is insufficient, which may easily lead to insufficient potential of the sixth node Q2.

[0100] In the above embodiment, by making the ratio of the width-to-length ratio of the seventh transistor T7 and the width-to-length ratio of the eleventh transistor T11 greater than or equal to a preset ratio, insufficient potential writing of the sixth node Q2 and the fifth node P2 is avoided, so that the twelfth transistor T12 connected to the sixth node Q2 and the thirteenth transistor T13 connected to the fifth node P2 can achieve stable on-off control, thereby improving the stability of the scanning signal Pscan1 output by the output terminal POUT of the second driving circuit 20.

[0101] In some embodiments, the tenth transistor T10 is a dual-gate transistor.

[0102] As an example, during the display period of a frame, the sixth node Q2 is a high potential signal for most of the time, and the fifth node P2 is a low potential signal for most of the time, that is, the scanning signal Pscan1 output by the output terminal POUT of the second driving circuit 20 is a high potential signal for most of the time. Setting the tenth transistor T10 as a dual-gate transistor helps to stably turn off the tenth transistor T10 when the sixth node Q2 is a high potential signal, thereby reducing the leakage current between the fifth node P2 and the sixth node Q2. This avoids the problem of abnormal scanning signal Pscan1 output by the output terminal POUT of the second driving circuit 20 caused by the high potential signal on the first potential line VGH being transmitted to the fifth node P2 due to insufficient closure of the tenth transistor T10.

[0103] Reference Fig.12 , the first gate layer may include a gate T6G of a sixth transistor T6, a gate T7G of a seventh transistor T7, a gate T8G of an eighth transistor T8, a gate T9G of a ninth transistor T9, a gate T10G of a tenth transistor T10, a gate T11G of an eleventh transistor T11, a gate T12G of a twelfth transistor T12, and a gate T13G of a thirteenth transistor T13. Among them, the gate T7G of the seventh transistor T7, the gate T8G of the eighth transistor T8, and the gate T11G of the eleventh transistor T11 extend along the first direction X. The gate T6G of the sixth transistor T6, the gate T9G of the ninth transistor T9, the gate T12G of the twelfth transistor T12, and the gate T13G of the thirteenth transistor T13 extend along the second direction Y. The tenth transistor T10 is a dual-gate structure, and its two gate branches T10G are parallel to each other and extend along the first direction X. The second gate layer includes a first plate of the second capacitor C2, a first plate of the third capacitor C3, and a first plate of the fourth capacitor C4. The third gate layer includes a second plate of the second capacitor C2, a second plate of the third capacitor C3, and a second plate of the fourth capacitor C4.

[0104] The gate T6G of the sixth transistor T6 and the gate T8G of the eighth transistor T8 are connected; the first electrode plate of the fourth capacitor C4 and the gate T7G of the seventh transistor T7 are connected to the fourth node K.

[0105] Reference Fig.12The sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12 and the thirteenth transistor T13 are P-type transistors, whose first electrodes may be sources and whose second electrodes may be drains. The first active layer includes an active portion formed by the first electrode T7S and the second electrode T7D of the sixth transistor T6, an active portion formed by the first electrode T6S and the second electrode T6D of the seventh transistor T7, an active portion formed by the first electrode T7S and the second electrode T7D of the seventh transistor T7, an active portion formed by the first electrode T8S and the second electrode T8D of the eighth transistor T8, an active portion formed by the first electrode T9S and the second electrode T9D of the ninth transistor T9, an active portion formed by the first electrode T10S and the second electrode T10D of the tenth transistor T10, an active portion formed by the first electrode T11S and the second electrode T11D of the eleventh transistor T11, an active portion formed by the first electrode T12S and the second electrode T12D of the twelfth transistor T12, and an active portion formed by the first electrode T13S and the second electrode T13D of the thirteenth transistor T13.

[0106] Since the ratio of the channel width to the channel length of the seventh transistor T7 is greater than that of the eleventh transistor T11 , the area of ​​the active portion of the seventh transistor T7 may be greater than that of the eleventh transistor T11 .

[0107] The active portion of the twelfth transistor T12 and the active portion of the thirteenth transistor T13 extend along the first direction X, and the active portion of the twelfth transistor T12 and the active portion of the thirteenth transistor T13 are connected. The active portions of the remaining transistors extend along the second direction Y. The active portions of the above transistors have overlapping portions with the gates of the corresponding transistors, and the overlapping portions are the channels of the corresponding transistors.

[0108] Combination Fig.10, the first source-drain layer includes a plurality of connectors; as an example, the third connector is respectively connected to the second electrode T6D of the sixth transistor T6, the second electrode T11D of the eleventh transistor T11, the gate T10G of the tenth transistor T10, and the first electrode T9S of the ninth transistor T9 through the via hole, so that the second electrode T6D of the sixth transistor T6, the second electrode T11D of the eleventh transistor T11, the first electrode T9S of the ninth transistor T9, and the gate T10G of the tenth transistor T10 located in the first gate layer are connected to the third node N. The fourth connector is respectively connected to the second electrode of the eighth transistor T8 and the first plate of the third capacitor C3 through the via hole, so that the second electrode of the eighth transistor T8 located in the first active layer and the second electrode and the third capacitor C3 located in the first gate layer are connected to the fourth node K. The fifth connection member is connected to the second electrode T10D of the tenth transistor T10, the gate T11G of the eleventh transistor T11, the second electrode T7D of the seventh transistor T7, the first plate of the third capacitor C3 and the gate T13G of the thirteenth transistor T13 through the via hole, so that the gate T11G of the eleventh transistor T11 and the gate T13G of the thirteenth transistor T13 located at the first gate layer, the gate T13G of the thirteenth transistor T13 located at the first active layer, the second electrode T7D of the seventh transistor T7 and the first plate of the third capacitor C3 are connected to the fifth node P2. The sixth connection member is connected to the second electrode T9D of the ninth transistor T9, the first plate of the second capacitor C2 and the gate T12G of the twelfth transistor T12 through the via hole, so that the gate T12G of the twelfth transistor T12 located at the first gate layer, the second electrode T9D of the ninth transistor T9 located at the first active layer and the first plate of the second capacitor C2 are connected to the sixth node Q2.

[0109] Combination Fig.11 The second source-drain layer includes a start line STV, a first potential line VGH, a second potential line VGL and a plurality of third clock lines CK3, wherein the plurality of third clock lines CK3 are CK31, CK32, CK33 and CK34 respectively; the number of third clock lines CK3 can be greater than four, for example, 6 or 8, so as to realize functions such as driving odd and even rows separately, which is not specifically limited here.

[0110] As an example, the first electrode T7S of the seventh transistor T7 and the second electrode plate of the fourth capacitor C4 can be connected to one of the third clock lines CK3 by means of a via. The gate T9G of the ninth transistor T9 can be connected to the second potential line VGL by means of a via. The first electrode T11S of the eleventh transistor T11 and the first electrode T10S of the tenth transistor T10 can be first connected to the first electrode T13S of the thirteenth transistor T13 through a connector of the first source-drain layer, and then the first electrode T11S of the eleventh transistor T11, the first electrode T10S of the tenth transistor T10, and the first electrode T13S of the thirteenth transistor T13 are connected to the first potential line VGH through a via between the first source-drain layer and the second source-drain layer.

[0111] In a second aspect, in one embodiment, the present application provides a display panel, including a pixel circuit and the above-mentioned gate driving device, wherein the gate driving device is used to drive the pixel circuit.

[0112] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0113] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0114] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A gate driving device, characterized in that: A signal line group and a plurality of first driving circuits connected in cascade; Each signal line in the signal line group extends along a first direction in a plan view of the gate driving device; The first driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a first capacitor; The first transistor, the second transistor and the third transistor are located in a first region in the plan view and are arranged along the first direction; The fourth transistor and the fifth transistor are located in the second region in the plan view and are arranged along the first direction; The first region, the second region, and the first capacitor are sequentially arranged along a second direction intersecting the first direction in the plan view.

2. The gate driving device according to claim 1, characterized in that: The signal line includes a clock line, a start line, a first potential line and a second potential line; The gate of the first transistor is connected to the clock line, the first electrode is connected to the start line, and the second electrode is connected to the first node; The second transistor has a gate connected to the first node, a first electrode connected to the first potential line, and a second electrode connected to a second node; The gate of the third transistor is connected to the first node, the first electrode is connected to the second potential line, and the second electrode is connected to the second node; The gate of the fourth transistor is connected to the first node, the first electrode is connected to the second potential line, and the second electrode is connected to the output end of the first driving circuit; The gate of the fifth transistor is connected to the second node, the first electrode is connected to the first potential line, and the second electrode is connected to the output end of the first driving circuit; One end of the first capacitor is connected to the first node, and the other end is connected to the output end of the first driving circuit; The first potential line and the second potential line cover the fourth transistor and the fifth transistor; the clock line and the start line are located on one side of the fourth transistor and the fifth transistor in the plan view.

3. The gate driving device according to claim 2, characterized in that: When the first driving circuit is used to output a threshold compensation signal or a first reset signal, a ratio of a channel width to a channel length of the fourth transistor and the fifth transistor is greater than a preset aspect ratio; wherein the preset aspect ratio is 40:

1.

4. The gate driving device according to claim 3, characterized in that: The clock line includes a first clock line, and the signal line further includes a first inverted clock line; The first clock line and the first inverted clock line are respectively located at two sides of the first region in the plan view.

5. The gate driving device according to claim 3, characterized in that: When the first driving circuit is used to output a light emitting control signal or a second reset signal, a ratio of a channel width to a channel length of the fourth transistor and the fifth transistor is smaller than the preset aspect ratio.

6. The gate driving device according to claim 5, characterized in that: The clock line includes a second clock line, and the signal line further includes a second inverted clock line; The second clock line, the second inverted clock line, and the start line are located on a side of the first region away from an output terminal of the first driving circuit in the plan view.

7. The gate driving device according to claim 1, characterized in that: Also included are a plurality of second drive circuits cascaded for outputting a scan signal, wherein the signal line includes a third clock line, a first potential line, and a second potential line; The second driving circuit includes a first transistor group, a second transistor group and an output sub-circuit; The first transistor group is connected to the third clock line, the second potential line and the output sub-circuit; The second transistor group is connected to the first potential line and the output sub-circuit; Wherein, the first transistor group includes a plurality of transistors located in the third region, and the plurality of transistors are arranged along the second direction in the plan view; The second transistor group includes a plurality of transistors located in a fourth region, and the plurality of transistors are arranged along the second direction in the plan view; the third region and the fourth region are arranged along the first direction, and there is a gap between the third region and the fourth region.

8. The gate driving device according to claim 7, characterized in that: The signal line includes a third inverted clock line; The first transistor group includes a sixth transistor, a seventh transistor and a ninth transistor; the second transistor group includes an eighth transistor, a tenth transistor and an eleventh transistor; the output sub-circuit includes a twelfth transistor and a thirteenth transistor; The gate of the sixth transistor is connected to the start line, the first electrode is connected to the second potential line, and the second electrode is connected to the third node; The gate of the seventh transistor is connected to the fourth node, the first electrode is connected to the third inverted clock line, and the second electrode is connected to the fifth node; The gate of the eighth transistor is connected to the start line, the first electrode is connected to the first potential line, and the second electrode is connected to the fourth node; The gate of the ninth transistor is connected to the second potential line, the first electrode is connected to the third node, and the second electrode is connected to the sixth node; The gate of the tenth transistor is connected to the third node, the first electrode is connected to the first potential line, and the second electrode is connected to the fifth node; The eleventh transistor has a gate connected to the fifth node, a first electrode connected to the first potential line, and a second electrode connected to the third node; The gate of the twelfth transistor is connected to the sixth node, the first electrode is connected to the third clock line, and the second electrode is connected to the scan signal output terminal of the second driving circuit; The gate of the thirteenth transistor is connected to the fifth node, the first electrode is connected to the second potential line, and the second electrode is connected to the scan signal output terminal; Among them, a plurality of the third clock lines cover the first transistor group and the second transistor group, and the third clock lines are arranged in sequence at equal intervals along the second direction; and the first potential line covers the output sub-circuit.

9. The gate driving device according to claim 8, characterized in that: A ratio of a channel width to a channel length of the seventh transistor is greater than a ratio of a channel width to a channel length of the eleventh transistor.

10. The gate driving device according to claim 8, characterized in that: The tenth transistor is a dual-gate transistor.

11. A display panel, characterized in that: It comprises a pixel circuit and a gate driving device as claimed in any one of claims 1 to 10, wherein the gate driving device is used to drive the pixel circuit.

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