Bearing table, alignment method, equipment, storage medium and program product

Abstract

The embodiment of the invention provides a bearing table, an alignment method and device, a storage medium and a program product. The detector is arranged above the carrying table and is used for acquiring multiple pieces of edge position data of a wafer relative to a first preset position of the carrying table; the processor is electrically connected with the detector and used for determining the position deviation between the second preset position and the first preset position of the wafer according to the multiple pieces of edge position data and generating an adjusting signal according to the position deviation, and the adjusting signal comprises a voltage value corresponding to the position deviation; and the adjusting assembly is connected with the carrying table, is electrically connected with the processor, bears the wafer in the adjusting process, and is used for generating a driving force for adjusting the pose of the wafer relative to the carrying table according to the voltage value contained in the adjusting signal. By adopting the technical scheme, the alignment precision between the wafer and the bearing table can be improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing technology, and in particular to a carrier, an alignment method, a device, a storage medium, and a program product. Background Art

[0002] In the semiconductor manufacturing process, wafers usually need to be transferred between different processing machines for processing. During the wafer transfer process, if the position of the wafer is offset, when the wafer is placed on the carrier, the position of the wafer on the carrier will also be offset, which will affect the processing quality of the wafer.

[0003] In this context, how to improve the alignment accuracy between the wafer and the carrier has become a technical problem that technical personnel in this field urgently need to solve. Summary of the invention

[0004] In view of this, embodiments of the present invention provide a carrier, an alignment method, an apparatus, a storage medium, and a program product, which can improve the alignment accuracy between a wafer and a carrier.

[0005] An embodiment of the present invention provides a carrying platform, including:

[0006] Carrier;

[0007] A detector, disposed above the stage, for acquiring a plurality of edge position data of a wafer relative to a first preset position of the stage;

[0008] a processor, electrically connected to the detector, for determining a position deviation between a second preset position of the wafer and the first preset position according to the plurality of edge position data, and generating an adjustment signal according to the position deviation, wherein the adjustment signal includes a voltage value corresponding to the position deviation;

[0009] An adjustment component is connected to the carrier and electrically connected to the processor, and during the adjustment process, carries the wafer and is used to generate a driving force for adjusting the position of the wafer relative to the carrier according to the voltage value included in the adjustment signal.

[0010] Optionally, there are multiple adjustment components, each of which is located at a different position above the carrier, wherein each adjustment component includes: a piezoelectric ceramic displacement module and a bearing module, wherein:

[0011] The carrying module is arranged above the carrier and is used to carry the wafer during the adjustment process;

[0012] The piezoelectric ceramic displacement module is disposed in the bearing module and is electrically connected to the processor, and is used to generate the driving force according to the voltage value to drive the bearing module to move.

[0013] Optionally, the processor is used to determine the coordinates of a second preset position of the wafer based on the plurality of edge position data, and use the difference between the coordinates of the second preset position of the wafer and the coordinates of the first preset position as the position deviation.

[0014] Optionally, the processor is used to determine the deviation direction and deviation value between the second preset position of the wafer and the first preset position according to the position deviation; determine a voltage value corresponding to the deviation value according to the deviation value; determine a driving direction corresponding to the voltage value according to the deviation direction; and generate the adjustment signal according to the voltage value and the driving direction corresponding to the voltage value.

[0015] Optionally, the processor is used to determine a voltage value corresponding to the deviation value according to a preset correspondence relationship between the deviation value and the driving voltage.

[0016] Optionally, the detector includes a plurality of grating components, each of which is disposed at a different position of the carrier and located above the wafer, wherein one grating component corresponds to one edge position data.

[0017] Optionally, the second preset position is the center of the wafer, and the first preset position is the center of the stage.

[0018] An embodiment of the present invention further provides an alignment method, which is applied to a carrier platform, wherein the carrier platform includes a carrier, and the alignment method includes:

[0019] Acquiring a plurality of edge position data of a wafer relative to a first preset position of the carrier;

[0020] Determining a position deviation between a second preset position of the wafer and the first preset position according to the plurality of edge position data;

[0021] An adjustment signal is generated according to the position deviation, wherein the adjustment signal includes a voltage value corresponding to the position deviation, and the voltage value is used to control the generation of a driving force for adjusting the position of the wafer relative to the carrier.

[0022] Optionally, determining the position deviation between the second preset position of the wafer and the first preset position according to the plurality of edge position data includes:

[0023] Determining the coordinates of a second preset position of the wafer according to the plurality of edge position data;

[0024] The difference between the coordinates of the second preset position of the wafer and the coordinates of the first preset position is used as the position deviation.

[0025] Optionally, generating an adjustment signal according to the position deviation includes:

[0026] Determining a deviation direction and a deviation value between a second preset position of the wafer and the first preset position according to the position deviation;

[0027] According to the deviation value, determining a driving voltage value corresponding to the deviation value;

[0028] Determining a driving direction corresponding to the driving voltage value according to the deviation direction;

[0029] The adjustment signal is generated according to the driving voltage value and the driving direction corresponding to the driving voltage value.

[0030] An embodiment of the present invention further provides a semiconductor device, comprising: a carrier platform as described in any of the above embodiments.

[0031] An embodiment of the present invention further provides a data processing device, comprising a memory and a processor, wherein the memory is suitable for storing one or more computer instructions, and when the processor runs the computer instructions, it executes the alignment method described in any of the above embodiments.

[0032] An embodiment of the present invention further provides a computer-readable storage medium storing computer instructions, which, when executed, execute the alignment method described in any of the aforementioned embodiments.

[0033] An embodiment of the present invention further provides a computer program product, comprising computer instructions, which, when executed by a processor, implement the alignment method described in any of the aforementioned embodiments.

[0034] In the carrier provided by the embodiment of the present invention, the detector is arranged above the carrier, so that the detector can obtain multiple edge position data of the wafer relative to the first preset position of the carrier, and the processor can determine the position deviation between the second preset position of the wafer and the first preset position based on the multiple edge position data, and then generate an adjustment signal including a voltage value corresponding to the position deviation based on the position deviation, so that during the adjustment process, the adjustment component can generate a driving force according to the voltage value included in the adjustment signal to adjust the driving force of the wafer carried by itself and the posture of the carrier. Since the position deviation reflects the current relative position of the wafer and the carrier, by applying a driving force to the wafer, the wafer and the carrier can have a preset posture, thereby improving the alignment accuracy between the wafer and the carrier, and thus improving the wafer processing quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments of the present invention or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0036] Figure 1 A schematic structural diagram of a carrier platform in an embodiment of the present invention is shown;

[0037] Figure 2 Shows Figure 1 A top view of the middle platform;

[0038] Figure 3 A flow chart of an alignment method in an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0039] As described in the background art, during the semiconductor manufacturing process, when the position of the wafer on the carrier table shifts, the processing quality of the wafer will be affected.

[0040] For example, during the photolithography exposure process, if the position of the wafer on the carrier is offset, a large overlay error will occur between the current layer pattern and the previous layer pattern formed on the wafer, which seriously affects the quality of the final semiconductor structure.

[0041] At present, in order to solve the problem of wafer position deviation caused by transmission error, multiple rework operations are required until the wafer is in the preset position, and then the corresponding processing technology is executed, which increases the processing time.

[0042] To solve the above technical problems, an embodiment of the present invention provides a carrier, and a detector is arranged above the carrier, so that the detector can obtain multiple edge position data of the wafer relative to the first preset position of the carrier, and the processor can determine the position deviation between the second preset position of the wafer and the first preset position according to the multiple edge position data, and then generate an adjustment signal including a voltage value corresponding to the position deviation according to the position deviation, so that during the adjustment process, the adjustment component can generate a driving force according to the voltage value included in the adjustment signal to adjust the driving force of the wafer carried by itself and the posture of the carrier. Since the position deviation reflects the current relative position of the wafer and the carrier, by applying a driving force to the wafer, the wafer and the carrier can have a preset posture, thereby improving the alignment accuracy between the wafer and the carrier, thereby improving the wafer processing quality; and there is no need for rework operations, thereby reducing the processing time.

[0043] In order to enable those skilled in the art to have a clearer understanding of the technical concepts, technical principles, advantages, etc. included in the embodiments of the present invention, the following exemplary descriptions are given through specific embodiments and in combination with specific application scenarios, with reference to the accompanying drawings.

[0044] See also Figure 1 and Figure 2 , Figure 1 is a structural schematic diagram of a carrier platform in an embodiment of the present invention, Figure 2 for Figure 1 The top view of the middle platform, such as Figure 1 and Figure 2 As shown, the carrier may include: a carrier 110; a detector 120, disposed above the carrier 110, for obtaining a plurality of edge position data of a wafer W relative to a first preset position of the carrier 110; a processor 140, electrically connected to the detector 120, for determining a position deviation between a second preset position of the wafer W and the first preset position according to the plurality of edge position data, and generating an adjustment signal according to the position deviation, wherein the adjustment signal includes a voltage value corresponding to the position deviation; an adjustment component 130, connected to the carrier 110 (it should be noted that Figure 1 and Figure 2 The specific connection method is not shown), and is electrically connected to the processor 140, and during the adjustment process, carries the wafer W, and is used to generate a driving force for adjusting the position of the wafer W relative to the carrier according to the voltage value included in the adjustment signal.

[0045] Combination Figure 1 and Figure 2 , the working mechanism of the carrier is:

[0046] When executing the processing technology for wafer W, through the detector 120 arranged above the stage 110 (as a non-limiting example, the detector 120 is embedded on the stage 110), multiple edge position data of the edge of wafer W relative to the first preset position of the stage 110 in the current state can be obtained, and the multiple edge position data can reflect the actual position of wafer W in the current state.

[0047] By electrically connecting the detector 120 to the processor 140, the processor 140 can obtain a plurality of edge position data, and then determine the coordinate information of the second preset position of the wafer W according to the plurality of edge position data through fitting and other methods. Based on the coordinate information of the second preset position and the coordinate information of the first preset position, the processor 140 can determine the position deviation, and then based on the position deviation, can generate an adjustment signal containing a voltage value corresponding to the position deviation, and output it to the adjustment component 130, so that the adjustment component 130 can generate a driving force in response to the voltage value contained in the adjustment signal, and under the action of the driving force, the posture of the wafer W changes, so that the wafer W and the carrier 110 have a preset posture, and the alignment accuracy between the wafer W and the carrier is improved, thereby improving the processing quality of the wafer W.

[0048] It should be noted that Figure 1 and Figure 2 The structure of the carrier platform and the relative position relationship between the various components are shown for illustrative purposes only and are a simplified description for adjusting the relative posture of the wafer W and the carrier platform 110 through the cooperation among the processor 140, the detector 120 and the adjustment assembly 130. It does not indicate or imply that the carrier platform in the present invention must have a specific orientation and / or be constructed in a specific orientation. Therefore, it should not be understood as a limitation to the present invention.

[0049] In this embodiment, the carrier 110 is used to carry the wafer W during the processing process (which can be considered as other processes other than the adjustment process).

[0050] In a specific embodiment, the carrier 110 has a carrying surface 111 for carrying the wafer W, and the carrying surface 111 has a through hole G, and a lifting component (eg, Figure 1 The wafer W can be placed on the carrying surface 111 of the carrier 110 by the lifting components P1, P2 and P3, and the wafer W can also be removed from the carrying surface.

[0051] For example, when wafer W is transferred to a processing chamber by a robot arm, or when posture calibration is completed, the lifting components P1, P2 and P3 can drive wafer W to move toward one side of the carrier 110, so that wafer W can be placed on the carrier 110; for another example, when the processing process is completed, the lifting components P1, P2 and P3 can drive wafer W to move toward a side away from the carrier 110 to remove wafer W from the carrier 110.

[0052] It should be noted that, first, Figure 1 and Figure 2 The shapes of the lifting components P1, P2 and P3, the stage 110 and the through hole G are only for illustration; second, Figure 1 and Figure 2 The sizes of the lifting components P1, P2 and P3 and the through hole G are only for illustration. In this embodiment, as long as the size of the through hole G is larger than the size of the lifting components P1, P2 and P3; thirdly, the distribution position of the through hole G on the carrier 110 is only for illustration and cannot be understood as a limitation on the embodiment of the present invention.

[0053] The detector 120 is used to obtain a plurality of edge position data of the edge of the wafer W relative to a first preset position of the stage 110 .

[0054] In this embodiment, the first preset position may be the center of the carrier 110, so that it is convenient to obtain the relative position information (ie, edge position data) between the edge of the wafer W and the first preset position of the carrier 110, so as to quickly align the wafer W with the carrier.

[0055] In some other embodiments, the first preset position may be a position other than the center, and the embodiment of the present invention does not impose any limitation on this.

[0056] In this embodiment, the detector 120 may include a plurality of grating components (as a non-limiting example, the detector 120 may include Figure 2 As shown in the figure, each grating component is arranged at a different position of the carrier 110 and is located above the wafer W, wherein one grating component corresponds to one edge position data.

[0057] Specifically, the grating components are located at different positions of the stage 110 (as a non-limiting example, the grating components 121, 122, 123 and 124 can be symmetrically arranged along the center of the stage 110, for example Figure 2 The four corners are shown in the figure. In some other embodiments, the grating components 121, 122, 123 and 124 can also be set at other positions). The grating components can cover the edge of the wafer W at different positions, so that each grating component can obtain edge position data at that position.

[0058] The grating assembly is based on the principle of photoelectric encoding and consists of a transparent glass engraved with hundreds to thousands of parallel grating lines and a receiver. When the light source shines on the grating, the light is reflected or transmitted by the grating lines. The receiver is located opposite the grating and can detect the change in light. By measuring the characteristics of the reflected or transmitted light, the grating assembly can obtain edge position data.

[0059] In this embodiment, the detection accuracy of the grating component can reach the micron level. By adopting the micron-level grating component, multiple edge position data of the edge of the wafer W relative to the first preset position of the carrier 110 can be more accurately detected, which is beneficial to improving the alignment accuracy of the wafer W and the carrier 110.

[0060] It should be noted that, first, Figure 2 The positions and numbers of the illustrated grating components are for illustrative purposes only, and are used to indicate that edge position data can be obtained by setting up detection devices, and should not be construed as limiting the embodiments of the present invention. It can be expected that the greater the number of grating components, the higher the accuracy of the position deviation obtained by subsequent calculation; second, in some other embodiments, the detector may also be an interferometer or other device or equipment with a ranging function; third, in this embodiment, the edge position data can be obtained by putting the wafer in motion.

[0061] In this embodiment, the processor 140 is a general term for a class of devices or equipment with data processing capabilities. For example, the processor 140 can be implemented by a processing chip such as a central processing unit (CPU), a field programmable gate array (FPGA), or a single-chip microcomputer.

[0062] In this embodiment, the processor 140 can be used to determine the coordinates of the second preset position of the wafer based on the multiple edge position data, and use the difference between the coordinates of the second preset position of the wafer W and the coordinates of the first preset position as the position deviation.

[0063] Among them, the second preset position of wafer W can refer to the center of wafer W. The center of wafer W is usually the symmetry center of the features or patterns on wafer W. By taking the center as the second preset position, the measurement error caused by asymmetry or offset can be reduced, thereby improving the measurement accuracy.

[0064] Specifically, the edge position data reflects the current position of the edge of wafer W. Through multiple different edge position data, fitting processing and other operations can be performed to fit the current position profile of wafer W, so that the center (i.e., the second preset position) coordinates of wafer W can be determined. Then, by comparing the difference between the two centers, the deviation between the position of wafer W in the current state and the actual position, i.e., the position deviation, can be determined. Based on the position deviation, the posture of wafer W in the current state can be adjusted.

[0065] In this embodiment, based on the different positions of the wafer, the size and direction of the obtained position deviation may be different. In this way, after determining the position deviation based on the edge position data, the processor 140 can determine the deviation direction and deviation value between the second preset position and the first preset position of the wafer according to the position deviation; and then determine the voltage value corresponding to the deviation value according to the deviation value; and determine the driving direction corresponding to the voltage value according to the deviation direction; and generate the adjustment signal according to the voltage value and the driving direction corresponding to the voltage value.

[0066] In other words, the position deviation is a vector with directionality and magnitude, wherein the directionality indicates the current offset direction of wafer W relative to the preset position, and the direction in which wafer W needs to move during subsequent posture adjustment; the magnitude indicates the current degree of offset of wafer W relative to the preset position, which determines how much voltage adjustment the processor 140 needs to generate so that wafer W is driven exactly to the preset position.

[0067] More specifically, once the deviation direction and the deviation value are determined, the voltage value and the direction in which the voltage value acts can be determined.

[0068] For example, assuming that the coordinates of the center of the carrier are (0, 0) and the position deviation is (+2, +3), then relative to the center of the carrier, the wafer W is located at the upper right position (where +2 is the deviation in the first direction, +3 is the deviation in the second direction, and the first direction and the second direction are perpendicular). When the adjustment signal is generated, the adjustment direction is opposite to the first direction and the second direction, so that the wafer W can be located at the preset position.

[0069] In this embodiment, the processor 140 may be configured to determine a voltage value corresponding to the deviation value according to a preset correspondence relationship between the deviation value and the driving voltage.

[0070] Specifically, when the processor 140 determines the position deviation, it can automatically obtain the voltage value corresponding to the position deviation based on the correspondence between the deviation value and the driving voltage stored internally, without manual processing, which can improve the calculation efficiency and the accuracy of the calculated voltage value.

[0071] In some optional embodiments, the corresponding relationship between the deviation value and the driving voltage can be obtained in the following manner:

[0072] Determine the position deviation of the wafer at any position, and select at least one voltage value that can make the wafer at a preset position by outputting adjustment signals with different voltage values; then change the position of the wafer multiple times, and obtain the position deviation of the wafer at different positions, and determine the voltage value corresponding to each position deviation, wherein the voltage value enables the wafer to be at the preset position, so that multiple voltage values ​​and position deviations with corresponding relationships can be obtained, and then various different calculation methods such as fitting processing are used to determine the corresponding relationship between the deviation value and the driving voltage.

[0073] In this embodiment, as mentioned above, the position deviation has directionality and size, so during the actual adjustment process, the adjustment component may need to apply forces for driving the wafer to move in different directions.

[0074] Based on this, see Figure 1 and Figure 2 There are multiple adjustment components, and each adjustment component is located at a different position above the carrier.

[0075] As a non-limiting example, the carrier may include two adjustment components, and the two adjustment components are relatively arranged above the carrier 110. It can be understood that the more the number of adjustment components is, the higher the adjustment accuracy is. For example, in some embodiments, the carrier may include four adjustment components, and the four adjustment components are symmetrically arranged above the carrier 110.

[0076] In a non-limiting example, the number of adjustment components is the same as the number of grating components, and the grating component is located between any two adjustment components, or the adjustment components and the grating components are arranged in an alternating sequence.

[0077] In this embodiment, the structures of the various adjustment components are the same, and each adjustment component may include: a piezoelectric ceramic displacement module 131 and a bearing module 132, wherein:

[0078] The carrying module 132 is disposed above the carrier 100 and is used to carry the wafer W during the adjustment process;

[0079] The piezoelectric ceramic displacement module 131 is disposed in the support module 132 and is electrically connected to the processor 140 , and is used to generate the driving force according to the voltage value to drive the support module 132 to move.

[0080] Specifically, the piezoelectric ceramic displacement module 131 is fixed above the carrier 110, and the bearing module 132 is connected to the piezoelectric ceramic displacement module 131, so that when one of the adjustment components obtains the adjustment signal from the processor 140, the piezoelectric ceramic displacement module 131 can be extended and retracted according to the voltage value in the adjustment signal, thereby generating a driving force. Driven by the driving force, the bearing module 132 can drive the wafer W to move to change the relative posture between the wafer W and the carrier.

[0081] In this embodiment, Figure 2 As shown, the piezoelectric ceramic displacement module 131 has three piezoelectric ceramic displacement modules arranged in one carrier module 132. For example, the piezoelectric ceramic displacement modules 1311, 1312 and 1313 are arranged in one of the carrier modules 132; for another example, the piezoelectric ceramic displacement modules 1314, 1315 and 1316 are arranged in another carrier module 132.

[0082] It should be noted that in the actual adjustment process, an adjustment signal may include multiple sub-adjustment signals, and one sub-adjustment signal corresponds to a voltage value and a direction corresponding to the voltage value. The wafer posture can be adjusted by outputting multiple sub-adjustment signals to the corresponding adjustment components simultaneously or in time-sharing.

[0083] For example, if the coordinates of the carrier are (0, 0) and the position deviation is (+2, +3), the adjustment signal generated by the processor may include at least two sub-adjustment signals (for example, a first sub-adjustment signal and a second sub-adjustment signal), and output the first sub-adjustment signal to the first adjustment component, and output the second sub-adjustment signal to the second adjustment component. In this way, the wafer can be adjusted to move in a direction opposite to the first direction so that the deviation "+2" in the first direction becomes "0", and the wafer can be adjusted to move in a direction opposite to the second direction so that the deviation "+3" in the second direction becomes "0".

[0084] More specifically, the wafer position adjustment process can be: first change the deviation "+2" in the first direction to "0", and then change the deviation "+3" in the second direction to "0"; or, first change the deviation "+3" in the second direction to "0", and then change the deviation "+2" in the first direction to "0"; or, move the wafer at the same time so that the position deviation (+2, +3) becomes (0, 0).

[0085] In this embodiment, the piezoelectric ceramic displacement module 131 may be composed of a plurality of piezoelectric ceramics, and the piezoelectric ceramics are driven to expand or compress to change the position of the wafer. When the driving voltage value of the adjustment signal changes in a positive direction (from small to large), the piezoelectric ceramic may expand (i.e., stretch), or when the driving voltage value of the adjustment signal changes in a negative direction (from large to small), the piezoelectric ceramic may be compressed (i.e., contracted), so that the wafer moves toward or away from the center area of ​​the carrier.

[0086] In this embodiment, the movement accuracy of the piezoelectric ceramic displacement module can reach the nanometer level (greater than the micron level accuracy of the gate component). By adopting the nanometer-level piezoelectric ceramic displacement module, the position of the wafer W relative to the carrier 110 can be adjusted more finely, which is beneficial to improving the alignment accuracy of the wafer W and the carrier 110.

[0087] In this embodiment, a suction port (such as Figure 1 As shown in the dotted box K), by setting the adsorption port K, the gas at the contact point between the carrying module and the wafer can be sucked, so that the wafer is firmly adsorbed on the carrying surface of the carrying module, avoiding the problem of the wafer slipping during the adjustment process.

[0088] An embodiment of the present invention further provides an alignment method, which can be applied to a carrier platform, and the carrier platform can include a carrier. The following is an illustrative description through specific examples with reference to the accompanying drawings.

[0089] See also Figure 3 A flowchart of an alignment method in an embodiment of the present invention is shown in FIG. Figure 3 As shown, the following steps can be performed:

[0090] S11, acquiring a plurality of edge position data of a wafer relative to a first preset position of the carrier.

[0091] Specifically, the edge position data can reflect the current position of the wafer, so by acquiring multiple edge position data, the current state of the wafer can be confirmed, and then according to the multiple edge position data, the corresponding alignment strategy can be determined.

[0092] In this embodiment, the first preset position may be the center of the carrier, which facilitates obtaining the relative position information (ie, edge position data) between the edge of the wafer and the first preset position of the carrier, so as to quickly achieve alignment between the wafer and the carrier.

[0093] In some other embodiments, the first preset position may be a position other than the center, and the embodiment of the present invention does not impose any limitation on this.

[0094] S12, determining a position deviation between a second preset position of the wafer and the first preset position according to the plurality of edge position data.

[0095] Among them, the second preset position of the wafer can refer to the center of the wafer W. The center of the wafer is usually the symmetry center of the features or patterns on the wafer. By taking the center as the second preset position, the measurement error caused by asymmetry or offset can be reduced, thereby improving the measurement accuracy.

[0096] Specifically, the edge position data reflects the current position of the edge of the wafer. Through multiple different edge position data, fitting processing and other operations can be performed to fit the current position contour of the wafer, so that the center (i.e., the second preset position) coordinates of the wafer can be determined, and then by comparing the difference between the two centers, the deviation between the position of wafer W in the current state and the actual position, i.e., the position deviation, can be determined. Based on the position deviation, the posture of wafer W in the current state can be adjusted.

[0097] In this embodiment, step S12 may include:

[0098] The coordinates of the second preset position of the wafer are determined according to the plurality of edge position data.

[0099] Specifically, based on a plurality of edge position data, a fitting circle characterizing the current trajectory of the wafer can be determined, and through the fitting circle, the position information of any point on the wafer can be determined, including the coordinates of the second preset position.

[0100] The difference between the coordinates of the second preset position of the wafer and the coordinates of the first preset position is used as the position deviation.

[0101] S13, generating an adjustment signal according to the position deviation, wherein the adjustment signal includes a voltage value corresponding to the position deviation, and the voltage value is used to control the generation of a driving force for adjusting the position of the wafer relative to the carrier.

[0102] Specifically, the position deviation is a vector with directionality and magnitude. The directionality indicates the current offset direction of the wafer relative to the preset position, as well as the direction in which the wafer needs to move during subsequent posture adjustments. The magnitude indicates the current degree of offset of the wafer relative to the preset position, which determines the voltage value in the adjustment signal. Therefore, the adjustment signal obtained based on the position deviation can drive the wafer exactly to the preset position.

[0103] In this embodiment, based on the different positions of the wafer, the size and direction of the obtained position deviation may be different. In this way, after determining the position deviation based on the edge position data, the deviation direction and deviation value between the second preset position and the first preset position of the wafer can be determined according to the position deviation; and then, based on the deviation value, the voltage value corresponding to the deviation value can be determined; and based on the deviation direction, the driving direction corresponding to the voltage value can be determined; and the adjustment signal can be generated according to the voltage value and the driving direction corresponding to the voltage value.

[0104] In this embodiment, the voltage value corresponding to the deviation value may be determined according to a preset correspondence relationship between the deviation value and the driving voltage.

[0105] Specifically, when determining the position deviation, the voltage value corresponding to the position deviation can be automatically obtained based on the correspondence between the pre-stored deviation value and the driving voltage without manual processing, which can improve the calculation efficiency and the accuracy of the calculated voltage value.

[0106] In some optional embodiments, the corresponding relationship between the deviation value and the driving voltage can be obtained in the following manner:

[0107] Determine the position deviation of the wafer at any position, and select at least one voltage value that can make the wafer at a preset position by outputting adjustment signals with different voltage values; then change the position of the wafer multiple times, and obtain the position deviation of the wafer at different positions, and determine the voltage value corresponding to each position deviation, wherein the voltage value enables the wafer to be at the preset position, so that multiple voltage values ​​and position deviations with corresponding relationships can be obtained, and then various different calculation methods such as fitting processing are used to determine the corresponding relationship between the deviation value and the driving voltage.

[0108] In this embodiment, as mentioned above, the position deviation has directionality and size, so during the actual adjustment process, the adjustment component may need to apply forces for driving the wafer to move in different directions.

[0109] Specifically, in the actual adjustment process, an adjustment signal may include multiple sub-adjustment signals, and one sub-adjustment signal corresponds to a voltage value and a direction corresponding to the voltage value. The wafer posture can be adjusted by outputting multiple sub-adjustment signals to the corresponding adjustment components simultaneously or in time-sharing.

[0110] For example, if the coordinates of the carrier are (0, 0) and the position deviation is (+2, +3), the adjustment signal generated by the processor may include at least two sub-adjustment signals (for example, a first sub-adjustment signal and a second sub-adjustment signal), and output the first sub-adjustment signal to the first adjustment component, and output the second sub-adjustment signal to the second adjustment component. In this way, the wafer can be adjusted to move in a direction opposite to the first direction so that the deviation "+2" in the first direction becomes "0", and the wafer can be adjusted to move in a direction opposite to the second direction so that the deviation "+3" in the second direction becomes "0".

[0111] More specifically, the wafer position adjustment process can be: first change the deviation "+2" in the first direction to "0", and then change the deviation "+3" in the second direction to "0"; or, first change the deviation "+3" in the second direction to "0", and then change the deviation "+2" in the first direction to "0"; or, move the wafer at the same time so that the position deviation (+2, +3) becomes (0, 0).

[0112] An embodiment of the present invention provides a semiconductor device, which may include the carrier described in any of the above examples.

[0113] In a specific embodiment, the semiconductor device may be a photolithography machine, and the carrier may carry or drive the wafer to move during the photolithography process.

[0114] An embodiment of the present invention provides a data processing device, which may include a memory and a processor. The memory and the processor may communicate with each other through a communication bus. The memory stores one or more computer instructions that can be run on the processor. When the processor runs the computer instructions, the alignment method described in any of the above embodiments may be executed. For details, please refer to the above-mentioned related content and will not be repeated here.

[0115] In some examples, computer instructions may include any suitable type of code, e.g., source code, compiled code, interpreted code, executable code, static code, dynamic code, encrypted code, etc., implemented using any suitable high-level, low-level, object-oriented, visual, compiled and / or interpreted programming language.

[0116] In some examples, the data processing device may further include a display interface and a display connected through the display interface. The display interface may communicate with the memory and the processor through a communication bus. The display may display the position deviation obtained by the processor executing the alignment method provided in the embodiment of the present invention.

[0117] In some embodiments, the data processing device may further include a data output interface. The data output interface may communicate with the memory and the processor via a communication bus to output various data in the mask alignment process.

[0118] The present invention also provides a computer-readable storage medium on which computer instructions are stored. When the computer instructions are executed, the alignment method described in any of the above embodiments of the present invention can be executed. For details, please refer to the above related content and will not be repeated here.

[0119] Among them, the computer-readable storage medium may include any suitable type of memory unit, memory device, memory article, memory medium, storage device, storage article, storage medium and / or storage unit. For example, memory, removable or non-removable medium, erasable or non-erasable medium, writable or rewritable medium, digital or analog medium, hard disk, floppy disk, compact disk read-only memory (CDROM), compact disk recordable (CD-R), compact disk rewritable (CD-RW), optical disk, magnetic medium, magneto-optical medium, removable memory card or disk, various types of digital versatile disks (DVD), magnetic tape, cassette tape, etc. Moreover, the computer instructions may include any suitable type of code implemented by using any suitable high-level, low-level, object-oriented, visual, compiled and / or interpreted programming language, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, encrypted code, etc.

[0120] The present invention also provides a computer program product, which may include computer instructions. When the computer instructions are executed by a processor, the alignment method described in any of the above embodiments of the present invention is implemented. For details, please refer to the above-mentioned related content and will not be repeated here.

[0121] It is understood that the terms "first", "second", etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined by the terms "first", "second", etc. may explicitly or implicitly include one or more of the features. Moreover, the terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or indicate importance. It is understood that the terms used in this way are interchangeable where appropriate so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein.

[0122] Although the embodiments of this specification are disclosed as above, the invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention, so the protection scope of the invention shall be subject to the scope defined by the claims.

Claims

1. A carrying platform, characterized in that: include: Carrier; A detector, disposed above the stage, for acquiring a plurality of edge position data of a wafer relative to a first preset position of the stage; a processor, electrically connected to the detector, for determining a position deviation between a second preset position of the wafer and the first preset position according to the plurality of edge position data, and generating an adjustment signal according to the position deviation, wherein the adjustment signal includes a voltage value corresponding to the position deviation; An adjustment component is connected to the carrier and electrically connected to the processor, and during the adjustment process, carries the wafer and is used to generate a driving force for adjusting the position of the wafer relative to the carrier according to the voltage value included in the adjustment signal.

2. The carrying platform according to claim 1, characterized in that: There are multiple adjustment components, each of which is located at a different position above the carrier, wherein each adjustment component includes: a piezoelectric ceramic displacement module and a bearing module, wherein: The carrying module is arranged above the carrier and is used to carry the wafer during the adjustment process; The piezoelectric ceramic displacement module is disposed in the bearing module and is electrically connected to the processor, and is used to generate the driving force according to the voltage value to drive the bearing module to move.

3. The carrying platform according to claim 1, characterized in that: The processor is used to determine the coordinates of the second preset position of the wafer according to the plurality of edge position data, and use the difference between the coordinates of the second preset position of the wafer and the coordinates of the first preset position as the position deviation.

4. The carrying platform according to claim 1, characterized in that: The processor is used to determine the deviation direction and deviation value between the second preset position of the wafer and the first preset position according to the position deviation; and determine the voltage value corresponding to the deviation value according to the deviation value; Determining a driving direction corresponding to the voltage value according to the deviation direction; The adjustment signal is generated according to the voltage value and the driving direction corresponding to the voltage value.

5. The carrying platform according to claim 4, characterized in that: The processor is used to determine a voltage value corresponding to the deviation value according to a preset correspondence relationship between the deviation value and the driving voltage.

6. The carrying platform according to claim 1, characterized in that: The detector includes a plurality of grating components, each of which is disposed at a different position of the carrier and located above the wafer, wherein one grating component corresponds to one edge position data.

7. The carrying platform according to claim 1, characterized in that: The second preset position is the center of the wafer, and the first preset position is the center of the stage.

8. An alignment method, applied to a carrier platform, characterized in that: The carrier platform includes a carrier platform, and the alignment method includes: Acquiring a plurality of edge position data of a wafer relative to a first preset position of the carrier; Determining a position deviation between a second preset position of the wafer and the first preset position according to the plurality of edge position data; An adjustment signal is generated according to the position deviation, wherein the adjustment signal includes a voltage value corresponding to the position deviation, and the voltage value is used to control the generation of a driving force for adjusting the position of the wafer relative to the carrier.

9. The alignment method according to claim 8, characterized in that: Determining the position deviation between the second preset position of the wafer and the first preset position according to the plurality of edge position data includes: Determining the coordinates of a second preset position of the wafer according to the plurality of edge position data; The difference between the coordinates of the second preset position of the wafer and the coordinates of the first preset position is used as the position deviation.

10. The alignment method according to claim 8, characterized in that: The step of generating an adjustment signal according to the position deviation comprises: Determining a deviation direction and a deviation value between a second preset position of the wafer and the first preset position according to the position deviation; According to the deviation value, determining a driving voltage value corresponding to the deviation value; Determining a driving direction corresponding to the driving voltage value according to the deviation direction; The adjustment signal is generated according to the driving voltage value and the driving direction corresponding to the driving voltage value.

11. A semiconductor device, characterized in that: include: A support platform as claimed in any one of claims 1 to 7.

12. A data processing device, characterized in that: The device comprises a memory and a processor, wherein the memory is suitable for storing one or more computer instructions, and when the processor runs the computer instructions, the alignment method according to any one of claims 8 to 10 is executed.

13. A computer-readable storage medium, characterized in that: Computer instructions are stored, and when the computer instructions are executed, the alignment method according to any one of claims 8 to 10 is executed.

14. A computer program product, characterized in that The method comprises computer instructions, which, when executed by a processor, implement the alignment method according to any one of claims 8 to 10.

Images