Ceramic packaged digital isolator product structure and chip isolation structure manufacturing method

Abstract

The invention relates to a ceramic-packaged digital isolator product structure and a chip isolation structure manufacturing method, the digital isolator product structure aims at solving the high-voltage isolation problem of a ceramic-packaged digital isolator and improving the reliability of the ceramic-packaged digital isolator, and the digital isolator product structure comprises a digital isolator chip and a shell, the substrate of the digital isolator chip is a semiconductor silicon wafer, and meanwhile, the digital isolator chip is provided with metal pressure bonding pads at the input end and the output end of the receiver chip and the transmitter chip; and the shell and the digital isolator chip are provided with insulating glue. In the digital isolator product structure provided by the invention, only the PAD spacing of the chips for designing the isolator is increased, so that the problem of voltage resistance between the input end and the output end of the isolator manufactured by the existing semiconductor silicon wafer process is solved; and meanwhile, the insufficiency of insulation and voltage resistance of the digital isolator manufactured by the semiconductor silicon wafer process can be solved by adopting the existing silicon wafer process line and chip.

Description

Technical Field

[0001] The present invention relates to the technical field of digital isolator packaging, and in particular to a ceramic packaged digital isolator product structure and a chip isolation structure manufacturing method. Background Art

[0002] Most of the existing digital isolators use plastic packages injected with epoxy molding compounds. In humid environments or under temperature cycles and high temperatures, the difference in thermal expansion coefficients between the molding compounds and different materials (chips, frames, bonding wires) can lead to device delamination, leakage, reduced isolation voltage resistance and other problems. Some products use ceramic packages. To improve the isolation voltage resistance, potting glue is introduced to wrap the PAD and chip periphery of the digital isolator chip to solve the problem of use in humid environments. However, in environments with large environmental changes such as aviation, aerospace, and missiles, large mechanical stress will lead to bonding reliability problems.

[0003] In order to achieve the isolation and voltage resistance requirements, if the digital isolator chip in the air-sealed ceramic package is made using a mature silicon wafer process line, it is necessary to increase the distance from the input and output ends of all digital isolator chips to the side of the chip (the exposed part of the semiconductor silicon wafer) to eliminate surface creepage, leakage, and substrate breakdown through the semiconductor silicon. However, this will cause the digital isolator chip to increase in size beyond the design requirements and cannot be received. Summary of the invention

[0004] To this end, the technical problem to be solved by the present invention is to overcome the problem in the prior art that wind turbines are easily affected by sea conditions, resulting in low construction efficiency, thereby providing a manufacturing method for a simple trolley bearing device that is less affected by sea conditions and can ensure the overall stability of the wind turbine to the greatest extent.

[0005] In order to solve the above technical problems, the present invention provides a ceramic packaged digital isolator product structure, which specifically solves the high-voltage isolation problem of ceramic packaged digital isolators and improves the reliability of ceramic packaged digital isolators. The digital isolator product structure comprises a digital isolator chip and a shell. The substrate of the digital isolator chip is a semiconductor silicon wafer, and the digital isolator chip is provided with input and output metal pads of a receiver chip and a transmitter chip. The shell and the digital isolator chip are provided with insulating glue for bonding and connecting, and the insulating glue is also used to bond the receiver chip and the transmitter chip to the digital isolator chip.

[0006] In one embodiment of the present invention, the digital isolator chip is made of semiconductor silicon wafer, which is thinned by 100 μm. The isolator chip is bonded to the housing with insulating glue, and the insulating glue is required to overflow and wrap around the digital isolator chip.

[0007] In one embodiment of the present invention, after the digital isolator chip is attached to the housing, a cover plate is installed on the top of the housing.

[0008] In one embodiment of the present invention, the receiver chip and the transmitter chip are connected to the digital isolator chip through bonding wires, and then capped to form a digital isolator product.

[0009] The present invention also provides a method for preparing a digital isolator chip isolation structure, comprising the following steps:

[0010] Step S1: First, according to the technical documents of product isolation withstand voltage requirements, the primary and secondary PAD spacing of the isolator chip is designed, and the digital isolator chip is manufactured based on a semiconductor silicon wafer and a polyimide process line;

[0011] Step S2: Secondly, the digital isolator wafer is thinned to 100 μm and diced with a 30 μm thick blade;

[0012] Step S3: Then, the digital isolator chip is bonded to the housing with insulating glue, the receiver chip and the transmitter chip are bonded to the digital isolator chip with insulating glue, and then the chips are interconnected with bonding wires, baked, capped, and formed.

[0013] The above technical solution of the present invention has the following advantages over the prior art: in the digital isolator product structure described in the present invention, the chip of the isolator is designed by only increasing the chip PAD spacing, thereby solving the voltage resistance problem between the input and output ends of the isolator manufactured by the existing semiconductor silicon wafer process, without the need to redesign the receiver isolator chip and the transmitter chip, and meeting the ceramic packaging requirements; at the same time, the existing silicon wafer process line and chip can be used to solve the insufficient insulation voltage resistance of the digital isolator manufactured by the semiconductor silicon wafer process, thereby reducing the investment and production cost of the digital isolator manufacturing, and at the same time, the ceramic package does not need to be potted, and the digital isolator can work stably for a long time in harsh environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0015] Figure 1 is a top view of the digital isolator chip of the present invention;

[0016] Figure 2 It is a schematic diagram of the product structure of the digital isolator in ceramic package in the present invention;

[0017] Figure 3 It is a top view bonding schematic diagram of the digital isolator product structure of the ceramic package of the present invention.

[0018] In the figure: 1. Housing; 2. Insulation glue; 3. Digital isolator chip; 4. Receiver chip; 5. Transmitter chip; 6. Bonding wire; 7. Cover plate. DETAILED DESCRIPTION

[0019] Embodiment 1

[0020] like Figure 1 and Figure 2 As shown, this embodiment provides a digital isolator product structure of a ceramic package, which specifically solves the high-voltage isolation problem of the digital isolator of the ceramic package and improves the reliability of the ceramic-sealed digital isolator, including a digital isolator chip 3 and a housing 1. The substrate of the digital isolator chip 3 is a semiconductor silicon wafer, and the digital isolator chip 3 is provided with input and output metal pads of the receiver chip 4 and the transmitter chip 5; the housing 1 and the digital isolator chip 3 are provided with insulating glue 2 for bonding and connecting, and the insulating glue 2 is also used to bond the receiver chip 4 and the transmitter chip 5 to the digital isolator chip 3.

[0021] The digital isolator chip 3 is made of semiconductor silicon wafer, thinned by 100 μm, and the isolator chip 3 is bonded to the housing 1 with insulating glue 2, and the insulating glue is required to overflow and wrap around the digital isolator chip 3. The isolator chip 3 is designed according to product requirements, and the PAD spacing between the isolator input and output ends is increased.

[0022] Specifically, the isolator chip 3 is thinned to 100 μm, and the isolator chip is bonded to the inside of the tube shell cavity by using the insulating glue 2. The insulating glue 2 overflows and covers the isolator chip 3 all around to prevent the isolator chip 3 from being broken through the substrate.

[0023] like Figure 2 and Figure 3 As shown, after the digital isolator chip 3 is pasted to the housing 1, a cover plate 7 is provided on the top of the housing 1 for assembly.

[0024] The receiver chip 4 and the transmitter chip 5 are connected to the digital isolator chip 3 via bonding wires 6 and then capped to form a digital isolator product.

[0025] The chip of the isolator designed in this embodiment only increases the chip PAD spacing, solving the voltage resistance problem between the input and output ends of the isolator manufactured by the existing semiconductor silicon wafer process. There is no need to redesign the receiver isolator chip and the transmitter chip, and ceramic packaging requirements are met.

[0026] The digital isolator product structure described in this embodiment includes a digital isolator chip manufactured by semiconductor silicon wafer process and a digital isolator circuit package. The present invention adopts the existing silicon wafer process line and chip to solve the problem of insufficient insulation withstand voltage of the digital isolator manufactured by semiconductor silicon wafer process, reduces the investment and production cost of digital isolator manufacturing, and the ceramic package does not need to be potted, so the digital isolator can work stably for a long time in harsh environment.

[0027] Embodiment 2

[0028] This embodiment provides a method for preparing a digital isolator chip isolation structure, comprising the following steps:

[0029] Step S1: First, according to the technical documents of product isolation withstand voltage requirements, the primary and secondary PAD spacing of the isolator chip is designed, and the digital isolator chip is manufactured based on a semiconductor silicon wafer and a polyimide process line;

[0030] Step S2: Secondly, the digital isolator wafer is thinned to 100 μm and diced with a 30 μm thick blade;

[0031] Step S3: Then, the digital isolator chip 3 is bonded to the housing 1 using insulating glue 2, the receiver chip 4 and the transmitter chip 5 are bonded to the digital isolator chip 2 using insulating glue 2, and then the chips are interconnected with bonding wires 7, baked, capped, and formed.

[0032] In the chip isolation structure preparation method described in the present embodiment, only the PAD spacing of the digital isolator chip is increased, and there is no need to redesign the receiver chip and the transmitter chip. The digital isolator chip is wrapped around by overflowing insulating glue to prevent the isolator chip from breaking through the substrate. There is no need to use potting glue to wrap the bonding wire and the PAD, which solves the high-voltage isolation problem of the ceramic-packaged digital isolator and improves the reliability of the ceramic-packaged digital isolator.

[0033] Furthermore, in actual use, the pad spacing is 1.5mm, and the substrate spacing in the pad is 200um. If the chip mounting method is adopted, the withstand voltage can be increased from the original 1000V to more than 2000V.

[0034] In summary, with the aid of the above technical solution of the present invention, the present invention uses insulating glue to bond the digital isolator chip to the tube shell, and wraps the isolator chip around by overflowing the insulating glue, thereby solving the problem of insufficient withstand voltage between the input and output ends of the unsealed digital isolator chip caused by semiconductor silicon.

[0035] Obviously, the above embodiments are merely examples for clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from these are still within the protection scope of the invention.

Claims

1. A digital isolator product structure of a ceramic package, which specifically solves the high-voltage isolation problem of the digital isolator of the ceramic package and improves the reliability of the digital isolator of the ceramic package, characterized in that: The invention comprises a digital isolator chip (3) and a housing (1); the substrate of the digital isolator chip (3) is a semiconductor silicon wafer; the digital isolator chip (3) is provided with metal pads for input and output of a receiver chip (4) and a transmitter chip (5); the housing (1) and the digital isolator chip (3) are provided with insulating glue (2) for bonding and connecting them; and the insulating glue (2) is also used to bond the receiver chip (4) and the transmitter chip (5) to the digital isolator chip (3).

2. The digital isolator product structure according to claim 1, characterized in that: The digital isolator chip (3) is made of a semiconductor silicon wafer, which is thinned by 100 μm. The isolator chip (3) is bonded to the housing (1) using an insulating glue (2), and the insulating glue is required to overflow and wrap around the digital isolator chip (3).

3. The digital isolator product structure according to claim 2, characterized in that: After the digital isolator chip (3) is pasted to the housing (1), a cover plate (7) is provided on the top of the housing (1) for assembly.

4. The digital isolator product structure according to claim 1, characterized in that: The receiver chip (4) and the transmitter chip (5) are connected to the digital isolator chip (3) via bonding wires (6), and then capped to form a digital isolator product.

5. A method for preparing a digital isolator chip isolation structure, characterized in that: The steps include: Step S1: First, according to the technical documents of product isolation withstand voltage requirements, the primary and secondary PAD spacing of the isolator chip is designed, and the digital isolator chip is manufactured based on a semiconductor silicon wafer and a polyimide process line; Step S2: Secondly, the digital isolator wafer is thinned to 100 μm and diced with a 30 μm thick blade; Step S3: Then, the digital isolator chip (3) is bonded to the housing (1) using insulating glue (2), the receiver chip (4) and the transmitter chip (5) are bonded to the digital isolator chip (2) using insulating glue (2), and then the chips are interconnected with each other using bonding wires (7), baked, capped, and molded.

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