Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a first electrode, a first dielectric layer and a second electrode. The first electrode is located on the substrate. The first electrode is columnar. The first dielectric layer is located on the first electrode. The second electrode is located on the first dielectric layer. The second electrode includes a first silicon germanium layer and a second silicon germanium layer. The first silicon germanium layer is located on the first dielectric layer. The second silicon germanium layer is on the first silicon germanium layer. The content of germanium in the second silicon germanium layer is greater than the content of germanium in the first silicon germanium layer. The semiconductor structure can effectively improve the reliability of the semiconductor structure and reduce the process time of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a manufacturing method thereof, and in particular to a semiconductor structure with a silicon germanium layer and a manufacturing method thereof. Background Art

[0002] In some semiconductor structures (eg, dynamic random access memory (DRAM) structures), silicon germanium layers are used as electrodes. However, how to effectively improve the reliability of semiconductor structures and reduce the processing time of semiconductor structures is a goal of continuous efforts. Summary of the invention

[0003] The present invention provides a semiconductor structure and a manufacturing method thereof, which can effectively improve the reliability of the semiconductor structure and reduce the process time of the semiconductor structure.

[0004] The present invention provides a semiconductor structure, comprising a substrate, a first electrode, a first dielectric layer and a second electrode. The first electrode is located on the substrate. The first electrode is columnar. The first dielectric layer is located on the first electrode. The second electrode is located on the first dielectric layer. The second electrode comprises a first silicon germanium layer and a second silicon germanium layer. The first silicon germanium layer is located on the first dielectric layer. The second silicon germanium layer is located on the first silicon germanium layer. The germanium content in the second silicon germanium layer is greater than the germanium content in the first silicon germanium layer.

[0005] The present invention provides a method for manufacturing a semiconductor structure, comprising the following steps: providing a substrate; forming a first electrode on the substrate; the first electrode being columnar; forming a first dielectric layer on the first electrode; forming a second electrode on the first dielectric layer; the second electrode comprising a first silicon germanium layer and a second silicon germanium layer; the first silicon germanium layer being located on the first dielectric layer; the second silicon germanium layer being located on the first silicon germanium layer; the method for forming the first silicon germanium layer comprising performing a furnace tube process; the method for forming the second silicon germanium layer comprising performing a chemical vapor deposition process.

[0006] Based on the above, in the semiconductor structure and the manufacturing method thereof proposed in the present invention, the second electrode includes a first silicon germanium layer and a second silicon germanium layer, the second silicon germanium layer is located on the first silicon germanium layer, and the germanium content in the second silicon germanium layer is greater than the germanium content in the first silicon germanium layer. Therefore, the process of the first silicon germanium layer and the process of the second silicon germanium layer can be optimized, thereby effectively improving the reliability of the semiconductor structure and reducing the process time of the semiconductor structure. In addition, since the second silicon germanium layer has a higher germanium content, the second silicon germanium layer can have a lower resistance.

[0007] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1A to 1E FIG. 4 is a cross-sectional view of a manufacturing process of a semiconductor structure according to some embodiments of the present invention.

[0009] Description of Figure Numbers:

[0010] 10: Semiconductor structure

[0011] 100: substrate

[0012] 102,118: Electrode

[0013] 104,106: Support layer

[0014] 108,116: Dielectric material layer

[0015] 108a, 116a: dielectric layer

[0016] 110: conductive material layer

[0017] 110a: conductive layer

[0018] 112,114: Silicon Germanium Material Layer

[0019] 112a, 114a: silicon germanium layer

[0020] 120: Capacitor

[0021] S1: Inclined surface

[0022] SW1, SW2, SW3, SW4, SW5: Side wall DETAILED DESCRIPTION

[0023] The following examples are listed and described in detail with reference to the accompanying drawings, but the examples provided are not intended to limit the scope of the present invention. For ease of understanding, the same components will be described with the same symbols in the following description. In addition, the drawings are for illustrative purposes only and are not drawn to their original size. In fact, the size of various features may be increased or decreased arbitrarily for the sake of clarity.

[0024] Please refer to Figure 1A , providing a substrate 100. The substrate 100 may be a semiconductor substrate, such as a silicon substrate. In addition, although not shown in the figure, corresponding components may be provided on and / or in the substrate 100 according to the type of semiconductor structure. For example, the substrate 100 may have components required for an isolation structure, a doped region and / or a buried word line (not shown), and the substrate 100 may have components required for a dielectric layer and / or an interconnection line structure (such as a bit line and a contact) (not shown), and the description thereof is omitted here.

[0025] Next, an electrode 102 is formed on the substrate 100. The electrode 102 is columnar. In some embodiments, the material of the electrode 102 is, for example, titanium nitride (TiN). In this embodiment, the number of electrodes 102 is plural, but the present invention is not limited thereto. As long as the number of electrodes is at least one, it falls within the scope of the present invention.

[0026] A support layer 104 is formed on the sidewall SW1 of the electrode 102. In some embodiments, the material of the support layer 104 is, for example, nitride (e.g., silicon nitride). A support layer 106 is formed on the sidewall SW1 of the electrode 102. The support layer 106 is located between the support layer 104 and the substrate 100. In some embodiments, the material of the support layer 104 is, for example, nitride (e.g., silicon nitride).

[0027] Please refer to Figure 1B , a dielectric material layer 108 is formed on the electrode 102. In some embodiments, the material of the dielectric material layer 108 is, for example, a high dielectric constant (high-k) dielectric material. In some embodiments, the dielectric material layer 108 is formed by, for example, chemical vapor deposition. Next, a conductive material layer 110 is formed on the dielectric material layer 108. In some embodiments, the material of the conductive material layer 110 is, for example, titanium nitride. In some embodiments, the conductive material layer 110 is formed by, for example, chemical vapor deposition.

[0028] Please refer to Figure 1C , a silicon germanium material layer 112 is formed on the dielectric material layer 108. The silicon germanium material layer 112 can be formed by a furnace tube process. In some embodiments, the furnace tube process can be performed for 1 hour to 5 hours, and the temperature of the furnace tube process can be 400° C. to 430° C. Then, a silicon germanium material layer 114 can be formed on the silicon germanium material layer 112. The silicon germanium material layer 114 can be formed by a chemical vapor deposition process. In some embodiments, the chemical vapor deposition process can be performed for 3 minutes to 5 minutes, and the temperature of the chemical vapor deposition process can be 400° C. to 430° C.

[0029] Please refer to Figure 1D , a dielectric material layer 116 may be formed on the silicon germanium material layer 114. In some embodiments, the material of the dielectric material layer 116 may be an oxide (e.g., silicon oxide). In some embodiments, the material of the dielectric material layer 116 is, for example, tetraethoxysilane (TEOS) silicon oxide. In some embodiments, the dielectric material layer 116 is formed by, for example, chemical vapor deposition.

[0030] Please refer to Figure 1E, the dielectric material layer 116, the silicon germanium material layer 114, the silicon germanium material layer 112, the conductive material layer 110 and the dielectric material layer 108 can be patterned to form a dielectric layer 116a, a silicon germanium layer 114a, a silicon germanium layer 112a, a conductive layer 110a and a dielectric layer 108a. Thus, the dielectric layer 108a can be formed on the electrode 102, the electrode 118 can be formed on the dielectric layer 108a, and the dielectric layer 116a can be formed on the electrode 118. The electrode 118 includes a silicon germanium layer 112a and a silicon germanium layer 114a. The silicon germanium layer 112a is located on the dielectric layer 108a. The silicon germanium layer 114a is located on the silicon germanium layer 112a. The germanium content in the silicon germanium layer 114a is greater than the germanium content in the silicon germanium layer 112a. In some embodiments, the electrode 118 may also include a conductive layer 110a. The conductive layer 110a is located between the silicon germanium layer 112a and the dielectric layer 108a. In some embodiments, the dielectric material layer 116, the silicon germanium material layer 114, the silicon germanium material layer 112, the conductive material layer 110 and the dielectric material layer 108 can be patterned by photolithography and etching. In some embodiments, the etching process is, for example, a dry etching process.

[0031] Below, through Figure 1E In order to explain the semiconductor structure 10 of the present embodiment, although the method for forming the semiconductor structure 10 is described by taking the above method as an example, the present invention is not limited thereto.

[0032] Please refer to Figure 1E , the semiconductor structure 10 includes a substrate 100, an electrode 102, a dielectric layer 108a, and an electrode 118. In some embodiments, the semiconductor structure 10 may be a memory structure, such as a dynamic random access memory (DRAM) structure. In addition, the electrode 102, the dielectric layer 108a, and the electrode 118 may form a capacitor 120. In some embodiments, the capacitor 120 may be used as a capacitor in a dynamic random access memory.

[0033] The electrode 102 is located on the substrate 100. The electrode 102 is columnar. In some embodiments, the cross-sectional shape of the electrode 102 may be U-shaped. The dielectric layer 108a is located on the electrode 102. The electrode 118 is located on the dielectric layer 108a. The electrode 118 includes a silicon germanium layer 112a and a silicon germanium layer 114a. The silicon germanium layer 112a is located on the dielectric layer 108a. The silicon germanium layer 114a is located on the silicon germanium layer 112a. The content of germanium in the silicon germanium layer 114a is greater than the content of germanium in the silicon germanium layer 112a. In some embodiments, the atomic percentage of germanium in the silicon germanium layer 114a may be greater than the atomic percentage of germanium in the silicon germanium layer 112a. In some embodiments, the content of germanium in the silicon germanium layer 112a may be 50 atomic % to 60 atomic %, and the content of germanium in the silicon germanium layer 114a may be 70 atomic % to 90 atomic %. In some embodiments, the hardness of the silicon germanium layer 112a may be greater than the hardness of the silicon germanium layer 114a. In some embodiments, the density of the silicon germanium layer 112a may be greater than the density of the silicon germanium layer 114a. In some embodiments, the silicon germanium layer 112a may include a P-type dopant (e.g., boron). In some embodiments, the silicon germanium layer 114a may include a P-type dopant (e.g., boron). The electrode 118 may also include a conductive layer 110a. The conductive layer 110a is located between the silicon germanium layer 112a and the dielectric layer 108a.

[0034] In some embodiments, the end of the electrode 118 may have an inclined surface S1. In some embodiments, the inclined surface S1 may include the sidewall SW2 of the silicon germanium layer 112a and the sidewall SW3 of the silicon germanium layer 114a. In some embodiments, the inclined surface S1 may also include the sidewall SW4 of the conductive layer 110a. In some embodiments, the inclined surface S1 may also include the sidewall SW5 of the dielectric layer 108a.

[0035] The semiconductor structure 10 may further include at least one of a support layer 104, a support layer 106, and a dielectric layer 116a. The support layer 104 is located on the sidewall SW1 of the electrode 102. The support layer 106 is located on the sidewall SW1 of the electrode 102. The support layer 106 may be located between the support layer 104 and the substrate 100. The dielectric layer 116a is located on the electrode 118.

[0036] Based on the above, in the semiconductor structure 10 and the manufacturing method thereof, the electrode 118 includes a silicon germanium layer 112a and a silicon germanium layer 114a, the silicon germanium layer 114a is located on the silicon germanium layer 112a, and the germanium content in the silicon germanium layer 114a is greater than the germanium content in the silicon germanium layer 112a. Therefore, the process of the silicon germanium layer 112a and the process of the silicon germanium layer 114a can be optimized, thereby effectively improving the reliability of the semiconductor structure and reducing the process time of the semiconductor structure. In addition, since the silicon germanium layer 114a has a higher germanium content, the silicon germanium layer 114a can have a lower resistance.

[0037] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A first electrode is located on the substrate, wherein the first electrode is columnar; a first dielectric layer, located on the first electrode; as well as A second electrode is located on the first dielectric layer, wherein the second electrode comprises: a first silicon germanium layer, located on the first dielectric layer; as well as The second silicon germanium layer is located on the first silicon germanium layer, wherein the germanium content in the second silicon germanium layer is greater than the germanium content in the first silicon germanium layer.

2. The semiconductor structure according to claim 1, characterized in that: An inclined surface is formed at the end of the second electrode, and the inclined surface includes a side wall of the first silicon germanium layer and a side wall of the second silicon germanium layer.

3. The semiconductor structure according to claim 2, characterized in that: The inclined surface also includes a sidewall of the first dielectric layer.

4. The semiconductor structure according to claim 1, characterized in that: An atomic percentage of germanium in the second silicon germanium layer is greater than an atomic percentage of germanium in the first silicon germanium layer.

5. The semiconductor structure according to claim 1, characterized in that: The hardness of the first silicon germanium layer is greater than the hardness of the second silicon germanium layer.

6. The semiconductor structure according to claim 1, characterized in that The density of the first silicon germanium layer is greater than the density of the second silicon germanium layer.

7. The semiconductor structure according to claim 1, characterized in that: Also includes: A first supporting layer, located on a side wall of the first electrode; a second supporting layer, located on a side wall of the first electrode and between the first supporting layer and the substrate; as well as A second dielectric layer is disposed on the second electrode, wherein The second electrode further comprises: The conductive layer is located between the first silicon germanium layer and the first dielectric layer.

8. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate; forming a first electrode on the substrate, wherein the first electrode is columnar; forming a first dielectric layer on the first electrode; as well as forming a second electrode on the first dielectric layer, wherein the second electrode comprises: a first silicon germanium layer, located on the first dielectric layer; as well as The second silicon germanium layer is located on the first silicon germanium layer, wherein the first silicon germanium layer is formed by a furnace tube process, and the second silicon germanium layer is formed by a chemical vapor deposition process.

9. The method for manufacturing a semiconductor structure according to claim 8, characterized in that: The second electrode has an inclined surface at its end, and The method for forming the first dielectric layer, the first silicon germanium layer and the second silicon germanium layer comprises: forming a dielectric material layer on the first electrode; forming a first silicon germanium material layer on the dielectric material layer; forming a second silicon germanium material layer on the first silicon germanium material layer; and The second silicon germanium material layer, the first silicon germanium material layer, and the dielectric material layer are patterned to form the second silicon germanium layer, the first silicon germanium layer, and the first dielectric layer.

10. The method for manufacturing a semiconductor structure according to claim 8, characterized in that: A germanium content in the second silicon germanium layer is greater than a germanium content in the first silicon germanium layer.

11. The method for manufacturing a semiconductor structure according to claim 8, characterized in that: The furnace process takes 1 to 5 hours, and the chemical vapor deposition process takes 3 to 5 minutes.

12. The method for manufacturing a semiconductor structure according to claim 8, characterized in that: The temperature of the furnace process is 400° C. to 430° C., and the temperature of the chemical vapor deposition process is 400° C. to 430° C.

13. The method for manufacturing a semiconductor structure according to claim 8, characterized in that: Also includes: forming a first supporting layer on a side wall of the first electrode; forming a second supporting layer on a side wall of the first electrode, wherein the second supporting layer is located between the first supporting layer and the substrate; as well as A second dielectric layer is formed on the second electrode.

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