Semiconductor memory device

Abstract

An embodiment provides a semiconductor memory device suitable for improving reliability of operation. According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a first polycrystalline semiconductor film, and a first insulating film. The laminated body is disposed above the substrate. The laminated body is laminated with a plurality of conductive layers through an insulating layer. The first polycrystalline semiconductor film extends in the stacking direction in the stacking body. The first insulating film extends in the lamination direction between the plurality of conductive layers and the first polycrystalline semiconductor film in the lamination body. The first polycrystalline semiconductor film includes a first portion and a second portion. The first portion corresponds to the first conductive layer. The first conductive layer is the conductive layer farthest from the substrate among the plurality of conductive layers. The second portion corresponds to two or more conductive layers. The two or more conductive layers are disposed between the substrate and the first conductive layer among the plurality of conductive layers. The height from the boundary of the first part and the second part to the substrate is between the height from the upper surface of the first conductive layer to the substrate and the height from the upper surface of the second conductive layer to the substrate. The second conductive layer is the conductive layer farthest from the substrate among the two or more conductive layers. The particle diameter of the first portion is smaller than that of the second portion.

Description

[0001] References to related applications

[0002] This application claims priority based on Japanese Patent Application No. 2023-150162 (filing date: September 15, 2023). This application incorporates all the contents of the basic application by reference. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Art

[0004] In a semiconductor memory device having a laminated body in which a plurality of conductive layers are laminated with an insulating layer interposed therebetween, and a polycrystalline semiconductor film extending in the laminated body in a lamination direction, a plurality of memory cells are provided at a plurality of intersections where the plurality of conductive layers intersect the polycrystalline semiconductor film. It is desired that the semiconductor memory device has improved operational reliability. Summary of the invention

[0005] An object of the present invention is to provide a semiconductor memory device suitable for improving the reliability of operation.

[0006] According to one embodiment, a semiconductor memory device having a substrate, a stacked body, a first polycrystalline semiconductor film, and a first insulating film is provided. The stacked body is arranged above the substrate. The stacked body is provided with a plurality of conductive layers stacked with an insulating layer. The first polycrystalline semiconductor film extends in the stacked body along the stacking direction. The first insulating film extends in the stacked body between the plurality of conductive layers and the first polycrystalline semiconductor film along the stacking direction. The first polycrystalline semiconductor film includes a first portion and a second portion. The first portion corresponds to the first conductive layer. The first conductive layer is the conductive layer farthest from the substrate among the plurality of conductive layers. The second portion corresponds to two or more conductive layers. The two or more conductive layers are arranged between the substrate and the first conductive layer among the plurality of conductive layers. The height of the boundary between the first portion and the second portion from the substrate is between the height of the upper surface of the first conductive layer from the substrate and the height of the upper surface of the second conductive layer from the substrate. The second conductive layer is the conductive layer farthest from the substrate among the two or more conductive layers. The grain size of the first portion is smaller than the grain size of the second portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a cross-sectional view showing the structure of a semiconductor memory device according to an embodiment.

[0008] Figure 2 This is a block diagram showing the structure of a semiconductor memory device according to an embodiment.

[0009] Figure 3 is a circuit diagram showing the configuration of a memory cell array in an embodiment.

[0010] Figure 4 It is a cross-sectional view showing the structure of a memory cell array in the embodiment.

[0011] Figure 5 It is a cross-sectional view showing the structure of a memory cell in the embodiment.

[0012] Figure 6 (a) and (b) are diagrams showing the distribution of impurity concentration of the semiconductor film in the embodiment.

[0013] Figure 7 It is a cross-sectional view showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0014] Figure 8 It is a cross-sectional view showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0015] Fig. 9 It is a cross-sectional view showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0016] Fig.10 It is a cross-sectional view showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0017] Fig.11 It is a cross-sectional view showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0018] Fig.12 It is a cross-sectional view showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0019] Fig.13 It is a cross-sectional view showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0020] Fig.14 It is a cross-sectional view showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0021] Fig.15 It is a cross-sectional view showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0022] Fig.16 It is a cross-sectional view showing a method for manufacturing a semiconductor memory device according to an embodiment.

[0023] Fig.17 It is a cross-sectional view showing a method for manufacturing a semiconductor memory device according to a modification of the embodiment.

[0024] Fig.18 It is a cross-sectional view showing a method for manufacturing a semiconductor memory device according to a modification of the embodiment. DETAILED DESCRIPTION

[0025] Hereinafter, the semiconductor memory device according to the embodiment will be described in detail with reference to the attached drawings. However, the present invention is not limited to these embodiments.

[0026] (Implementation Method)

[0027] The semiconductor memory device of the embodiment comprises: a stacked body, in which a plurality of conductive layers are stacked with an insulating layer; and a polycrystalline semiconductor film extending in the stacked body along the stacking direction; and a plurality of memory cells are arranged at a plurality of intersections where the plurality of conductive layers and the polycrystalline semiconductor film intersect. The semiconductor memory device implements a technique for improving the reliability of operation.

[0028] The semiconductor memory device 1 is Figure 1 As shown. Figure 1 It is a cross-sectional view schematically showing the structure of semiconductor memory device 1 .

[0029] In the following description, directions orthogonal to each other in a plane parallel to the surface of the substrate SUB are defined as the X direction and the Y direction. More specifically, the X direction is defined as the extending direction of the word line WL, and the Y direction is defined as the extending direction of the bit line BL. The Z direction is defined as the direction orthogonal to the surface of the substrate SUB. Therefore, the Z direction is orthogonal to the X direction and the Y direction.

[0030] like Figure 1 As shown in FIG. 1 , the semiconductor memory device 1 includes select gates SGS and SGSB, word lines WL, and select gates SGDT and SGD. The select gate SGS is laminated on the source line SL via an insulating layer 7. Figure 1 In the example of FIG. 1 , four layers of selection gates SGSB are provided, and three layers of selection gates SGS are provided. The word lines WL are interposed between insulating layers 7 and are stacked on the top selection gate SGS. Figure 1 In the example of FIG. 1 , the word lines WL are arranged in multiple layers alternately with the insulating layer 7 along the Z direction. The select gates SGD and SGDT are interposed between the insulating layer 7 and are stacked on the top word line WL. Figure 1 In the example of , two layers of selection gates SGD are provided, and two layers of selection gates SGDT are provided. The selection gates SGSB and SGS, the word line WL, and the selection gates SGD and SGDT are plate-shaped and extend in the X direction and the Y direction, respectively.

[0031] exist Figure 1In the example, the selection gates SGDT, SGD, the word line WL, and the selection gates SGS, SGSB are separated and insulated in the Y direction by the slit ST. The source line can be a two-layer structure. The two-layer structure includes a stack of source lines BSL and source lines SL. The source line BSL and the source line SL are interposed with an interlayer insulating film 81 and are sequentially stacked on the +Z side of the substrate SUB. In order to reduce the resistance of the source line SL, the source line BSL contacts the surface of the -Z side of the source line SL. The slit ST is provided on the +Z side of the source line SL and extends along the X direction and the Z direction.

[0032] The selection gate SGD is divided by, for example, a dividing film SHE (not shown) in the Y direction. The dividing film SHE is provided above the word line WL (on the +Z side) and extends in the X direction and the Z direction.

[0033] The substrate SUB is, for example, a silicon substrate. The select gate SGS, the word line WL, and the select gate SGD are, for example, metal layers containing tungsten (W). The insulating layer 7 and the interlayer insulating film 81 are, for example, an insulator containing silicon oxide.

[0034] The semiconductor memory device 1 further includes a plurality of pillars 40. The pillars 40 penetrate the select gate SGS, the word line WL, and the select gate SGD, and extend in the stacking direction thereof, that is, the Z direction. The semiconductor memory device 1 further includes a plurality of bit lines BL provided above the select gate SGD.

[0035] The pillars 40 are respectively electrically connected to the bit lines BL via the contact plugs 31. For example, one of the pillars 40 sharing the selection gate SGD0 and one of the pillars 40 sharing the selection gate SGD1 are electrically connected to one bit line BL.

[0036] An interlayer insulating film 83 is provided between the pillar 40 and the bit line BL. An interlayer insulating film 82 is provided between the interlayer insulating film 83 and the selection gate SGD. The contact plug 31 penetrates the interlayer insulating film 83. The -Z side end of the contact plug 31 is connected to the semiconductor film of the pillar 40, and the +Z side end is connected to the bit line BL.

[0037] In the semiconductor memory device 1, the selection gate SGD, the word line WL, and the selection gate SGS are each composed of a conductive layer. On the +Z side of the source line SL, a stacked body SST is formed in which conductive layers and insulating layers 7 are alternately stacked. The stacked body SST is penetrated by a columnar body 40 to form a three-dimensional arrangement of memory cells (memory cell array).

[0038] That is, in the semiconductor memory device 1, the portion where the word line WL intersects the column 40 functions as a memory cell, and a memory cell array 2 is formed in which a plurality of memory cells are arranged three-dimensionally. In addition, the portion where the selection gate SGS intersects the column 40 functions as a source-side selection gate, and the portion where the selection gate SGD intersects the column 40 functions as a drain-side selection gate. In the semiconductor memory device 1, by increasing the number of stacked layers of the word line WL in the stacked body SST, the storage capacity can be increased even without using a finer patterning technology.

[0039] Figure 2 It is a block diagram showing a schematic configuration of the semiconductor memory device 1 .

[0040] like Figure 2 As shown, the semiconductor memory device 1 includes a memory cell array 2, a peripheral circuit 100, and an interface 200. The peripheral circuit 100 includes a WL driver circuit 110, an SGS driver circuit 120, an SGD driver circuit 130, an SL driver circuit 140, and a sense amplifier circuit 150.

[0041] The WL driving circuit 110 is a circuit for controlling the voltage applied to the word line WL, the SGS driving circuit 120 is a circuit for controlling the voltage applied to the selection gates SGS and SGSB. The SGD driving circuit 130 is a circuit for controlling the voltage applied to the selection gates SGD and SGDT, and the SL driving circuit 140 is a circuit for controlling the voltage applied to the source line SL. The sense amplifier circuit 150 is a circuit for controlling the voltage applied to the bit line BL, and is a circuit for determining the data to be read based on the signal from the selected memory cell.

[0042] The peripheral circuit 100 controls the operation of the semiconductor memory device 1 based on an instruction input from the outside (for example, a memory controller of a memory system to which the semiconductor memory device 1 is applied) via the interface 200 .

[0043] Next, use Figure 3 The circuit configuration of the memory cell array 2 will be described. Figure 3 2 is a circuit diagram showing the structure of the memory cell array 2.

[0044] Each memory cell array 2 includes a set of a plurality of memory cell transistors MT, that is, a plurality of blocks BLK. Hereinafter, the memory cell transistor MT is referred to as a memory cell MT for short.

[0045] Each block BLK has a set of memory cells MT associated with word lines WL and bit lines BL, that is, multiple string units SU0, SU1, SU2, and SU3. Each string unit SU0-SU3 has multiple memory strings MST that connect the memory cells MT in series. In addition, the number of memory strings MST in the string unit SU0-SU3 is arbitrary.

[0046] The plurality of string units SU0, SU1, SU2, SU3 correspond to the plurality of selection gates SGD0, SGD1, SGD2, SGD3 and share the selection gate SGS, functioning as a plurality of driving units in the block BLK. Each string unit SU can be driven by its corresponding selection gate SGD and selection gate SGS. In addition, each string unit SU includes a plurality of memory strings MST.

[0047] Each memory string MST includes, for example, 11 memory cells MT (MT0 to MT10) and selection transistors DGT and SGT. The memory cell MT has a control gate and a charge accumulation film, and non-volatilely retains and stores data. Moreover, the 11 memory cells MT are connected in series between the source of the selection transistor DGT and the drain of the selection transistor SGT. In addition, the number of memory cells MT in the memory string MST is not limited to 11.

[0048] The gates of the selection transistors DGTb in each string unit SU0 to SU3 are connected to the selection gates SGD0T to SGD3T, respectively. The gates of the selection transistors DGTa in each string unit SU0 to SU3 are connected to the selection gates SGD0 to SGD3, respectively. In contrast, the gates of the selection transistors SGTa in each string unit SU are commonly connected to, for example, the selection gate SGS. The gates of the selection transistors SGTb in each string unit SU are commonly connected to, for example, the selection gate SGSB.

[0049] The drains of the selection transistors DGT of each memory string MST in each string unit SU are connected to different bit lines BL0 to BLk (k is an arbitrary integer greater than 2). In addition, the bit lines BL0 to BLk are commonly connected to one memory string MST in each string unit SU among multiple blocks BLK. In addition, the sources of each selection transistor SGT are commonly connected to the source line SL.

[0050] That is, the string unit SU is a collection of memory strings MST connected to different bit lines BL0 to BLk and connected to the same selection gate SGD. In addition, each block BLK is a collection of multiple string units SU0 to SU3 that share a common word line WL. Moreover, the memory cell array 2 is a collection of multiple blocks BLK that share a common bit line BL0 to BLk.

[0051] In addition, when a group of storage cells MT sharing a common word line WL is referred to as a "memory cell group MCG", the memory cell group MCG is the minimum unit of a collection of storage cells MT to which a specified voltage (e.g., write voltage, read voltage) can be uniformly applied via the word line WL.

[0052] Next, use Figure 4 The cross-sectional structure of the memory cell array 2 will be described. Figure 4 The YZ cross-sectional view showing the structure of the memory cell array 2 is an enlarged view. Figure 1 An enlarged cross-sectional view of part A.

[0053] In the semiconductor memory device 1, a source line SL (refer to Figure 1 ). A plurality of columnar bodies 40 are arranged in the XY direction. Each columnar body 40 extends in the Z direction and penetrates the stacked body SST.

[0054] Figure 4 The columnar body 40 shown has a columnar shape having a central axis CA along the Z direction, and has, for example, a substantially cylindrical shape. Figure 4 , a portion near the -Z side end of the columnar body 40 is illustrated. The columnar body 40 may have a tapered shape in which the diameter of the -Z side end is narrower than the diameter of the +Z side end. The columnar body 40 may also have an arched shape in which the diameter of the -Z side end is narrower than the diameter of the +Z side end and the diameter expands at a predetermined Z position between the +Z side end and the -Z side end. The diameter of the -Z side end of the columnar body 40 is smaller than the diameter of the +Z side end of the columnar body 40.

[0055] like Figure 4 and Figure 5 As shown, the columnar body 40 includes a core member 41, a polycrystalline semiconductor film 42, and an insulating film 43 in order from the central axis CA side. The insulating film 43 is a multilayer film including an insulating film 43a, a charge storage film 43b, and an insulating film 43c in order from the central axis CA side. Figure 5 is an XY cross-sectional view showing the structure of a storage cell, showing the BB line. Figure 4 Cross section when cut.

[0056] The core member 41 is disposed near the central axis CA of the columnar body 40 and has a substantially cylindrical shape extending along the central axis CA of the columnar body 40. The core member 41 can be formed of a material having an insulator (for example, a semiconductor oxide such as silicon oxide) as a main component.

[0057] The polycrystalline semiconductor film 42 is disposed so as to surround the core member 41 from the outside and has a substantially cylindrical shape extending along the central axis CA of the columnar body 40. The polycrystalline semiconductor film 42 can be formed of a material mainly composed of a semiconductor (eg, polycrystalline silicon) containing substantially no impurities.

[0058] The insulating film 43a is disposed so as to surround the polycrystalline semiconductor film 42 from the outside, and has a substantially cylindrical shape extending along the central axis CA of the columnar body 40. The insulating film 43a can be formed of a material having an oxide (eg, silicon oxide or silicon oxynitride) as a main component.

[0059] The charge storage film 43b is disposed so as to surround the insulating film 43a from the outside, and has a substantially cylindrical shape extending along the central axis CA of the columnar body 40. The charge storage film 43b can be formed of a material having nitride (eg, silicon nitride) as a main component.

[0060] The insulating film 43c is arranged so as to surround the charge accumulation film 43b from the outside, and has a substantially cylindrical shape extending along the central axis CA of the columnar body 40. The insulating film 43c can be formed of a material having an oxide (e.g., silicon oxide, metal oxide, or a stack of these) as a main component. Thus, a three-layer structure of an ONO type in which the charge accumulation film 43b is sandwiched by a pair of insulating films 43a and 43c can be formed.

[0061] The insulating film 8 covers the insulating film 43c from the outside in the XY direction and extends to cover the surface on the +Z side of the conductive layer 6, the surface on the columnar body 40 side, and the surface on the -Z side of the conductive layer 6, forming a substantially hollow disk shape having an axis along the Z direction. The insulating film 8 can be formed of an insulating material such as aluminum oxide. In the following, for simplicity, the illustration and description of the insulating film 8 are sometimes omitted.

[0062] like Figure 4 As shown, the columnar body 40 also has a polycrystalline semiconductor film 44 .

[0063] The polycrystalline semiconductor film 44 is arranged near the central axis CA of the columnar body 40, and has a substantially cylindrical shape extending along the central axis CA of the columnar body 40. The outer diameter of the polycrystalline semiconductor film 44 corresponds to the outer diameter of the polycrystalline semiconductor film 42. The polycrystalline semiconductor film 44 is arranged between the core part 41 and the polycrystalline semiconductor film 42 and the contact plug 31. The end surface on the -Z side of the polycrystalline semiconductor film 44 covers the end on the -Z side of the core part 41 and the end on the -Z side of the polycrystalline semiconductor film 42, and the end surface on the +Z side is in contact with the contact plug 31.

[0064] The polycrystalline semiconductor film 42 of the columnar body 40 is connected to the source line SL (refer to Figure 1 ), and connected to the bit line BL (reference Figure 1 ). That is, the polycrystalline semiconductor film 42 of the pillar 40 includes a channel region (active region) in the memory string MST.

[0065] In the laminated body SST, the conductive layers 6 and the insulating layers 7 are alternately and repeatedly laminated. Each conductive layer 6 extends in a plate shape in the XY direction. Each conductive layer 6 can be formed of a material having a conductive substance (for example, a metal such as tungsten) as a main component. The surface on the +Z side, the surface on the -Z side, and the surface opposite to the columnar body 40 of each conductive layer 6 can be covered by an insulating film 8. The composition of the insulating film 8 may be different from that of the insulating film 43c. The insulating film 8 can be formed of a material having an insulating substance (for example, a metal oxide such as aluminum oxide, zirconium oxide, hafnium oxide, etc.) as a main component. Each insulating layer 7 extends in a plate shape in the XY direction. Each insulating layer 7 can be formed of a material having an insulating substance (for example, a semiconductor oxide such as silicon oxide) as a main component.

[0066] In the stacked body SST, among the plurality of conductive layers 6 arranged apart from each other in the Z direction, the conductive layer 6 on the -Z side serves as the selection gates SGSB and SGS (refer to Figure 1 ) functions, and the conductive layer 6 on the +Z side serves as the selection gate SGDT, SGD (reference Figure 1 ) functions, and the conductive layer 6 therebetween functions as a word line WL. Figure 4 In the figure, there is illustrated an example of a structure in which, in the laminate body SST, a conductive layer 6 of a selection gate SGSB1, a conductive layer 6 of a selection gate SGSB2, a conductive layer 6 of a selection gate SGSB3, a conductive layer 6 of a selection gate SGSB4, a conductive layer 6 of a selection gate SGS1, a conductive layer 6 of a selection gate SGS2, and a conductive layer 6 of a selection gate SGS3 are laminated from the -Z side.

[0067] The selection transistor DGTb0 is formed at a position where the conductive layer 6 of the selection gate SGDT0 intersects the polycrystalline semiconductor film 42. The selection transistor SGTb1 is formed at a position where the conductive layer 6 of the selection gate SGDT1 intersects the polycrystalline semiconductor film 42.

[0068] A selection transistor DGTa0 is formed at a position where the conductive layer 6 of the selection gate SGD0 intersects the polycrystalline semiconductor film 42 and the charge storage film 43b. A selection transistor DGTa1 is formed at a position where the conductive layer 6 of the selection gate SGD1 intersects the polycrystalline semiconductor film 42.

[0069] The memory cell MT0 is formed at the intersection of the conductive layer 6 of the word line WL0 with the polycrystalline semiconductor film 42 and the charge accumulation film 43b. Figure 1 ) of the conductive layer 6 and the polycrystalline semiconductor film 42 and the charge accumulation film 43b intersect to form a memory cell MT1 (reference Figure 3 ) A memory cell MT10 is formed at a position where the conductive layer 6 of the word line WL10 intersects the polycrystalline semiconductor film 42 and the charge storage film 43b.

[0070] The select gate SGS (reference Figure 1 ) at a position where the conductive layer 6 and the polycrystalline semiconductor film 42 intersect, forming a selection transistor SGTa (reference Figure 3 ).

[0071] The select gate SGSB (reference Figure 1 ) is formed at a position where the conductive layer 6 and the polycrystalline semiconductor film 42 intersect each other, and a selection transistor SGTb (reference Figure 3 ).

[0072] In addition, the charge storage film 43 b and the insulating film 43 c may be partially omitted at the position where the columnar body 40 intersects with the conductive layer 6 of the selection gates SGD and SGDT.

[0073] like Figure 4 As shown, the polycrystalline semiconductor film 42 of each columnar body 40 has a portion 42 a and a portion 42 b .

[0074] The portion 42 a is disposed so as to surround the core member 41 from the outside, and has a substantially cylindrical shape extending along the central axis CA of the columnar body 40 .

[0075] The portion 42a corresponds to the conductive layer 6 closest to the +Z side among the multiple conductive layers 6 in the stack body SST (for example, the conductive layer 6 of the selection gate SGDT0). The conductive layer 6 closest to the +Z side among the multiple conductive layers 6 can also be referred to as the conductive layer 6 closest to the substrate SUB among the multiple conductive layers 6 (refer to Figure 1 )The farthest conductive layer 6.

[0076] The portion 42a is a portion from the +Z side end of the polycrystalline semiconductor film 42 to the Z position corresponding to the conductive layer 6 closest to the +Z side. The Z position corresponding to the conductive layer 6 closest to the +Z side can be a Z position between the Z position of the surface on the +Z side of the conductive layer 6 closest to the +Z side and the Z position of the surface on the +Z side of the conductive layer 6 closest to the +Z side.

[0077] The portion 42a is in contact with the polycrystalline semiconductor film 44 on the +Z side, and is in contact with the portion 42b on the -Z side. The portion 42a may be integrally continuous with the portion 42b on the -Z side.

[0078] The portion 42b corresponds to the remaining conductive layers 6 except the one closest to the +Z side among the plurality of conductive layers 6 in the laminate SST (for example, the conductive layers 6 of the selection gate SGDT1 to the conductive layers 6 of the selection gate SGSB). The remaining conductive layers 6 except the one closest to the +Z side among the plurality of conductive layers 6 can also be referred to as the conductive layers 6 disposed on the substrate SUB (refer to Figure 1 ) and two or more conductive layers 6 between the conductive layer 6 on the +Z side.

[0079] The portion 42 b is a portion of the polycrystalline semiconductor film 42 from the Z position corresponding to the conductive layer 6 closest to the +Z side to the −Z side end.

[0080] The portion 42b is in contact with the portion 42a on the +Z side. The portion 42b may be integrally continuous with the portion 42a on the +Z side.

[0081] The Z height of the boundary between portion 42a and portion 42b from the substrate SUB can be between the Z height of the upper surface (surface on the +Z side) of the conductive layer 6 closest to the +Z side among the multiple conductive layers 6 from the substrate SUB and the Z height of the upper surface (surface on the +Z side) of the second conductive layer 6 closest to the +Z side from the substrate SUB.

[0082] For example, the Z height of the boundary between the portion 42a and the portion 42b from the substrate SUB may be equal to the Z height of the bottom surface (the surface on the −Z side) of the conductive layer 6 closest to the +Z side among the plurality of conductive layers 6 from the substrate SUB.

[0083] Each of the portion 42a and the portion 42b can be formed of a material having a polycrystalline semiconductor (eg, polycrystalline silicon) as a main component. The average grain size d1 of the portion 42a is smaller than the average grain size d2 of the portion 42b.

[0084] In addition, the method for obtaining the average particle size is not particularly limited, but the average particle size measured by, for example, a flow-type particle image analyzer, a particle size distribution measuring device using a laser diffraction or scattering method, etc., can also be used. Alternatively, the average particle size can be calculated from a TEM (Transmission Electron Microscope) image using an Intercept method (also called the Heyn method) or a Planimetric method (also called the Jeffries method).

[0085] Alternatively, ACOM-TEM (Automated Crystal Orientation Mapping in TEM) analysis can be used to calculate the average grain size. In ACOM-TEM analysis, the polycrystalline semiconductor film 42 is sliced ​​in a direction perpendicular to the central axis CA to make a semicircular sample, which is analyzed in a field of view of about 5nm×5nm, and the azimuthal angle difference of less than 5° is judged to be the same grain size. The in-plane average grain size obtained by ACOM-TEM analysis under such conditions is set. The average grain size is calculated using the average grain size in a field of view of about 5nm×5nm.

[0086] For example, the crystal grains included in the polycrystalline semiconductor film 42 may have twins. When the twin boundary is not used as the grain boundary, the total number of particles is N, and the particle size (equivalent circle diameter) of each particle is d iWhen d is calculated by the following formula 1, the average particle size can be set. In this case, the average particle size of the portion 42a may be less than 80 nm, and the average particle size of the portion 42b may be greater than 80 nm.

[0087] [Number 1]

[0088]

[0089] When the twin boundary is defined as the grain boundary, the total number of particles is defined as N, and the particle size (equivalent circle diameter) of each particle is defined as d i ', d calculated by the following formula 2 can be used as the average particle size. In this case, the average particle size of the portion 42a may be less than 30 nm, and the average particle size of the portion 42b may be greater than 30 nm.

[0090] [Number 2]

[0091]

[0092] In addition, the average grain size d3 of the polycrystalline semiconductor film 44 may be larger than the average grain size d1 of the portion 42a. The average grain size d3 of the polycrystalline semiconductor film 44 may be larger than the average grain size d2 of the portion 42b.

[0093] In the process of writing information to the storage cell MT, a write voltage is applied to the conductive layer 6 of the selected word line WL, a transfer voltage is applied to the conductive layer 6 of the non-selected word line WL, a reference voltage is applied to the polycrystalline semiconductor film 42, a selection voltage is applied to the selection gate lines SGD and SGDT of the selection string, and a reference voltage is applied to the selection gate lines SGS and SGSB. The write voltage has a potential (e.g., 20V) for injecting the charge (electrons) of the polycrystalline semiconductor film 42 into the charge accumulation film 43b. The transfer voltage has a potential (e.g., 10V) between the write voltage and the reference voltage. The reference voltage has a potential (e.g., 0V) as a reference. The selection voltage has a potential (e.g., 2.5V) for turning on the selection transistors DGTa and DGTb, and the reference voltage has a potential for turning off the selection transistors SGTa and SGTb. Thus, charge is accumulated in the charge accumulation film 43b of the selected storage cell MT at the position where the conductive layer 6 of the selected word line WL intersects with the polycrystalline semiconductor film 42, and information is written to the selected storage cell MT.

[0094] In the erasing process for the information of the storage cell MT, a reference voltage is applied to the conductive layer 6 of each word line WL, an erase voltage is applied to the polycrystalline semiconductor film 42, a selection voltage is applied to the selection gates SGS and SGSB, and an intermediate voltage between the two is applied to the selection gates SGD and SGDT. The erase voltage has a potential (e.g., 20V) for injecting the opposite charge (holes) of the polycrystalline semiconductor film 42 into the charge accumulation film 43b. The reference voltage has a potential (e.g., 0V) as a reference. The selection voltage has a potential (e.g., 20V) for disconnecting the selection transistors SGTa and SGTb, and the intermediate voltage has a potential (e.g., 5V) between the erase process and the reference voltage. Through such control, electron-hole pairs are generated near the drain of the selection transistor SGTb by GIDL (Gate Induced Drain Leakage), and the opposite charge (holes) are injected from the polycrystalline semiconductor film 42 to the charge accumulation film 43b. As a result, the charge accumulated in the charge accumulation film 43b can be erased, and the information of the storage cell MT can be erased.

[0095] In the erase process, the selection transistor DGTb corresponding to the selection gate SGDT has the function of generating GIDL, and the selection transistor DGTa corresponding to the selection gate SGD has the function of electrically connecting and disconnecting the polycrystalline semiconductor film 42 and the bit line BL.

[0096] When the semiconductor memory device 1 is manufactured, the N-type impurities (for example, phosphorus) contained in the polycrystalline semiconductor film 44 diffuse into the polycrystalline semiconductor film 42. Accordingly, the concentration of the N-type impurities in the polycrystalline semiconductor film 42 is as follows: Figure 6 As indicated by the solid line in (a), the portion 42a is relatively high, but tends to decrease as it approaches the Z position Zb at the boundary between the portion 42a and the portion 42b.

[0097] Figure 6 4 is a diagram showing the distribution of the impurity concentration of the polycrystalline semiconductor film 42 . Figure 6 (a) in FIG. 1 shows the distribution of the N-type impurity concentration of the polycrystalline semiconductor film 42 in the Z direction, where the vertical axis represents the N-type impurity concentration and the horizontal axis represents the Z position. Figure 6 (b) in the expression is the same as Figure 6 The horizontal axis (Z position) in (a) corresponds to the YZ cross section of the polycrystalline semiconductor film 42 .

[0098] At this time, as described above, the average grain size of the portion 42a in the polycrystalline semiconductor film 42 is smaller than the average grain size of the portion 42b. As a result, the diffusion amount of the N-type impurity from the polycrystalline semiconductor film 44 to the portion 42a and the portion 42b can be appropriately controlled. The diffusion distance of the N-type impurity in the polycrystalline semiconductor film 42 from the polycrystalline semiconductor film 44 in the Z direction is equal to the distance from the interface between the polycrystalline semiconductor film 44 and the polycrystalline semiconductor film 42 to the boundary (Z position Zb) in the Z direction.

[0099] That is to say, Figure 6 As shown by the solid line in (a), in the polycrystalline semiconductor film 42, N-type impurities with a threshold concentration Cth or higher can be contained in the channel region of the selection gate SGDT, but the N-type impurities in the channel region of the selection gate SGD are suppressed to be less than the threshold concentration Cth. As a result, the GIDL generation in the selection gate SGDT during the erase process can be made more efficient, and the selection gate SGD can be appropriately turned on and off.

[0100] The method of determining the impurity concentration is not particularly limited, and for example, a concentration measured by a SIMS (Secondary Ion Mass Spectrometry) device or the like may be used.

[0101] Next, use Figure 7 to Figure 16 and Figure 4 A method for manufacturing semiconductor memory device 1 will be described. Figure 7 to Figure 16 It is a YZ cross-sectional view showing a method of manufacturing the semiconductor memory device 1 . Figure 4 It is a YZ cross-sectional view showing the structure of the semiconductor memory device 1, but it is used as a cross-sectional view showing the manufacturing method.

[0102] exist Figure 7 In the steps shown, the substrate SUB (reference Figure 1 ) to form a transistor, a contact plug, a wiring film, a via plug, etc. are formed on the substrate SUB, and an interlayer insulating film 81 is formed around them. Thus, a peripheral circuit 100 is formed. The interlayer insulating film 81 can be formed by depositing a material having an insulator (for example, a semiconductor oxide such as silicon oxide) as a main component on the +Z side of the substrate SUB.

[0103] The layer of the source line BSL is deposited on the +Z side of the interlayer insulating film 81. The layer of the source line BSL can be formed of a material mainly composed of a semiconductor (eg, silicon) containing an N-type impurity (eg, phosphorus or arsenic).

[0104] A layer of source line SL is deposited on the +Z side of the layer of source line BSL. The layer of source line SL can be formed of a material mainly composed of a semiconductor (eg, silicon) containing an N-type impurity (eg, phosphorus or arsenic).

[0105] On the +Z side of the layer of the source line SL, the insulating layer 7i and the sacrificial layer 13i are alternately deposited multiple times to form a laminated body SSTi. The insulating layer 7i can be formed of a material having an oxide (e.g., silicon oxide) as a main component. The sacrificial layer 13i can be formed of a material having a nitride (e.g., silicon nitride) as a main component. Each insulating layer 7i and each sacrificial layer 13i can be deposited with substantially the same film thickness.

[0106] An interlayer insulating film 82i is deposited on the +Z side of the sacrificial layer 13i that is closest to the +Z side in the stacked body SSTi. The interlayer insulating film 82i can be formed of a material having an oxide (for example, silicon oxide) as a main component.

[0107] exist Figure 8 In the step shown, a resist pattern with an opening at the formation position of the memory hole 26 is formed on the laminate. Using the resist pattern as a mask, anisotropic etching such as RIE (Reactive Ion Etching) is performed to form a layer that penetrates the interlayer insulating film 82, the laminate SSTj, and the source line SL (see Figure 1 ) reaches the memory hole 26 of the layer of the source line BSL.

[0108] exist Fig. 9 In the steps shown, an insulating film 43ci, a charge accumulation film 43bi, and an insulating film 43ai are sequentially deposited on the side and bottom of the memory hole 26 (see Figure 4 ). The insulating film 43ci can be formed of a material having an oxide (e.g., silicon oxide, metal oxide, or a stack of these) as a main component. The charge accumulation film 43bi can be formed of a material having a nitride (e.g., silicon nitride) as a main component. The insulating film 43ai can be formed of a material having an oxide (e.g., silicon oxide or silicon oxynitride) as a main component.

[0109] exist Fig.10 In the step shown, a polycrystalline semiconductor film 42i is deposited on the side and bottom of the memory hole 26. The polycrystalline semiconductor film 42i can be formed of a material having a polycrystalline semiconductor (e.g., polycrystalline silicon) substantially free of impurities as a main component. The film thickness of the polycrystalline semiconductor film 42i is controlled by film formation conditions and the like.

[0110] For example, the polycrystalline semiconductor film 42i is deposited under film formation conditions (eg, gas flow rate, film formation time) such that the film thickness in a YZ cross section including the central axis CA is D42i.

[0111] In addition, there is a correlation between the film thickness of a polycrystalline semiconductor film and its average grain size. The larger the film thickness of a polycrystalline semiconductor film is, the larger the average grain size tends to be. Fig.10The film thickness D42i of the polycrystalline semiconductor film 42i shown corresponds to the average grain size d2. The average grain size d2 is the average grain size of the portion 42b (refer to Figure 4 )’s average particle size.

[0112] exist Fig.11 In the step shown, the polycrystalline semiconductor film 42i is thinned by isotropic etching such as wet etching to form a polycrystalline semiconductor film 42j. The etching amount of the isotropic etching is controlled by etching conditions and the like.

[0113] For example, the polycrystalline semiconductor film 42 j is etched under such etching conditions (for example, etching time) that the film thickness in a YZ cross section including the central axis CA is D42 j (< D42 i ).

[0114] in addition, Fig.11 The film thickness D42j of the polycrystalline semiconductor film 42i shown corresponds to the average grain size d1 (< d2). The average grain size d1 is the average grain size of the portion 42a (refer to Figure 4 )’s average particle size.

[0115] exist Fig.12 In the step shown, the core member 41 is buried in the memory hole 26. The core member 41 can be formed of a material having an insulator (for example, a semiconductor oxide such as silicon oxide) as a main component. Thus, a columnar body 40i (refer to Figure 1 ).

[0116] In addition, the core member 41 can be embedded in the memory hole 26 in such a manner that the Z height of the end portion on the +Z side of the core member 41 is lower than the Z height of the end portions on the +Z side of the insulating film 43ci, the charge accumulation film 43bi, the insulating film 43ai, and the polycrystalline semiconductor film 42j. Thus, a recessed portion 261 is formed which is surrounded by the inner side surface of the polycrystalline semiconductor film 42j and the surface on the +Z side of the core member 41. The recessed portion 261 is a space on a substantially cylindrical surface.

[0117] exist Fig.13 In the step shown, a polycrystalline semiconductor film 44i is buried in the recess 261. The polycrystalline semiconductor film 44i can be formed of a material containing a polycrystalline semiconductor (eg, polycrystalline silicon) containing an impurity (eg, phosphorus) as a main component.

[0118] The XY direction width D44i of the polycrystalline semiconductor film 44i corresponds to the average grain size d3. The XY direction width D44i is larger than the film thickness D42j (refer to Fig.11 ) and is greater than the film thickness D42i (reference Fig.10 ). Accordingly, the average particle size d3 is larger than the average particle size d1, and larger than the average particle size d2.

[0119] exist Fig.14 In the steps shown, specified particles are introduced into the polycrystalline semiconductor film 42j up to a specified Z position by a particle implantation method or the like, so that a portion 42ak of the polycrystalline semiconductor film 42k up to the specified Z position is rendered amorphous, and a portion 42bk deeper than the specified Z position is not rendered amorphous but remains in a polycrystalline state.

[0120] The prescribed particles include any particles suitable for amorphization. The prescribed particles may be arsenic ions or argon molecules. The prescribed Z position may be a Z position between the Z position of the surface on the +Z side of the sacrificial layer 13 closest to the +Z side and the Z position of the surface on the +Z side of the sacrificial layer 13 closest to the +Z side. When the particle injection method is used, the prescribed Z position may be controlled by the acceleration voltage of the particle injection.

[0121] exist Fig.15 In the step shown, the columnar body 40i is heat-treated. As a result, the amorphous portion 42ak in the polycrystalline semiconductor film 42i is crystallized to become the side portion of the polycrystalline semiconductor film 44 and the polycrystalline portion 42a in the polycrystalline semiconductor film 42. The polycrystalline portion 42bk in the polycrystalline semiconductor film 42i remains substantially unchanged and becomes the polycrystalline portion 42b in the polycrystalline semiconductor film 42.

[0122] Here, when the portion 42a is crystallized, according to its film thickness D42j (reference Fig.11 ), the average particle size becomes d1. Part 42b remains substantially unchanged, and the average particle size remains d2. The film thickness D42j is greater than the film thickness D42i (reference Fig.10 Accordingly, the average particle size d1 of the portion 42a is smaller than the average particle size d2 of the portion 42b.

[0123] In addition, the average grain size d3 of the polycrystalline semiconductor film 44 is larger than the average grain size d1 of the portion 42 a and larger than the average grain size d2 of the portion 42 b .

[0124] exist Fig.16 In the step shown, the sacrificial layer 13 in the stacked body SSTj is removed by isotropic etching such as wet etching to form the gap 28. Then, an insulating film 8 (see FIG. 1 ) is formed to cover the exposed surface of the gap 28. Figure 4 ). The insulating film 8 can be formed of an insulating material such as aluminum oxide.

[0125] exist Figure 4 In the step shown, a conductive material is buried in the gap 28 to form a conductive layer 6. The conductive layer 6 is formed of a material containing a metal such as tungsten as a main component. Thus, a laminated body SST is formed in which a plurality of insulating layers 7 and conductive films 6 are alternately laminated. That is, a semiconductor memory device 1 including the laminated body SST is formed.

[0126] As described above, in the embodiment, in the semiconductor memory device 1, a polycrystalline semiconductor film 42 extending in the Z direction is provided in the stacked body SST in which the conductive layer 6 and the insulating layer 7 are alternately and repeatedly stacked. In the polycrystalline semiconductor film 42, the average grain size d1 of the portion 42a corresponding to the conductive layer 6 closest to the +Z side (for example, the conductive layer 6 of the selection gate SGDT0) is smaller than the average grain size d2 of the portion 42b corresponding to the remaining conductive layers 6 other than the closest to the +Z side (for example, the conductive layer 6 of the selection gate SGDT1, the conductive layer 6 of the selection gate SGD0, the conductive layer 6 of the selection gate SGD1, ..., the conductive layer 6 of the selection gate SGSB). Thus, the diffusion amount of the N-type impurity from the polycrystalline semiconductor film 44 to the portion 42a and the portion 42b can be appropriately controlled. As a result, since the generation of GIDL in the selection gate SGDT during the erase process can be made efficient and the selection gate SGD can be appropriately turned on and off, the reliability of the operation of the semiconductor memory device 1 can be improved.

[0127] For example, when the average grain size of the polycrystalline semiconductor film 42 is relatively large uniformly from the +Z side end to the -Z side end (for example, the average grain size d2), the deviation in the diffusion length of the N-type impurity from the polycrystalline semiconductor film 44 to the polycrystalline semiconductor film 42 is likely to become large.

[0128] In the polycrystalline semiconductor film 42, there is a tendency that the diffusion length of the N-type impurities diffused through the grain boundaries becomes longer, but the diffusion length of the N-type impurities diffused through the crystals becomes shorter. When the average grain size of the polycrystalline semiconductor film 42 is relatively large evenly, the influence of the deviation of the diffusion path tends to become larger. That is, the ratio of the N-type impurities diffused through the crystals to the N-type impurities diffused through the grain boundaries becomes larger, and the deviation of the diffusion length of the N-type impurities caused by the difference in the diffusion path tends to become larger.

[0129] This tendency may become significant due to the influence of the deviation of the Z height of the core member 19. For example, in the case where the Z height of the core member 19 is relatively high, the +Z side end of the core member 19 is at the desired Z position Zb (reference Figure 6 The Z distance of (a)) becomes longer, and it is not easy to diffuse to the desired Z position Zb. When the Z height of the core member 19 is relatively low, the +Z side end of the core member 19 is closer to the desired Z position Zb (reference Figure 6 The Z distance of (a)) is shortened, making it easier to diffuse to the desired Z position Zb.

[0130] Due to variations in the diffusion length of the N-type impurity, the amount of diffusion of the N-type impurity from the polycrystalline semiconductor film 44 to the polycrystalline semiconductor film 42 may be excessive.

[0131] That is to say, Figure 6As shown by the dashed line in (a), in the polycrystalline semiconductor film 42, N-type impurities having a threshold concentration Cth or higher are contained in the channel region of the selection gate SGD. As a result, the selection gate SGD is turned on when not selected, and it is difficult to properly turn on and off the selection gate SGD, and the reliability of the operation of the semiconductor memory device 1 may be deteriorated.

[0132] Alternatively, due to variations in the diffusion length of the N-type impurities, the diffusion amount of the N-type impurities from the polycrystalline semiconductor film 44 to the polycrystalline semiconductor film 42 may be insufficient.

[0133] That is to say, Figure 6 As shown by the dotted line in (a), in the polycrystalline semiconductor film 42, the N-type impurities in the channel region of the selection gate SGDT are suppressed to below the threshold concentration Cth. As a result, the GIDL in the selection gate SGDT during the erase process becomes insufficient, resulting in erase failure, making it difficult to properly perform the erase process, and the reliability of the operation of the semiconductor memory device 1 may be deteriorated.

[0134] Meanwhile, in the embodiment, the average grain size d1 of the portion 42a of the polycrystalline semiconductor film 42 is smaller than the average grain size d2 of the portion 42b. This allows the diffusion amount of the N-type impurity from the polycrystalline semiconductor film 44 into the portion 42a and the portion 42b to be appropriately controlled.

[0135] In the polycrystalline semiconductor film 42, the influence of the deviation of the diffusion path can be reduced. That is, the ratio of the N-type impurities diffused through the crystal to the N-type impurities diffused through the grain boundary becomes smaller, and the deviation of the diffusion length of the N-type impurities caused by the difference in the diffusion path can be reduced. As a result, the influence of the deviation of the Z height of the core part 19 can be reduced.

[0136] For example, Figure 6 As shown by the solid line in (a), in the polycrystalline semiconductor film 42, N-type impurities having a threshold concentration Cth or higher are contained in the channel region of the selection gate SGDT, but N-type impurities in the channel region of the selection gate SGD are suppressed to be less than the threshold concentration Cth. As a result, since the GIDL generation in the selection gate SGDT during the erase process can be made more efficient and the selection gate SGD can be appropriately turned on and off, the reliability of the operation of the semiconductor memory device 1 can be improved.

[0137] As a variation of the embodiment, in the method for manufacturing the semiconductor memory device 1 , the step of partially amorphizing the polycrystalline semiconductor film 42 j and the step of burying the polycrystalline semiconductor film 44 i in the recess 261 may be performed in a different order.

[0138] For example, instead of Figure 13-14 The steps shown are Figure 17-18 Steps shown. Figure 17-18Each of them is a YZ cross-sectional view showing a method of manufacturing semiconductor memory device 1 according to a modification of the embodiment.

[0139] In the same manner as in the embodiment Figure 7 to Figure 12 After following the steps shown, proceed Fig.17 Steps shown. Fig.17 In the steps shown, specified particles are introduced into the polycrystalline semiconductor film 42j up to a specified Z position by a particle implantation method or the like, so that a portion 42ak of the polycrystalline semiconductor film 42k up to the specified Z position is rendered amorphous, while a portion 42bk deeper than the specified Z position is not rendered amorphous and remains in a polycrystalline state.

[0140] The prescribed particles include any particles suitable for amorphization. The prescribed particles may be arsenic ions or argon molecules. The prescribed Z position may be a Z position between the Z position of the surface on the +Z side of the sacrificial layer 13 closest to the +Z side and the Z position of the surface on the +Z side of the sacrificial layer 13 closest to the +Z side. When the particle injection method is used, the prescribed Z position may be controlled by the acceleration voltage of the particle injection.

[0141] exist Fig.18 In the step shown, a polycrystalline semiconductor film 44i is buried in the recess 261. The polycrystalline semiconductor film 44i can be formed of a material containing a polycrystalline semiconductor (eg, polycrystalline silicon) containing an impurity (eg, phosphorus) as a main component.

[0142] The XY direction width D44i of the polycrystalline semiconductor film 44i corresponds to the average grain size d3. The XY direction width D44i is larger than the film thickness D42j (refer to Fig.11 ) and is greater than the film thickness D42i (reference Fig.10 ). Accordingly, the average particle size d3 is larger than the average particle size d1, and larger than the average particle size d2.

[0143] Afterwards, proceed Fig.15 Follow the steps shown.

[0144] According to such a manufacturing method, it is also possible to manufacture the semiconductor memory device 1 including the polycrystalline semiconductor film 42 in which the average grain size d1 of the portion 42 a is smaller than the average grain size d2 of the portion 42 b .

[0145] Although several embodiments of the present invention have been described, the embodiments are presented as examples and are not intended to limit the scope of the invention. The novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. The embodiments or their variations are included in the scope or spirit of the invention, and are included in the invention described in the claims and their equivalents.

[0146] [Explanation of Symbols]

[0147] 1: Semiconductor storage device

[0148] 6: Conductive layer

[0149] 7: Insulation layer

[0150] 42,42i,42j,44,44i: Polycrystalline semiconductor film

[0151] 43: Insulation film

[0152] SST,SSTi,SSTj:Layered

[0153] SUB: Substrate.

Claims

1. A semiconductor storage device comprising: Substrate: A laminated body is disposed above the substrate, wherein a plurality of conductive layers are laminated via insulating layers; A first polycrystalline semiconductor film extends in the stacking direction within the stacking body; and a first insulating film extending in the stacking direction between the plurality of conductive layers and the first polycrystalline semiconductor film in the stacking body; and The first polycrystalline semiconductor film includes: a first portion corresponding to a first conductive layer farthest from the substrate among the plurality of conductive layers; and The second portion corresponds to two or more conductive layers among the plurality of conductive layers disposed between the substrate and the first conductive layer; and The height of the boundary between the first portion and the second portion from the substrate is between the height of the upper surface of the first conductive layer from the substrate and the height of the upper surface of the second conductive layer farthest from the substrate among the two or more conductive layers from the substrate; The average particle size of the first part is smaller than the average particle size of the second part.

2. The semiconductor memory device according to claim 1, wherein A height between a boundary between the first portion and the second portion and the substrate is equal to a height between a lower surface of the first conductive layer and the substrate.

3. The semiconductor memory device according to claim 1, further comprising: a second insulating film extending in the stacking direction on the side opposite to the plurality of conductive layers with respect to the first polycrystalline semiconductor film in the stacking body; and The second polycrystalline semiconductor film covers an end portion of the first polycrystalline semiconductor film and an end portion of the second insulating film, and contains impurities.

4. The semiconductor memory device according to claim 3, wherein The grain size of the first portion is smaller than the grain size of the second polycrystalline semiconductor film.

5. The semiconductor memory device according to claim 3, wherein A diffusion distance of the impurities in the first polycrystalline semiconductor film from the second polycrystalline semiconductor film in the stacking direction is equal to a distance from an interface between the second polycrystalline semiconductor film and the first polycrystalline semiconductor film to the boundary in the stacking direction.

Images