BCD process device and preparation method thereof

Abstract

The invention belongs to the field of BCD process and discrete devices, and relates to a BCD process device and a preparation method thereof, the BCD process device comprises an N + substrate, an epitaxial layer NEPI-1 and an epitaxial layer NEPI-2; a PBL area is arranged at the joint of the NEPI-1 and the NEPI-2, and a DPWELL area is arranged on the right side of the PBL area in the NEPI-2. The left side of the DPWELL region in the NEPI-2 is provided with an NDRIFT region of the LDMOS and a PWEL-1 region; an SGT deep groove of the SGT-VDMOS and a PWELL-2 region are arranged on the right side of the DPWELL region in the NEPI-2; the NDRIFT region is provided with an N + region; the PWELL-1 region is provided with an N + region and a P + region; the DPWELL region is provided with a P + region, and the PWELL-2 region is provided with an N + region and a P + region; grid electrodes are arranged above the PWEL-1 region and the DPWELL region, and a metal layer is arranged above the PWELL-2 region; the SGT-VDMOS and the VDMOS are simultaneously integrated in the same process, and the SGT-VDMOS and the LDMOS are isolated by preparing the PBL region and the DPWELL region, so that the integrated BCD process device simultaneously has the advantages that the gate, the source and the drain of the LDMOS device are positioned on the surface of a chip and are easy to integrate and the advantages of high voltage, low resistance and high current of the SGT-VDMOS device.

Description

Technical Field

[0001] The invention belongs to the field of BCD technology and discrete devices, and relates to a BCD technology device and a preparation method thereof. Background Art

[0002] In recent years, power integration technology has developed rapidly, and power integrated circuit design represented by smart power integrated circuit (SPIC) has made great progress.

[0003] In the field of high-voltage SPIC, the BCD process is generally used for manufacturing and processing, due to the limitations of the BCD process device performance, including low current, low withstand voltage, high on-resistance and other issues. The development of higher voltage, faster speed and lower resistance SPIC has put forward higher requirements for devices.

[0004] The power tube of the traditional BCD process is made of Lateral Diffused MOSFET (LDMOS). Since the LDMOS device itself is a lateral device, its current flows in the horizontal direction. Due to the limitation of the silicon material itself, the relationship between the resistance and withstand voltage of the device cannot break the silicon limit. As power integrated circuits continue to expand to higher voltage and higher current application fields, the current and voltage of traditional LDMOS devices have great limitations and cannot meet the growing urgent demand for high voltage and high current.

[0005] The dual-gate structure of the Split Gate Transistor-Vertical Diffused MOSFET (SGT-VDMOS) device in high-voltage power integrated circuits can adjust the electric field in the drift region of the device, greatly reduce the on-resistance of the device, and can be widely used in various power integrated circuits. It has many advantages. Therefore, the research on SGT-VDMOS and LDMOS process integration is of great significance to high-voltage power integrated circuits.

[0006] However, since VDMOS is a vertical device, it has significant process differences from the lateral LDMOS device. How to integrate SGT-VDMOS devices and VDMOS devices in the same process is a key and difficult issue that needs to be studied in power integration. Summary of the invention

[0007] In order to solve the above-mentioned prior art problems, the present invention adopts a BCD process device, including: an N+ substrate, an epitaxial layer N EPI-1 and located in the epitaxial layer N EPI-1 The epitaxial layer NEPI-2 ;

[0008] Epitaxial layer N EPI-1 and epitaxial layer N EPI-2 There is a PBL area at the left connection; the epitaxial layer N EPI-2 There is a DP on the right side of the PBL area. WELL Area; epitaxial layer N EPI-2 Medium DP WELL The left side of the area has an LDMOS N DRIFT Area and P WELL-1 Area; epitaxial layer N EPI-2 Medium DP WELL The right side of the area has SGT deep trench and P WELL-2 district;

[0009] N DRIFT There are N+ area and P WELL-1 There are N+ area and P+ area in the area, DP WELL There is a P+ zone in the zone, P WELL-2 There are N+ area and P+ area from top to bottom in the area; WELL-1 Area and DP WELL The gate of the BCD process device is located above the region, WELL-2 A metal layer is provided above the region;

[0010] Among them, the N+ substrate is the drain of the BCD process device, and the N DRIFT The N+ region in the region is the source of the BCD process device. DRIFT represents the drift region, P WELL-1 represents the first P well, P WELL-2 Represents the second P well, DP WELL It represents deep P well, PBL represents phosphorus buried layer, SGT represents split gate field effect transistor, and N+ and P+ represent highly doped N-type and P-type regions respectively.

[0011] P WELL-1 Area and DP WELL An STI region is provided between the regions, and an STI region is provided on the right side of the first N+ region; wherein the STI is a shallow trench isolation.

[0012] The metal layer is provided with an isolation area and a metal area from bottom to top; the isolation area and the P WELL-2 The N+ region of the area is provided with a through hole, and the metal area is connected to the P WELL-2 The N+ region and the P+ region of the region are connected.

[0013] There are multiple SGT deep grooves, each of which is provided with a POLY area, a GPOLY area and a SGPOLY area; WELL-2The region is set in the area between the SGT deep trenches; wherein POLY, GPOLY and SGPOLY represent polysilicon, gate polysilicon and split gate polysilicon, respectively.

[0014] On the other hand, a method for preparing a BCD process device includes:

[0015] S1. Obtain an N+ substrate and grow an epitaxial layer N on the N+ substrate. EPI-1 ;

[0016] S2, in the epitaxial layer N EPI-1 PBL was injected into the left area to form a PBL zone;

[0017] S3, in the epitaxial layer N EPI-1 The epitaxial layer N EPI-2 ;

[0018] S4, in the epitaxial layer N EPI-2 P-type dopants are injected into the DP WELL District, in DP WELL SGT deep grooves are etched on the right side of the area;

[0019] S5, manufacturing an SGT gate in the SGT deep trench to form a POLY region, a GPOLY region, and a SGPOLY region;

[0020] S6, in the epitaxial layer N EPI-2 N-type dopants and P-type dopants are implanted in the DP WELL The left side of the area forms N DRIFT Area and P WELL-1 District, in DP WELL The right side of the area forms P WELL-2 district;

[0021] S7, in N DRIFT Area, P WELL Area, P WELL-1 Area and P WELL-2 N-type dopants and P-type dopants are implanted into the region to form an N+ region and a P+ region;

[0022] S8, in N DRIFT Area and P WELL The gate is grown above the P WELL-2 A metal layer is grown over the region.

[0023] Before step S7, DRIFT Within the area and in P WELL-1 The STI region is etched and grown on the right side of the region.

[0024] Beneficial effects:

[0025] The VDMOS device structure is a vertical device, and the LDMOS device structure is a lateral device, which is difficult to integrate directly. Therefore, the present invention integrates SGT-VDMOS and LDMOS in the same set of processes, and prepares the PBL region and the DP WELL The area is used to isolate SGT-VDMOS and LDMOS, so that the integrated BCD process device has both the advantages of LDMOS device gate, source and drain located on the chip surface for easy integration and the advantages of SGT-VDMOS device high voltage, low resistance and large current. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A structural diagram of a BCD process device integrating SGT-VDMOS and LDMOS provided in an embodiment of the present invention;

[0027] Figure 2 A flow chart of a method for preparing a BCD process device integrating SGT-VDMOS and LDMOS provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] like Figure 1 As shown, this embodiment adopts a BCD process device, including: an N+ substrate, an epitaxial layer N located above the N+ substrate EPI-1 and located in the epitaxial layer N EPI-1 The epitaxial layer N EPI-2 ;

[0030] Epitaxial layer N EPI-1 and epitaxial layer N EPI-2 There is a PBL area at the left connection; the epitaxial layer N EPI-2 There is a DP on the right side of the PBL area. WELL Area; epitaxial layer N EPI-2 Medium DP WELL The left side of the area has an LDMOS N DRIFT Area and P WELL-1 Area; epitaxial layer N EPI-2 Medium DP WELL The right side of the area has SGT deep trench and P WELL-2 district;

[0031] Among them, the N+ substrate is the drain of the BCD process device, and the N DRIFTrepresents the drift region; P WELL-1 represents the first P well, P WELL-2 PBL stands for the second P well, which is used to isolate different areas and prevent current leakage; PBL stands for phosphorus buried layer, DP WELL It stands for deep P-well, which is used to isolate SGT-VDMOS and LDMOS. SGT stands for split gate field effect transistor, which is used to increase the breakdown voltage of the device and reduce the on-resistance.

[0032] N DRIFT A first N+ region is provided in the region, and the first N+ region is the source of the BCD process device; WELL-1 From left to right, there are the second N+ region, the first P+ region and the third N+ region; WELL There is a second P+ zone in the zone, P WELL-2 The fourth N+ region and the fifth P+ region are arranged in sequence from top to bottom in the region; WELL-1 Area and DP WELL The gate (GATE) of the BCD process device is provided above the region to control the flow of current. WELL-2 A metal layer is provided above the region for forming electrode contacts and wiring;

[0033] The metal layer is provided with an isolation region and a metal region (MET) in sequence from bottom to top; the isolation region and the fourth N+ region are provided with through holes, and the metal region is connected with the fourth N+ region and the fifth P+ region through the through holes.

[0034] P WELL-1 Area and DP WELL An STI region is provided between the regions, and an STI region is provided on the right side of the first N+ region; wherein STI is a shallow trench isolation, which is used to isolate different regions.

[0035] There are four SGT deep trenches, which are arranged in the epitaxial layer N from left to right. EPI-2 DP WELL On the right side of the area, an isolation area is set in the SGT deep groove; among them, the leftmost SGT deep groove is provided with a POLY area, and the remaining SGT deep grooves are provided with a GPOLY area and a SGPOLY area from top to bottom; P WELL-2 The region is set in the area between the SGT deep trenches; wherein POLY, GPOLY and SGPOLY represent polysilicon, gate polysilicon and split gate polysilicon, respectively.

[0036] In one embodiment, a method for manufacturing the above-mentioned BCD process device integrating SGT-VDMOS and LDMOS is provided, comprising:

[0037] S1. Obtain an N+ substrate and grow an epitaxial layer N on the N+ substrate. EPI-1 ;

[0038] S2, in the epitaxial layer N EPI-1 PBL was injected into the left area to form a PBL zone;

[0039] S3, in the epitaxial layer N EPI-1 The epitaxial layer N EPI-2 ;

[0040] S4, in the epitaxial layer N EPI-2 P-type dopants are injected into the DP WELL District, in DP WELL SGT deep grooves are etched on the right side of the area;

[0041] S5, manufacturing an SGT gate in the SGT deep trench to form a POLY region, a GPOLY region, and a SGPOLY region;

[0042] S6, in the epitaxial layer N EPI-2 N-type dopants and P-type dopants are implanted in the DP WELL The left side of the area forms N DRIFT Area and P WELL-1 District, in DP WELL The right side of the area forms P WELL-2 Area; in N DRIFT Within the area and in P WELL-1 The STI region is etched and grown on the right side of the region;

[0043] S7, in N DRIFT Area, P WELL Area, P WELL-1 Area and P WELL-2 N-type dopants and P-type dopants are implanted into the region to form an N+ region and a P+ region;

[0044] S8, in N DRIFT Area and P WELL The gate is grown above the P WELL-2 A metal layer is grown over the region.

[0045] The above embodiments further illustrate the purpose, technical solutions and advantages of the present invention in detail. It should be understood that the above embodiments are only preferred implementation modes of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made to the present invention within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A BCD process device, characterized in that: include: N+ substrate, epitaxial layer N on top of the N+ substrate EPI-1 and located in the epitaxial layer N EPI-1 The epitaxial layer N EPI-2 ; Epitaxial layer N EPI-1 and epitaxial layer N EPI-2 There is a PBL area at the left connection; the epitaxial layer N EPI-2 There is a DP on the right side of the PBL area WELL Area; epitaxial layer N EPI-2 Medium DP WELL The left side of the area has an LDMOS N DRIFT Area and P WELL-1 Area; epitaxial layer N EPI-2 Medium DP WELL The right side of the area has the SGT deep trench and P WELL-2 district; N DRIFT There are N+ area and P WELL-1 There are N+ area and P+ area in the area, DP WELL There is a P+ zone in the zone, P WELL-2 There are N+ area and P+ area from top to bottom in the area; WELL-1 Area and DP WELL The gate of the BCD process device is located above the region, WELL-2 A metal layer is provided above the region; Among them, the N+ substrate is the drain of the BCD process device, and the N DRIFT The N+ region in the region is the source of the BCD process device. DRIFT represents the drift region, P WELL-1 represents the first P well, P WELL-2 Represents the second P well, DP WELL It represents deep P well, PBL represents phosphorus buried layer, SGT represents split gate field effect transistor, N+ and P+ represent highly doped N-type and P-type regions respectively, LDMOS represents lateral double diffused metal oxide semiconductor, and VDMOS represents vertical double diffused metal oxide semiconductor.

2. A BCD process device according to claim 1, characterized in that: P WELL-1 Area and DP WELL An STI region is provided between the regions, and an STI region is provided on the right side of the first N+ region; wherein the STI is a shallow trench isolation.

3. A BCD process device according to claim 1, characterized in that: The metal layer is provided with an isolation area and a metal area from bottom to top; the isolation area and the P WELL-2 The N+ region of the area is provided with a through hole, and the metal area is connected to the P WELL-2 The N+ region and the P+ region of the region are connected.

4. A BCD process device according to claim 1, characterized in that: There are multiple SGT deep grooves, each of which is provided with a POLY area, a GPOLY area and a SGPOLY area; WELL-2 The region is set in the area between the SGT deep trenches; wherein POLY, GPOLY and SGPOLY represent polysilicon, gate polysilicon and split gate polysilicon, respectively.

5. A method for preparing a BCD process device as claimed in claims 1 to 4, characterized in that: include: S1. Obtain an N+ substrate and grow an epitaxial layer N on the N+ substrate. EPI-1 ; S2, in the epitaxial layer N EPI-1 PBL was injected into the left area to form a PBL zone; S3, in the epitaxial layer N EPI-1 The epitaxial layer N EPI-2 ; S4, in the epitaxial layer N EPI-2 P-type dopants are injected into the DP WELL District, in DP WELL SGT deep grooves are etched on the right side of the area; S5, manufacturing an SGT gate in the SGT deep trench to form a POLY region, a GPOLY region, and a SGPOLY region; S6, in the epitaxial layer N EPI-2 N-type dopants and P-type dopants are implanted in the DP WELL The left side of the area forms N DRIFT Area and P WELL-1 District, in DP WELL The right side of the area forms P WELL-2 district; S7, in N DRIFT Area, P WELL Area, P WELL-1 Area and P WELL-2 N-type dopants and P-type dopants are implanted into the region to form an N+ region and a P+ region; S8, in N DRIFT Area and P WELL The gate is grown above the P WELL-2 A metal layer is grown over the region.

6. The method for preparing a BCD process device according to claim 5, characterized in that: Before step S7, DRIFT Within the area and in P WELL-1 The STI region is etched and grown on the right side of the region.

Images