Digital fuel oil adjusting solenoid valve synchronous cooperative control system and method

Abstract

The invention discloses a digital fuel oil adjusting solenoid valve synchronous cooperative control system and method, the input end of an FPGA is connected with a main processor board and a current acquisition circuit, the output end of the FPGA is connected with a multi-channel fuel oil adjusting solenoid valve conditioning and driving circuit, the current acquisition circuit is connected with respective sampling resistor connected in series at each fuel oil adjusting solenoid valve, and the sampling resistor is connected with the main processor board and the current acquisition circuit. A q value output by a main processor board is converted into a carrier waveform, a current acquisition circuit is used for acquiring a current acquisition output waveform, an FPGA (Field Programmable Gate Array) carries out AND operation on the carrier waveform and the current acquisition output waveform, and FPGA output control waveforms, namely output control signals, of different channels are obtained according to synchronous cooperative control requirements. A plurality of paths of fuel oil adjusting electromagnetic valves are synchronously and cooperatively adjusted through a fuel oil adjusting electromagnetic valve conditioning and driving circuit, so that digital dynamic synchronous cooperative control of control parameters of the plurality of paths of fuel oil adjusting electromagnetic valves is realized; and meanwhile, the design complexity of the multi-pass fuel regulating circuit synchronous coordination system is reduced, and the occupied volume is reduced by half when the same function is realized.

Description

Technical Field

[0001] The present invention belongs to the technical field of fuel regulating solenoid valve control, and in particular relates to a digital fuel regulating solenoid valve synchronous coordinated control system and method. Background Art

[0002] Traditional fuel regulators automatically adjust the throttle switch opening to control the fuel supply by sensing information such as engine airflow parameters, speed feedback, and throttle angle. This process ensures that the engine can obtain the required amount of fuel under various flight and operating conditions, thereby ensuring its performance. Early fuel regulators mainly relied on mechanical control; with the development of technology, analog electronic control has gradually replaced traditional mechanical control. Analog electronic control adjusts fuel flow through sensors and electrical signals, improving control accuracy and response speed.

[0003] In recent years, digital electronic control technology has gradually become mainstream due to its higher flexibility and accuracy. Digital control technology can better handle complex control algorithms and real-time data, thereby further improving the accuracy of fuel regulation and system stability.

[0004] However, the existing digital electronic control technology is difficult to adjust the parameters, which is mainly completed by debugging multiple resistors and capacitors. The debugging workload is large. When the parameters need to be adjusted again after debugging is completed, the product needs to be disassembled and the relevant debugging resistors and capacitors need to be replaced to complete the adjustment. The control circuit is complex, occupies a large space, and has poor control accuracy, which cannot meet the application scenarios with high-precision requirements. As the number of control objects increases, the synchronous and coordinated control of multiple solenoid valves is difficult to achieve, and the synchronization accuracy is poor, which cannot meet the requirements of multi-channel coordinated control. Summary of the invention

[0005] The purpose of the present invention is to provide a digital fuel regulating solenoid valve synchronous cooperative control system and method to overcome the problems of existing digital electronic control technology for controlling regulating valves, such as complex control circuits, large space occupied, poor synchronous cooperative control progress, and inability to meet high-precision, real-time synchronous control requirements.

[0006] In order to solve the above problems, the present invention adopts the following technical solutions: A digital fuel regulating solenoid valve synchronous cooperative control system comprises a main processor board and a power supply module, wherein the main processor board is connected to an FPGA, the FPGA is unidirectionally connected to a plurality of fuel regulating solenoid valve conditioning and drive circuits, the fuel regulating solenoid valve conditioning and drive circuits are used to be connected to respective fuel regulating solenoid valves, the FPGA is bidirectionally connected to a current acquisition circuit, the current acquisition circuit is connected to a sampling resistor connected in series at each fuel regulating solenoid valve, the power supply module is connected to a VPX connector, and the VPX connector is respectively connected to the FPGA and the plurality of fuel regulating solenoid valve conditioning and drive circuits.

[0007] Furthermore, the control system also includes a detection circuit, which is respectively connected to the fuel regulating solenoid valve conditioning and driving circuit and the current collection circuit.

[0008] Furthermore, the main processor board and the FPGA are bidirectionally connected via a SRIO bus.

[0009] Furthermore, the FPGA and the VPX connector are bidirectionally connected via a SRIO bus.

[0010] Furthermore, the power supply module adopts a DC-DC module.

[0011] In a second aspect, a method for synchronous coordinated control of a digital fuel regulating solenoid valve is provided, comprising the following steps: FPGA receives the q value bound by the main processor board and obtains the carrier waveform according to the q value; The current acquisition circuit acquires the current acquisition output waveform of the sampling resistor connected in series at the fuel regulating solenoid valve; The carrier waveform and the current acquisition output waveform are ANDed together, and after synchronization with the synchronous control waveform, the FPGA output control waveform is obtained; The FPGA outputs the FPGA output control waveform to the fuel regulating solenoid valve conditioning and driving circuit, and the fuel regulating solenoid valve conditioning and driving circuit are used to synchronously and collaboratively regulate multiple fuel regulating solenoid valves.

[0012] Furthermore, the detection circuit is included to detect the output control waveform of the adjusted fuel regulating solenoid valve conditioning and driving circuit.

[0013] Furthermore, the FPGA receives the q value bound by the main processor board, and the steps of obtaining the carrier waveform according to the q value are as follows: The q value is converted into the period of the carrier signal and then written into the dual-port RAM inside the FPGA for parameter binding; After the carrier signal command is started, the binding value read from the dual-port RAM inside the FPGA each cycle produces a continuous carrier signal through the state machine.

[0014] Furthermore, the period of the carrier signal is:

[0015] Where f is the period of the carrier signal, q is the duty cycle signal, and f0 is the signal frequency under q.

[0016] Furthermore, the control method includes controlling the fuel regulating solenoid valve to reach a maximum value of the strong excitation current, a minimum value of the strong excitation current, a maximum value of the maintaining current, and a minimum value of the maintaining current.

[0017] Compared with the prior art, the present invention has the following beneficial technical effects: The present invention provides a digital fuel regulating solenoid valve synchronous cooperative control system, comprising an FPGA, wherein the input end of the FPGA is respectively connected to a main processor board and a current acquisition circuit, and the output end is connected to a multi-channel fuel regulating solenoid valve conditioning and driving circuit, the fuel regulating solenoid valve conditioning and driving circuit is used for synchronously and cooperatively controlling the fuel regulating solenoid valve, the current acquisition circuit collects the sampling resistor connected in series at the fuel regulating solenoid valve, and finally realizes synchronous and cooperative control of the fuel regulating solenoid valve through the FPGA output control signal, and the FPGA chip can be used to realize complex synchronous and cooperative control logic to realize accurate synchronous and cooperative control of the solenoid valve, and its control accuracy is determined by the counter accuracy inside the FPGA, will not be affected by the ambient temperature, and the control error is not greater than 100ppm; the upgrade is flexible, and the FPGA control algorithm can be flexibly upgraded according to actual needs, and the control parameters can be adjusted by changing the value of the control parameter register; the FPGA can realize parallel processing of multiple control objects and improve the synchronization of the control process; at the same time, the design complexity of the engine fuel regulating circuit system is reduced, the reliability is improved, the complexity of the control circuit is reduced by 40%, and the number of control targets realized in the same space is doubled.

[0018] Preferably, the control system also includes a detection circuit, which is respectively connected to the fuel regulating solenoid valve conditioning and driving circuit and the current acquisition circuit. After the adjustment of the fuel regulating solenoid valve is completed, the waveform output from the fuel regulating solenoid valve is detected to determine whether the adjustment of the fuel regulating solenoid valve is qualified.

[0019] The present invention provides a synchronous and coordinated control method for a digital fuel regulating solenoid valve, which converts the q value output by a main processor board into a carrier waveform, uses a current acquisition circuit to acquire a current acquisition output waveform, and performs ANDing of the carrier waveform and the current acquisition output waveform by an FPGA, and synchronizes the waveform through a synchronous control logic to obtain an FPGA output control waveform, i.e., an output control signal, and adjusts the fuel regulating solenoid valve through a fuel regulating solenoid valve conditioning and a driving circuit; realizes digital dynamic synchronous and coordinated adjustment of control parameters of the fuel regulating solenoid valve, improves the synchronization of control; improves control accuracy, and increases control accuracy to 100ppm; and reduces the design complexity of a synchronous and coordinated control system for multi-channel engine fuel regulating circuits, thereby reducing the volume occupied by the same function by half; and realizes parallel control of multi-channel control objects.

[0020] Preferably, the control method can realize the control of the fuel regulating solenoid valve to reach the maximum value of the strong excitation current, the minimum value of the strong excitation current, the maximum value of the maintaining current and the minimum value of the maintaining current. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a structural diagram of a digital fuel regulating solenoid valve synchronous cooperative control system in an embodiment of the present invention; Figure 2 It is a load current waveform diagram of each fuel regulating solenoid valve in the embodiment of the present invention; Figure 3 A schematic diagram of generating a synchronous coordinated carrier signal output by an FPGA in an embodiment of the present invention; Figure 4 It is a schematic diagram of the design of a fast valve driving circuit of a single fuel regulating solenoid valve in an embodiment of the present invention; Figure 5 This is the layout of the PFWM control driver board in the embodiment of the present invention; Figure 6 The present invention is a flowchart of a synchronous coordinated control method of a digital fuel regulating solenoid valve in an embodiment of the present invention. DETAILED DESCRIPTION

[0022] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0023] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0024] Glossary The SRIO bus is a high-performance, low-pin-count, packet-switching-based interconnect architecture that features high-speed transmission, dynamic asymmetric communication modes, flexible topology, powerful error detection capabilities, scalability, and flexibility.

[0025] As a key component of the VPX bus standard, VPX connectors have the characteristics of high-speed transmission, high reliability, low insertion loss and environmental adaptability. They have broad application prospects in the fields of military, aerospace, etc. VPX connectors play an important role in high-speed data transmission, system interconnection and integration, maintaining compatibility and introducing new functions, providing reliable electrical connections and adapting to harsh environments.

[0026] A DC-DC module is a device that converts electrical energy of one voltage value into electrical energy of another voltage value in a DC circuit.

[0027] A digital fuel regulating solenoid valve synchronous coordinated control system, such as Figure 1 , Figure 4 As shown, it includes a main processor board, FPGA, fuel regulating solenoid valve conditioning and driving circuit, current acquisition circuit, VPX connector and power supply module, wherein the main processor board is connected to the input end of the FPGA, the output end of the FPGA is linked to the input end of the fuel regulating solenoid valve conditioning and driving circuit, the output end of the fuel regulating solenoid valve conditioning and driving circuit is connected to the fuel regulating solenoid valve, and is used to issue control instructions to the fuel regulating solenoid valve, a sampling resistor is connected in series at the fuel regulating solenoid valve, the current acquisition circuit is used to collect the sampling resistor information voltage and convert it into a current acquisition output waveform, and transmit the current acquisition output waveform to the FPGA, the FPGA processes the current acquisition output waveform and the carrier signal generated by the main processor board input to the FPGA, and outputs a control waveform to adjust the fuel regulating solenoid valve; the power supply module is connected to the VPX connector, and the VPX connector is also connected to the FPGA and the fuel regulating solenoid valve conditioning and driving circuit respectively.

[0028] The FPGA contains an SRIO controller, a bus conversion interface logic, a fuel regulating solenoid valve control logic, and an AD conversion control logic. The bus conversion interface logic is bidirectionally connected to the SRIO controller, the fuel regulating solenoid valve control logic, and the AD conversion control logic.

[0029] Specifically, the main processor board and the FPGA are bidirectionally connected through the SRIO bus. The SRIO controller inside the FPGA receives the carrier frequency duty cycle signal, i.e., the q value, issued by the main processor board through the SRIO bus, and the FPGA transmits the relevant collected data to the main processor board.

[0030] The VPX connector and the SRIO controller inside the FPGA are bidirectionally connected through the SRIO bus; the fuel regulating solenoid valve conditioning and driving circuit is connected to the fuel regulating solenoid valve control logic inside the FPGA; the current acquisition circuit adopts an AD acquisition circuit, and the AD acquisition circuit is bidirectionally connected to the AD conversion control logic inside the FPGA.

[0031] In one embodiment provided by the present invention, Figure 1 , Figure 4 As shown, it includes a main processor board, FPGA, fuel regulating solenoid valve conditioning and driving circuit, current acquisition circuit, VPX connector and power supply module, wherein the main processor board is connected to the input end of the FPGA, the output end of the FPGA is linked to the input end of the multi-channel fuel regulating solenoid valve conditioning and driving circuit, the output end of the fuel regulating solenoid valve conditioning and driving circuit is connected to the fuel regulating solenoid valve, the current acquisition circuit is used to collect the sampling resistor information voltage and convert it into a current acquisition output waveform, and transmit the current acquisition output waveform to the FPGA, the power supply module is connected to the VPX connector, and the VPX connector is also respectively connected to the FPGA and the fuel regulating solenoid valve conditioning and driving circuit.

[0032] The control system also includes a detection circuit, which is respectively connected to the fuel regulating solenoid valve conditioning and driving circuit and the current acquisition circuit, and is used to detect the waveform output from the fuel regulating solenoid valve after the fuel regulating solenoid valve is adjusted, so as to determine whether the adjustment of the fuel regulating solenoid valve is qualified.

[0033] A synchronous cooperative control method is proposed for the above-mentioned digital fuel regulating solenoid valve synchronous cooperative control system. Figure 6 As shown, the following steps are included: Step 1, FPGA receives the q value bound by the main processor board and obtains the carrier waveform according to the q value; Step 2: The current collection circuit collects the current of the sampling resistor connected in series at the fuel regulating solenoid valve and outputs the following waveform: Step 3: AND the carrier waveform and the current acquisition output waveform, and synchronize them to obtain the FPGA output control waveform: Step 4: FPGA outputs the FPGA output control waveform to the fuel regulating solenoid valve conditioning and driving circuit, and the fuel regulating solenoid valve conditioning and driving circuit are used to synchronously and collaboratively adjust multiple fuel regulating solenoid valves.

[0034] In detail, the FPGA control logic realizes the fuel regulating solenoid valve drive signal to perform closed-loop control on the fuel regulating solenoid valve in real time, completes the detection processing of the pulse width drive signal and the acquisition of the conditioned signal, communicates with the CPU board (main processor board) through the SRIO bus, receives the control instructions of the CPU board, and returns the acquisition results.

[0035] FPGA receives the q value bound by the main processor board through the SRIO bus, where the q value is the carrier frequency duty cycle signal. The q value is converted into the period of the carrier signal and written into the dual-port RAM inside the FPGA for parameter binding. After the carrier signal command is started, the binding value read from the dual-port RAM inside the FPGA in each period produces a continuous carrier signal through the state machine. If the q value is changed externally, the binding value in the dual-port RAM inside the FPGA is updated once, and the frequency of the carrier signal is synchronized according to the q value and updated in real time in the next period. The calculation formula of the carrier signal period is:

[0036] Where f is the period of the carrier signal, q is the duty cycle signal, and f0 is the signal frequency under q.

[0037] At the same time, the AD acquisition circuit continuously collects the voltage value of the sampling resistor connected in series on the fuel regulating solenoid valve and controls the output of an IO signal inside the FPGA, such as Figure 3 As shown, the above carrier signal and the IO signal (current acquisition output waveform) are ANDed to generate the control signal of the fuel regulating solenoid valve, i.e., the FPGA output control waveform. If the continuous acquisition value reaches the maximum value (V1) of the strong excitation current of the fuel regulating solenoid valve, the IO signal is changed from high level to low level to close the fuel regulating solenoid valve. If the continuous acquisition value reaches the minimum value (V2) of the strong excitation current of the fuel regulating solenoid valve, the IO signal is changed from low level to high level to open the fuel regulating solenoid valve (the strong excitation current is judged three times continuously for the maximum and minimum values). The above processing method is also adopted for the maintaining current. When the maximum value (V3) of the maintaining current (calculation method) is continuously judged, the IO signal is enabled to change from high level to low level, and the fuel regulating solenoid valve is closed. When the minimum value (V4) of the maintaining current is judged, the IO signal is enabled to change from low level to high level, and the fuel regulating solenoid valve is opened. The above process is controlled by the FPGA on the core board. The AD converter module continuously samples the high and low change pulse waveform of the control IO signal, and generates the control of the opening and closing of the fuel regulating solenoid valve after the 0~40Hz carrier modulation signal generated by the FPGA, thereby realizing real-time synchronous and coordinated control of the fuel regulating solenoid valve.

[0038] The current waveform output by the control circuit is as follows: Figure 2 As shown, In is the median of the strike current, the maximum strike current is In+1 / 2△In, the minimum strike current is In-1 / 2△In, Iy is the median of the maintaining current, the maximum maintaining current is Iy+1 / 2△Iy, the minimum maintaining current is Iy-1 / 2△Iy, Tq is the period, and Tu / Tq is the duty cycle.

[0039] On the other hand, the fuel regulating solenoid valve conditioning and driving circuit produces a DC voltage with a linear relationship through the detection circuit for external detection. The control signal waveform diagram generated by FPGA is shown in the figure below: Figure 3 As shown in the figure, the schematic diagram of the fuel regulating solenoid valve drive circuit design is as follows Figure 4 shown.

[0040] The control signal of the fuel regulating solenoid valve is directly generated by the carrier signal, which can meet the driving interface requirements of the ram fuel regulating solenoid valve.

[0041] In another embodiment provided by the present invention, Figure 5 As shown, the function of the PFWM output drive control circuit designed and developed according to the design concept of the present invention is to adjust the control output command of the main computer board into a drive signal of the control system actuator to drive the control system actuator. The drive signal required by the control system actuator is a pulse width modulation frequency modulation signal (0Hz~40Hz carrier signal, 3KHz~5KHz modulation signal). Coil winding DC resistance (normal temperature 20℃): (14±2.8)Ω. The relationship between the carrier frequency and the waveform duty cycle satisfies the formula , f0 is the signal frequency when the duty cycle is 50%, f0 = 40Hz, the accuracy requirement is ±10%; where is the duty cycle signal (0% ~ 100%). A reverse suppression circuit is set in the drive signal output circuit to eliminate the reverse electromotive force generated by the inductor coil of the solenoid valve. Under the conditions of 1000HZ and 10V, the inductance is 20±5mH.

[0042] The PFWM control driver board adopts the VPX 3U standard design, which mainly realizes the functions of 2-way fuel regulating solenoid valve fast valve drive circuit control and signal conditioning and acquisition circuit. It is mainly composed of FPGA devices, DA converters, AD converters, optocouplers, operational amplifiers and power operational amplifiers, MOS tubes, DC-DC power supplies and other parts. The PFWM control driver board generates 2-way fuel regulating solenoid valve fast valve drive signals from the SRIO interface FPGA circuit for real-time closed-loop control of the fuel regulating solenoid valve, and completes the detection processing of the pulse width drive signal and the acquisition of the conditioned signal. It communicates with the CPU board through the SRIO bus, receives the control instructions of the CPU board, and returns the acquisition results. The PFWM drive control circuit has a duty cycle signal output terminal after detection, which is used to test the duty cycle signal and perform system closed-loop testing. At the same time, the circuit design realizes the detection of the circuit breaker fault mode of the control system actuator, meeting the requirements of the control system emission inspection.

[0043] The preferred embodiments of the present invention are described in detail above, but the present invention is not limited thereto. Within the technical concept of the present invention, the technical solution of the present invention can be subjected to a variety of simple modifications, including the combination of various technical features in any other suitable manner, and these simple modifications and combinations should also be regarded as the contents disclosed by the present invention and belong to the protection scope of the present invention.

Claims

1. A digital fuel regulating solenoid valve synchronous coordinated control system, characterized in that: It includes a main processor board and a power supply module. The main processor board is connected to an FPGA. The FPGA is unidirectionally connected to a multi-way fuel regulating solenoid valve conditioning and drive circuit. The fuel regulating solenoid valve conditioning and drive circuit is used to be connected to the fuel regulating solenoid valve. The FPGA is bidirectionally connected to a current acquisition circuit. The current acquisition circuit is connected to a sampling resistor connected in series at the multi-way fuel regulating solenoid valve. The power supply module is connected to a VPX connector. The VPX connector is respectively connected to the FPGA and the multi-way fuel regulating solenoid valve conditioning and drive circuit.

2. A digital fuel regulating solenoid valve synchronous coordinated control system according to claim 1, characterized in that: The control system also includes a detection circuit, which is respectively connected to a multi-channel fuel regulating solenoid valve conditioning and driving circuit and a current collection circuit.

3. A digital fuel regulating solenoid valve synchronous coordinated control system according to claim 1, characterized in that: The main processor board and the FPGA are bidirectionally connected via the SRIO bus.

4. A digital fuel regulating solenoid valve synchronous coordinated control system according to claim 1, characterized in that: The FPGA and the VPX connector are bidirectionally connected via the SRIO bus.

5. A digital fuel regulating solenoid valve synchronous coordinated control system according to claim 1, characterized in that: The power supply module adopts a DC-DC module.

6. A synchronous coordinated control method for a digital fuel regulating solenoid valve according to claim 1, characterized in that: The following steps are involved: FPGA receives the q value bound by the main processor board and obtains the carrier waveform according to the q value; The current acquisition circuit acquires the current acquisition output waveform of the sampling resistor connected in series at the fuel regulating solenoid valve; The carrier waveform and the current acquisition output waveform are ANDed together, and the FPGA output control waveform is obtained according to the synchronous coordinated control requirements; The FPGA outputs the FPGA output control waveform to each fuel regulating solenoid valve conditioning and driving circuit, and the fuel regulating solenoid valve conditioning and driving circuit are used to synchronously and collaboratively adjust multiple fuel regulating solenoid valves.

7. A digital fuel regulating solenoid valve synchronous coordinated control method according to claim 6, characterized in that: The invention also includes a detection circuit which simultaneously detects the output control waveform of the adjusted fuel regulating solenoid valve and the driving circuit.

8. A synchronous coordinated control method for a digital fuel regulating solenoid valve according to claim 6, characterized in that: The FPGA receives the q value bound by the main processor board, and the steps of obtaining the carrier waveform according to the q value are as follows: The q value is converted into the period of the carrier signal and then written into the dual-port RAM inside the FPGA for parameter binding; After the carrier signal command is started, the binding value read from the dual-port RAM inside the FPGA each cycle produces a continuous carrier signal through the state machine.

9. A synchronous coordinated control method for a digital fuel regulating solenoid valve according to claim 8, characterized in that: The period of the carrier signal is: Where f is the period of the carrier signal, q is the duty cycle signal, and f0 is the signal frequency under q.

10. A synchronous coordinated control method for a digital fuel regulating solenoid valve according to claim 6, characterized in that: The control method includes controlling the fuel regulating solenoid valve to reach a maximum value of a strong excitation current, a minimum value of a strong excitation current, a maximum value of a maintaining current, and a minimum value of a maintaining current.

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