Display device

Abstract

According to one aspect of the present disclosure, a display device includes: a display panel in which a plurality of sub-pixels are defined; a first light emitting diode disposed in each of the plurality of sub-pixels; a second light emitting diode connected in series with the first light emitting diode; a first control transistor connected in parallel with the first light emitting diode and turned on by a first control signal; and a second control transistor connected in parallel with the second light emitting diode and turned on by a second control signal. Accordingly, the first light emitting diode and the second light emitting diode may be independently controlled using the first control transistor and the second control transistor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2023-0125525 filed in the Korean Intellectual Property Office on September 20, 2023, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device, and more particularly, to a display device using a light emitting diode (LED). Background Art

[0004] As a display device for a monitor of a computer, a television, or a cellular phone, there are an organic light emitting display (OLED) device which is a self-light emitting device, a liquid crystal display (LCD) device which requires a separate light source, and the like.

[0005] The application range of the display device is diversified to personal digital assistants and monitors of computers and televisions, and display devices having a large display area and reduced volume and weight are being studied.

[0006] In addition, recently, a display device including a light emitting diode (LED) has attracted attention as a next-generation display device. Since LED is formed of an inorganic material rather than an organic material, it has excellent reliability, making its life longer than that of a liquid crystal display device or an organic light emitting display device. In addition, LED has a fast lighting speed, excellent luminous efficiency, and strong impact resistance, making it excellent in stability and able to display images with high brightness. Summary of the invention

[0007] An object to be achieved by the present disclosure is to provide a display device in which dark spot defects of sub-pixels are reduced.

[0008] Another object to be achieved by the present disclosure is to provide a display device, wherein a plurality of light emitting diodes are disposed in a sub-pixel to reduce malfunction of the sub-pixel.

[0009] Another object to be achieved by the present disclosure is to provide a display device in which a plurality of light emitting diodes are arranged in a sub-pixel to display an image with high resolution.

[0010] Still another object to be achieved by the present disclosure is to provide a display device, in which, even if an open circuit defect or a short circuit defect occurs in one of a plurality of light emitting diodes connected in series, the remaining light emitting diodes are normally driven.

[0011] Still another object to be achieved by the present disclosure is to provide a display device, in which, when some light emitting diodes are defective, a path is provided for a driving current to detour through.

[0012] Still another object to be achieved by the present disclosure is to provide a display device which adds a minimum number of transistors to control a plurality of light emitting diodes.

[0013] The objects of the present disclosure are not limited to the above objects, and other objects not mentioned above can be clearly understood by those skilled in the art from the following description.

[0014] According to one aspect of the present disclosure, a display device includes: a display panel in which a plurality of sub-pixels are defined; a first light-emitting diode disposed in each of the plurality of sub-pixels; a second light-emitting diode connected in series with the first light-emitting diode; a first control transistor connected in parallel with the first light-emitting diode and turned on by a first control signal; and a second control transistor connected in parallel with the second light-emitting diode and turned on by a second control signal. Therefore, the first light-emitting diode and the second light-emitting diode can be independently controlled using the first control transistor and the second control transistor connected in parallel with the first light-emitting diode and the second light-emitting diode, respectively.

[0015] According to another aspect of the present disclosure, a display device includes: a substrate; an adhesive layer, the adhesive layer being disposed on the substrate; a first light-emitting diode, the first light-emitting diode being disposed on the adhesive layer and including a first anode and a first cathode; a second light-emitting diode, the second light-emitting diode being disposed on the adhesive layer and including a second anode and a second cathode; a plurality of reflective electrodes, the plurality of reflective electrodes being disposed between the substrate and the adhesive layer. The plurality of reflective electrodes include: a first reflective electrode, the first reflective electrode being electrically connected to the first anode; a second reflective electrode, the second reflective electrode being electrically connected to the first cathode and the second anode; and a third reflective electrode, the third reflective electrode being electrically connected to the second cathode. Therefore, the first light-emitting diode and the second light-emitting diode can be connected in series using a plurality of reflective electrodes.

[0016] Additional details of exemplary embodiments are included in the Detailed Description and the accompanying drawings.

[0017] According to the present disclosure, dark spot defects of sub-pixels are reduced to improve the reliability of a display device.

[0018] According to the present disclosure, a plurality of light emitting diodes are disposed in a sub-pixel to display an image with a higher resolution.

[0019] According to the present disclosure, a plurality of light emitting diodes are disposed in a sub-pixel, and when some of the light emitting diodes are defective, the remaining light emitting diodes are used to normally drive the sub-pixel.

[0020] According to the present disclosure, even if some of the plurality of light emitting diodes connected in series are defective, the remaining light emitting diodes can be normally driven using transistors through which a driving current is bypassed.

[0021] According to the present disclosure, a control transistor is connected in parallel with each of a plurality of light emitting diodes to provide a path allowing a driving current to detour when some of the light emitting diodes are defective.

[0022] According to the present disclosure, a control transistor is connected in parallel to each of a plurality of light emitting diodes to individually control the light emitting diodes.

[0023] According to the present disclosure, a minimum number of transistors are added to control multiple light emitting diodes.

[0024] The effects according to the present disclosure are not limited to those exemplified above, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0026] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure;

[0027] Figure 2A is a partial cross-sectional view of a display device according to an exemplary embodiment of the present disclosure;

[0028] Figure 2B is a perspective view of a spliced ​​display device according to an exemplary embodiment of the present disclosure;

[0029] Figure 3 is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure;

[0030] Figure 4A is a driving timing diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure when a first light emitting diode emits light;

[0031] Figure 4B is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure for explaining a flow of a driving current when a first light emitting diode emits light;

[0032] Figure 5A is a driving timing diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure when a second light emitting diode emits light;

[0033] Figure 5Bis a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure for explaining a flow of a driving current when a second light emitting diode emits light;

[0034] Figure 6 is a plan view of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure;

[0035] Figure 7 It is along Figure 6 Cross-sectional views taken along lines VIIa-VIIa' and VIIb-VIIb';

[0036] Figure 8 is a diagram of a gate driver of a display device according to an exemplary embodiment of the present disclosure;

[0037] Fig. 9 is a circuit diagram of a control signal generating circuit of a display device according to an exemplary embodiment of the present disclosure; and

[0038] Fig.10 is a driving timing diagram of a control signal generating circuit of a display device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] By referring to the exemplary embodiments described in detail below and the accompanying drawings, the advantages and features of the present disclosure and the methods for achieving these advantages and features will be clear. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only as examples so that those skilled in the art can fully understand the content disclosed in the present disclosure and the scope of the present disclosure.

[0040] The shapes, sizes, ratios, angles, quantities, etc. shown in the drawings for describing exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals generally represent the same elements. In addition, in the following description of the present disclosure, a detailed explanation of known related art may be omitted to avoid making the subject matter of the present disclosure unnecessarily difficult to understand. Terms such as "including", "having" and "consisting of..." used herein are generally intended to allow the addition of other components unless these terms are used together with the term "only". Unless otherwise expressly stated, any reference to the singular may include the plural.

[0041] Even if not explicitly stated, the components are interpreted as including the ordinary error range.

[0042] When terms such as "on," "above," "below," and "next" are used to describe a positional relationship between two parts, one or more parts may be located between the two parts unless these terms are used together with the terms "immediately next to" or "directly."

[0043] When an element or layer is disposed “on” another element or layer, the other layer or element may be directly interposed on or between the other element.

[0044] Although the terms "first", "second" and the like are used to describe various components, these components are not limited to these terms. These terms are only used to distinguish one component from other components. Therefore, the first component to be mentioned below may be the second component in the technical concept of the present disclosure.

[0045] Throughout the specification, like reference numerals generally refer to like elements.

[0046] For convenience of description, the size and thickness of each component shown in the drawings are illustrated, and the present disclosure is not limited to the size and thickness of the components shown.

[0047] The features of various embodiments of the present disclosure may be partially or completely dependent on or combined with each other, and may be linked and operated in various technical ways, and the embodiments may be performed independently or in association with each other.

[0048] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0049] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure. Figure 2A is a partial cross-sectional view of a display device according to an exemplary embodiment of the present disclosure. Figure 2B is a perspective view of a spliced ​​display device according to an exemplary embodiment of the present disclosure. Figure 1 In the embodiment, for convenience of explanation, among various components of the display device 100, only the display panel PN, the gate driver GD, the data driver DD, and the timing controller TC are shown.

[0050] refer to Figure 1 The display device 100 includes a display panel PN including a plurality of sub-pixels SP, a gate driver GD and a data driver DD providing various signals to the display panel PN, and a timing controller TC controlling the gate driver GD and the data driver DD.

[0051] The gate driver GD supplies a plurality of scan signals to the plurality of scan lines SL according to a plurality of gate control signals supplied from the timing controller TC. Figure 1 2 and 3. It is shown that one gate driver GD is disposed to be spaced apart from one side of the display panel PN, but the number of the gate drivers GD and the placement thereof are not limited thereto.

[0052] The data driver DD converts the image data input from the timing controller TC into the data voltage Vdata using the reference gamma voltage according to a plurality of data control signals provided from the timing controller TC. The data driver DD may provide the converted data voltage Vdata to the plurality of data lines DL.

[0053] The timing controller TC aligns image data input from the outside to provide the image data to the data driver DD. The timing controller TC can generate a gate control signal and a data control signal using synchronization signals (such as a dot clock signal, a data enable signal, and a horizontal / vertical synchronization signal) input from the outside. In addition, the timing controller TC provides the generated gate control signal and data control signal to the gate driver GD and the data driver DD, respectively, to control the gate driver GD and the data driver DD.

[0054] The display panel PN is a configuration that displays an image to a user and includes a plurality of sub-pixels SP. In the display panel PN, a plurality of scan lines SL and a plurality of data lines DL cross each other, and a plurality of sub-pixels SP are connected to the scan lines SL and the data lines DL, respectively. Even though not shown in the drawings, each of the plurality of sub-pixels SP may be connected to a high potential power line VDD, a low potential power line VSS, a reference line RL, etc.

[0055] In the display panel PN, an active area AA and an unactive area NA surrounding the active area AA may be defined.

[0056] The active area AA is an area where an image is displayed in the display device 100. In the active area AA, a plurality of sub-pixels SP constituting a plurality of pixels PX and a circuit for driving the plurality of sub-pixels SP may be provided. The plurality of sub-pixels SP are the minimum units constituting the active area AA, and n sub-pixels SP form one pixel PX. In each of the plurality of sub-pixels SP, a light emitting diode LED and a thin film transistor for driving the light emitting diode LED may be provided. The plurality of light emitting elements LED may be defined in different ways according to the type of the display panel PN. For example, when the display panel PN is an inorganic light emitting display panel, the light emitting diode LED may be a light emitting diode (LED) or a micro light emitting diode (LED).

[0057] In the active area AA, a plurality of wiring lines for transmitting various signals to a plurality of sub-pixels SP are provided. For example, the plurality of wiring lines may include a plurality of data lines DL for providing a data voltage Vdata to each of the plurality of sub-pixels SP, a plurality of scan lines SL for providing a scan signal to each of the plurality of sub-pixels SP, and the like. The plurality of scan lines SL extend in one direction in the active area AA to be connected to the plurality of sub-pixels SP, and the plurality of data lines DL extend in a direction different from the one direction in the active area AA to be connected to the plurality of sub-pixels SP. In addition, in the active area AA, a low potential power line VSS, a high potential power line VDD, and the like may be further provided, but are not limited thereto.

[0058] The inactive area NA is an area where no image is displayed, so that the inactive area NA can be defined as an area extending from the active area AA. In the inactive area NA, a link line, a pad electrode, or a driving IC (such as a gate driver IC or a data driver IC) that transmits a signal to the sub-pixel SP of the active area AA can be provided.

[0059] Meanwhile, the non-active area NA may be located on the rear surface of the display panel PN, that is, on a surface where the sub-pixel SP is not disposed or the sub-pixel SP may be omitted, and is not limited to that shown in the drawing.

[0060] Meanwhile, drivers such as a gate driver GD, a data driver DD, and a timing controller TC may be connected to the display panel PN in various ways. For example, the gate driver GD may be installed in the inactive area NA in a gate-in-panel (GIP) manner, or may be installed between a plurality of sub-pixels SP in the active area AA in a gate-in-active-area (GIA) manner. For example, the data driver DD and the timing controller TC are formed in separate flexible films and printed circuit boards. The data driver DD and the timing controller TC are electrically connected to the display panel PN by bonding the flexible film and the printed circuit board to the pad electrodes formed in the inactive area NA of the display panel PN.

[0061] If the gate driver GD is installed in a GIP manner, and the data driver DD and the timing controller TC transmit signals to the display panel PN through the pad electrode of the inactive area NA, the area of ​​the inactive area NA for setting the gate driver GD and the pad electrode must have a predetermined level or more. Therefore, the frame can be increased.

[0062] On the contrary, when the gate driver GD is installed in the active area AA in a GIA manner and a side line SRL connecting the signal line on the front surface of the display panel PN to the pad electrode on the rear surface of the display panel PN is formed to bond the flexible film and the printed circuit board to the rear surface of the display panel PN, the inactive area NA on the front surface of the display panel PN can be minimized. That is, when the gate driver GD, the data driver DD, and the timing controller TC are connected to the display panel PN as described above, a zero frame having substantially no frame can be realized.

[0063] Specifically, refer to Figure 2A and Figure 2B In the inactive area NA of the display panel PN, a plurality of pad electrodes for transmitting various signals to a plurality of sub-pixels SP are provided. For example, in the inactive area NA on the front surface of the display panel PN, a first pad electrode PAD1 for transmitting signals to a plurality of sub-pixels SP is provided. In the inactive area NA on the rear surface of the display panel PN, a second pad electrode PAD2 electrically connected to a driving component such as a flexible film and a printed circuit board is provided. That is, on the front surface of the display panel PN on which an image is displayed, only the pad area of ​​the inactive area NA in which the first pad electrode PAD1 is provided may be formed at least.

[0064] In this case, even though not shown in the drawings, various signal lines (eg, scan lines SL or data lines DL) connected to the plurality of sub-pixels SP extend from the active area AA to the non-active area NA to be electrically connected to the first pad electrode PAD1.

[0065] In addition, the side line SRL is disposed along the side surface of the display panel PN. The side line SRL may electrically connect the first pad electrode PAD1 on the front surface of the display panel PN and the second pad electrode PAD2 on the rear surface of the display panel PN. Therefore, a signal from a driving component on the rear surface of the display panel PN may be transmitted to a plurality of sub-pixels SP through the second pad electrode PAD2, the side line SRL, and the first pad electrode PAD1. Therefore, a signal transmission path is formed from the front surface of the display panel PN to the side surface and the rear surface to minimize the area of ​​the inactive area NA on the front surface of the display panel PN.

[0066] refer to Figure 2B , a spliced ​​display device TD with a large screen size can be realized by connecting a plurality of display devices 100. Figure 2A As shown, when the spliced ​​display device TD is implemented using the display device 100 with a minimized frame, the seam area where the image between the display devices 100 is not displayed is minimized, so that the display quality can be improved.

[0067] For example, a plurality of sub-pixels SP form one pixel PX, and a distance D1 between an outermost pixel PX of one display device 100 and an outermost pixel PX of another display device 100 adjacent to the one display device may be implemented to be equal to a distance D1 between pixels PX in one display device 100. Therefore, a constant distance D1 between pixels PX between display devices 100 is configured to minimize a seam area.

[0068] However, Figure 2A and Figure 2B It is illustrative such that the display device 100 according to an exemplary embodiment of the present disclosure may be a general display device having a bezel, but is not limited thereto.

[0069] Figure 3 is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure. Figure 4A 1 is a driving timing diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure when a first light emitting diode emits light. Figure 4B is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure for explaining a flow of a driving current when a first light emitting diode emits light. Figure 5A 1 is a driving timing diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure when a second light emitting diode emits light. Figure 5B is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure for explaining a flow of a driving current when a second light emitting diode emits light.

[0070] refer to Figure 3 According to an exemplary embodiment of the present disclosure, a sub-pixel SP of a display device 100 includes a pixel circuit and a first light-emitting diode LED1 and a second light-emitting diode LED2 connected to the pixel circuit, the pixel circuit including a driving transistor DT, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a first control transistor LET1, a second control transistor LET2, a first capacitor C1, a second capacitor C2 and a third capacitor C3.

[0071] Each of the plurality of subpixels SP is electrically connected to first and second scan lines SL1 and SL2 , data lines DL, emission control lines EML, reference lines RL, first and second control lines LEL1 and LEL2 , high potential power lines VDD and VSS.

[0072] At the same time, the plurality of transistors of the plurality of sub-pixels SP may be formed of transistors of different types. For example, one of the plurality of transistors may be a transistor having an oxide semiconductor as an active layer. The oxide semiconductor material has a low off current, so that the oxide semiconductor material is suitable for a switching transistor that maintains a short on-time and a long off-time. As another example, another transistor of the plurality of transistors may be a transistor having a low temperature polysilicon (LTPS) as an active layer. The polysilicon material has a high mobility to have low power consumption and good reliability, so that it may be suitable for the driving transistor DT.

[0073] In addition, the plurality of transistors provided in each of the plurality of sub-pixels SP may be an N-type transistor or a P-type transistor. In the N-type transistor, the carrier is an electron, so that the electron flows from the source electrode to the drain electrode, and the current flows from the drain electrode to the source electrode. In the P-type transistor, the carrier is a hole, so that the hole flows from the source electrode to the drain electrode, and the current flows from the source electrode to the drain electrode. For example, one of the plurality of transistors may be an N-type transistor, and another of the plurality of transistors may be a P-type transistor.

[0074] Hereinafter, even if it is assumed that the plurality of transistors are P-type transistors, the plurality of transistors may be N-type transistors or include both P-type transistors and N-type transistors, but the present disclosure is not limited thereto.

[0075] The driving transistor DT is a transistor that controls a driving current based on a data voltage Vdata. A driving gate electrode DGE of the driving transistor DT is connected to a second node N2, a driving source electrode DSE is connected to a third node N3, and a driving drain electrode DDE is connected to a fourth node N4. The driving transistor DT may control a driving current applied to the light emitting diode LED according to a gate-source voltage Vgs.

[0076] The first transistor T1 is a transistor that transmits the data voltage Vdata to the subpixel SP. The first gate electrode GE1 of the first transistor T1 is connected to the first scan line SL1, the first source electrode SE1 is connected to the data line DL, and the first drain electrode DE1 is connected to the first node N1. The first transistor T1 is turned on by the first scan signal SCAN1 to provide the data voltage Vdata from the data line DL to the first node N1.

[0077] The second transistor T2 is a transistor that samples and compensates for the threshold voltage of the driving transistor DT. The second gate electrode GE2 of the second transistor T2 is connected to the first scan line SL1, and the second source electrode SE2 and the second drain electrode DE2 are respectively connected to the second node N2 and the fourth node N4. The second transistor T2 is turned on by the first scan signal SCAN1 to connect the driving gate electrode DGE and the driving drain electrode DDE of the driving transistor DT. Therefore, when the second transistor T2 is turned on, the driving transistor DT can be in a diode connection state in which the driving gate electrode DGE and the driving drain electrode DDE are short-circuited to operate as a diode.

[0078] The third transistor T3 is a transistor that initializes the first node N1 to a reference voltage. The third gate electrode GE3 of the third transistor T3 is connected to the emission control line EML, the third source electrode SE3 is connected to the reference line RL, and the third drain electrode DE3 is connected to the first node N1. The third transistor T3 is turned on by the emission control signal EM to transmit the reference voltage to the first node N1.

[0079] The fourth transistor T4 is a transistor that controls the flow of a driving current. A fourth gate electrode GE4 of the fourth transistor T4 is connected to an emission control line EML, a fourth source electrode SE4 is connected to a fourth node N4, and a fourth drain electrode DE4 is connected to a low potential power line VSS. The fourth transistor T4 is turned on by an emission control signal EM to connect the fourth node N4 and the low potential power line VSS and allow a driving current to flow from the high potential power line VDD to the low potential power line VSS.

[0080] The fifth transistor T5 is a transistor that initializes the fourth node N4 to a reference voltage. The fifth gate electrode GE5 of the fifth transistor T5 is connected to the second scan line SL2, the fifth source electrode SE5 is connected to the reference line RL, and the fifth drain electrode DE5 is connected to the fourth node N4. The fifth transistor T5 is turned on by the second scan signal SCAN2 to transmit the reference voltage to the fourth node N4. Therefore, the voltage of the driving drain electrode DDE of the driving transistor DT can be initialized to the reference voltage by the fifth transistor T5.

[0081] The first control transistor LET1 is a transistor that controls whether the first light emitting diode LED1 emits light. The first control gate electrode EGE1 of the first control transistor LET1 is connected to the first control line LEL1, and the first control source electrode ESE1 is connected to the first anode AD1 of the first light emitting diode LED1 and the high potential power line VDD. The first control drain electrode EDE1 is connected to the first cathode CD1 of the first light emitting diode LED1 and the fifth node N5. The first control transistor LET1 and the first light emitting diode LED1 may be connected in parallel.

[0082] The first control transistor LET1 is turned on by the first control signal LE1 of the first control line LEL1 to allow the driving current to flow to the first control transistor LET1 instead of the first light emitting diode LED1. That is, when the first control transistor LET1 is turned on, the driving current does not flow to the first light emitting diode LED1, but detours to the turned-on first control transistor LET1. When the first control transistor LET1 is turned on, the driving current can detour from the first control source electrode ESE1 of the first control transistor LET1 to the first control drain electrode EDE1. On the contrary, when the first control transistor LET1 is turned off, the driving current can flow from the first anode AD1 of the first light emitting diode LED1 to the first cathode CD1. Therefore, the first light emitting diode LED1 can emit light only when the first control transistor LET1 is turned off.

[0083] The second control transistor LET2 is a transistor that controls whether the second light emitting diode LED2 emits light. The second control gate electrode EGE2 of the second control transistor LET2 is connected to the second control line LEL2, and the second control source electrode ESE2 is connected to the second anode AD2 of the second light emitting diode LED2 and the fifth node N5. The second control drain electrode EDE2 is connected to the second cathode CD2 of the second light emitting diode LED2 and the third node N3. The second control transistor LET2 and the second light emitting diode LED2 may be connected in parallel.

[0084] The second control transistor LET2 is turned on by the second control signal LE2 of the second control line LEL2 to allow the driving current to flow to the second control transistor LET2 instead of the second light emitting diode LED2. When the second control transistor LET2 is turned on, the driving current can be detoured from the second control source electrode ESE2 of the second control transistor LET2 to the second control drain electrode EDE2. When the second control transistor LET2 is turned off, the driving current can flow from the second anode AD2 of the second light emitting diode LED2 to the second cathode CD2. Therefore, the second light emitting diode LED2 can emit light only when the second control transistor LET2 is turned off.

[0085] The first capacitor C1 is connected between the first node N1 and the second node N2. The first capacitor C1 includes a plurality of first capacitor electrodes. Some of the plurality of first capacitor electrodes are connected to the first node N1, and the other first capacitor electrodes are connected to the second node N2. In addition, when the first light emitting diode LED1 or the second light emitting diode LED2 emits light, the first capacitor C1 is charged with the data voltage Vdata reflected by the threshold voltage of the driving transistor DT to fix the voltage applied to the driving gate electrode DGE of the driving transistor DT. In this way, a constant driving current can be provided to the first light emitting diode LED1 or the second light emitting diode LED2 during one frame.

[0086] The second capacitor C2 is connected between the second node N2 and the third node N3. The second capacitor C2 includes a plurality of second capacitor electrodes. Some of the plurality of second capacitor electrodes are connected to the second node N2, and the other second capacitor electrodes are connected to the third node N3. The second capacitor C2 may be connected between the driving gate electrode DGE and the driving source electrode DSE of the driving transistor DT.

[0087] At the same time, when the voltage in the first node N1 fluctuates, the voltage of the second node N2 may also fluctuate due to the coupling characteristics of the first capacitor C1. At this time, the second capacitor C2 connected in series with the first capacitor C1 is in a state of coupling to the first capacitor C1, so that the transmission rate of the voltage of the first node N1 to the voltage of the second node N2 can be varied according to the capacitance ratio of the first capacitor C1 to the second capacitor C2. Therefore, when the light emitting diode LED is configured by a micro-LED having an IV curve with a large slope, the second capacitor C2 is connected to the first capacitor C1 to reduce the transmission rate of the data voltage Vdata transmitted from the first node N1 to the second node N2. In addition, a finer grayscale can be expressed.

[0088] The third capacitor C3 is a capacitor formed between the high potential power line VDD and the third node N3, and may be a parasitic capacitor. The third capacitor C3 may be a capacitor formed between existing configurations without additionally forming a separate electrode. For example, at least a portion of the configuration connected to the high potential power line VDD and at least a portion of the configuration connected to the third node N3 overlap each other to form the third capacitor C3. The third capacitor C3 increases the intrinsic capacitance in the light emitting diode LED to allow the light emitting diode LED to emit light at a higher brightness.

[0089] The first light emitting diode LED1 includes a first anode AD1 and a first cathode CD1. The first anode AD1 of the first light emitting diode LED1 is connected to the high potential power supply line VDD, and the first cathode CD1 is connected to the fifth node N5. In the off state of the first control transistor LET1, the first light emitting diode LED1 is provided with a driving current set by the turned-on driving transistor DT to emit light.

[0090] The second light emitting diode LED2 is connected in series with the first light emitting diode LED1, and includes a second anode AD2 and a second cathode CD2. The second anode AD2 of the second light emitting diode LED2 is connected to the fifth node N5, and the second cathode CD2 is connected to the third node N3. In the off state of the second control transistor LET2, the second light emitting diode LED2 is provided with a driving current set by the turned-on driving transistor DT to emit light.

[0091] The first light emitting diode LED1 and the second light emitting diode LED2 may be driven in turn. The first light emitting diode LED1 and the second light emitting diode LED2 may emit light in different frames or different horizontal periods. For example, the first light emitting diode LED1 may emit light in the nth frame, and the second light emitting diode LED2 may emit light in the mth frame. For example, the first light emitting diode LED1 may emit light in the nth horizontal period, and the second light emitting diode LED2 may emit light in the mth horizontal period. In this case, the first control transistor LET1 and the second control transistor LET2 may also be turned on in turn. That is, the first control transistor LET1 and the second control transistor LET2 are turned on in different frames, and the first light emitting diode LED1 and the second light emitting diode LED2 are controlled to emit light in different periods.

[0092] Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, the first light emitting diode LED1 and the second light emitting diode LED2 connected in series with the plurality of sub-pixels SP, the first control transistor LET1 connected in parallel with the first light emitting diode LED1, and the second control transistor LET2 connected in parallel with the second light emitting diode LED2 are formed. Therefore, even if a defect occurs in the sub-pixel SP, it can be seen that the sub-pixel SP is driven normally. For example, an open circuit defect or a short circuit defect occurs, the driving current bypasses the first control transistor LET1 to be provided to the second light emitting diode LED2, and the second light emitting diode LED2 can be driven normally. The open circuit defect is a defect in which a part of the first anode AD1 and the first cathode CD1 of the first light emitting diode LED1 are not connected to the circuit. The short circuit defect is a defect in which the first anode AD1 and the first cathode CD1 of the first light emitting diode LED1 are electrically connected to each other. Similarly, even if an open circuit defect or a short circuit defect occurs in the second light emitting diode LED2, the second control transistor LET2 can form a current path between the driving transistor DT and the first light emitting diode LED1. That is, when the second light emitting diode LED2 is defective, the driving current bypasses the second control transistor LET2, and the first light emitting diode LED1 can be driven normally. Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, even if any one of the plurality of light emitting diodes LED provided in each of the plurality of sub-pixels SP is defective, the remaining light emitting diodes LED can be used to drive the sub-pixel SP. Therefore, dark spot defects can be minimized, and the reliability of the display device 100 can be improved.

[0093] In addition, as described above, the first light emitting diode LED1 and the second light emitting diode LED2 may emit light in turn in units of frames or in units of horizontal periods. If the first light emitting diode LED1 is defective so that the first light emitting diode LED1 does not emit light, the second light emitting diode LED2 emits light in another frame or another horizontal period so that the sub-pixel SP does not look like a dark spot. Specifically, when the display device 100 is driven at a high frequency, the length of one frame or the length of the horizontal period is very short, making it difficult for the user to recognize the non-emission defect of the first light emitting diode LED1 or the second light emitting diode LED2. Therefore, the first light emitting diode LED1 and the second light emitting diode LED2 emit light in turn. Even if one light emitting diode LED is defective so that it does not emit light, the remaining light emitting diodes LED emit light to display an image normally.

[0094] Hereinafter, a driving process of the sub-pixel SP will be described in detail by assuming that the first light emitting diode LED1 and the second light emitting diode LED2 emit light in turns in units of frames.

[0095] Reference together Figure 4A and Figure 4B , at time A, the low-level second scan signal SCAN2 is output to the second scan line SL2. The fifth transistor T5 is turned on by the low-level second scan signal SCAN2, and the reference voltage is applied to the driving drain electrode DDE of the driving transistor DT as the fourth node N4. Therefore, the voltage of the driving drain electrode DDE of the driving transistor DT may be initialized to the reference voltage at time A.

[0096] Next, in a period between time B and time C, a low-level first scan signal SCAN1 is output to the first scan line SL1. The first transistor T1 is turned on by the low-level first scan signal SCAN1 to transmit the data voltage Vdata to the first node N1. In addition, the second transistor T2 is turned on by the low-level first scan signal SCAN1 to connect the driving gate electrode DGE and the driving drain electrode DDE of the driving transistor DT.

[0097] In addition, during the period between time B and time C, the low-level first control signal LE1 and the second control signal LE2 are output to both the first control line LEL1 and the second control line LEL2. At time B, the high potential power line VDD and the driving source electrode DSE of the driving transistor DT may be electrically connected. At time B, the high potential power line VDD is connected to the driving source electrode DSE of the driving transistor DT in a diode connection state through the second transistor T2, so that current flows through the driving transistor DT, and the threshold voltage of the driving transistor DT may be sampled. Therefore, the threshold voltage of the driving transistor DT is sampled to be reflected to the second node N2, and the data voltage Vdata to which the threshold voltage of the driving transistor DT is reflected may be charged to the first capacitor C1.

[0098] Next, the emission control signal EM of a low level is output to the emission control line EML at time D. The third transistor T3 is turned on by the emission control signal EM of a low level, and the reference voltage may be applied to the first node N1.

[0099] The fourth transistor T4 is turned on by the low-level emission control signal EM, the driving transistor DT and the low-potential power line VSS may be electrically connected, and the driving current may flow to the first light emitting diode LED1 or the second light emitting diode LED2 .

[0100] refer to Figure 4A and Figure 4B, when it is the turn of the first light emitting diode LED1 to emit light between the first light emitting diode LED1 and the second light emitting diode LED2, a high-level first control signal LE1 is output to the first control line LEL1, and a low-level second control signal LE2 is output to the second control line LEL2. That is, the first control signal LE1 that turns off the first control transistor LET1 is output to the first control line LEL1, and the second control signal LE2 that turns on the second control transistor LET2 is output to the second control line LEL2.

[0101] When the first control transistor LET1 is turned off, the driving current may flow to the first light emitting diode LED1 connected in parallel with the first control transistor LET1. In addition, when the second control transistor LET2 is turned on, the driving current may flow to the second control transistor LET2. Therefore, the first control transistor LET1 is turned off between the high potential power supply line VDD and the fifth node N5 so that the driving current flows to the first light emitting diode LED1 connected in parallel with the first control transistor LET1. The second control transistor LET2 is turned on between the fifth node N5 and the third node N3 so that the driving current flows to the second control transistor LET2. Therefore, when the first control transistor LET1 is turned off and the second control transistor LET2 is turned on, the first light emitting diode LED1 emits light, and the second light emitting diode LED2 does not emit light.

[0102] Next, refer to Figure 5A and Figure 5B , when it is the turn of the second light emitting diode LED2 to emit light between the first light emitting diode LED1 and the second light emitting diode LED2, the low-level first control signal LE1 is output to the first control line LEL1, and the high-level second control signal LE2 is output to the second control line LEL2. That is, the first control signal LE1 that turns on the first control transistor LET1 is output to the first control line LEL1, and the second control signal LE2 that turns off the second control transistor LET2 is output to the second control line LEL2.

[0103] When the first control transistor LET1 is turned on, the drive current detours to the first control transistor LET1 to flow. In addition, when the second control transistor LET2 is turned off, the drive current can flow to the second light emitting diode LED2. Therefore, the first control transistor LET1 is turned on between the high potential power supply line VDD and the fifth node N5 so that the drive current flows to the first control transistor LET1. The second control transistor LET2 is turned off between the fifth node N5 and the third node N3 so that the drive current flows to the second light emitting diode LED2 connected in parallel with the second control transistor LET2. Therefore, when the first control transistor LET1 is turned on and the second control transistor LET2 is turned off, the first light emitting diode LED1 does not emit light, and the second light emitting diode LED2 can emit light.

[0104] Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, the first control transistor LET1 and the second control transistor LET2 respectively connected in parallel with the first light emitting diode LED1 and the second light emitting diode LED2 are formed to easily control the first light emitting diode LED1 and the second light emitting diode LED2 to emit light. The first light emitting diode LED1 and the first control transistor LET1 are connected in parallel, and when the first control transistor LET1 is turned off, the driving current flows to the first light emitting diode LED1 so that the first light emitting diode LED1 emits light. On the contrary, when the first control transistor LET1 is turned on, the driving current detours to the first control transistor LET1 so that the first light emitting diode LED1 does not emit light. Only when the second control transistor LET2 connected in parallel with the second light emitting diode LED2 is turned off, the second light emitting diode LED2 emits light. Therefore, the first light emitting diode LED1 and the second light emitting diode LED2 are selectively emitted using the first control transistor LET1 and the second control transistor LET2 respectively connected in parallel with the first light emitting diode LED1 and the second light emitting diode LED2. Furthermore, in order to independently control the first light emitting diode LED1 and the second light emitting diode LED2 , at least instead of a complicated circuit, only the first control transistor LET1 and the second control transistor LET2 are added, so that the configuration of the sub-pixel SP can be simplified.

[0105] Furthermore, in the display device 100 according to the exemplary embodiment of the present disclosure, the first control transistor LET1 and the second control transistor LET2 are formed and connected in parallel with the first light emitting diode LED1 and the second light emitting diode LED2, respectively. Therefore, even if one light emitting diode LED is defective, the remaining light emitting diodes LED can be driven normally. For example, when an open circuit defect occurs in the first light emitting diode LED1, it may be difficult to make the driving current flow to the second light emitting diode LED2 between the first light emitting diode LED1 and the second light emitting diode LED2 connected in series. However, in the display device 100 according to the exemplary embodiment of the present disclosure, the first control transistor LET1 connected in parallel with the first light emitting diode LED1 is turned on to form a path through which the driving current passes in a roundabout way, and the driving current is normally supplied to the second light emitting diode LED2. Therefore, even if some of the light emitting diodes LED are defective, the driving current can be normally supplied to the remaining light emitting diodes LED using the control transistors connected in parallel with the light emitting diodes LED.

[0106] In addition, in the display device 100 according to the exemplary embodiment of the present disclosure, a plurality of light emitting diodes LED are arranged in one sub-pixel SP, so that an image with high resolution can be easily displayed. For example, only one light emitting diode LED is arranged in each of the plurality of sub-pixels SP, and an image with high resolution can be displayed by increasing the number of the plurality of sub-pixels SP. However, in this case, the area allocated to each of the plurality of sub-pixels SP is reduced, making it difficult to design the sub-pixels SP. On the contrary, in the display device 100 according to the exemplary embodiment of the present disclosure, a plurality of light emitting diodes LED are arranged in each of the plurality of sub-pixels SP, so that an image with high resolution can be displayed without increasing the number of the plurality of sub-pixels SP. That is, the number of light emitting diodes LED is increased, so that the same effect as increasing the number of sub-pixels SP can be obtained. At this time, the number of sub-pixels SP is the same, and only the number of light emitting diodes LED is increased, thereby ensuring the area for designing each sub-pixel SP, and the sub-pixel SP can be designed more easily.

[0107] At the same time, reference Figure 4A , when the first light emitting diode LED1 emits light, the first control signal LE1 applied to the first control line LEL1 may have the same waveform as the first scan signal SCAN1. Figure 5A, when the second light emitting diode LED2 emits light, the second control signal LE2 applied to the second control line LEL2 may have the same waveform as the first scan signal SCAN1. In the display device 100 according to an exemplary embodiment of the present disclosure, the control signal generating circuit LEC is connected to each of the plurality of first stages ST1 generating the first scan signal SCAN1 to output any one of the first control signal LE1 and the second control signal LE2 to have the same waveform as the first scan signal SCAN1. This will be referred to below. Figures 8 to 10 Describe in more detail.

[0108] In the following, reference will be made to Figure 6 and Figure 7 A structure of a sub-pixel SP of the display device 100 according to an exemplary embodiment of the present disclosure is described.

[0109] Figure 6 is a plan view of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure. Figure 7 is along Figure 6 For ease of description, the cross-sectional view taken along the lines VIIa-VIIa' and VIIb-VIIb' is shown. Figure 6 In FIG. 1 , the plurality of reflective electrodes RE, the first light emitting diode LED1, the second light emitting diode LED2, the plurality of connection electrodes CE, and the bank BB are not shown.

[0110] refer to Figure 6 and Figure 7 A display device 100 according to an exemplary embodiment of the present disclosure includes a substrate 110, a buffer layer 111, a gate insulating layer 112, a first interlayer insulating layer 113a, a second interlayer insulating layer 113b, a first passivation layer 114a, a second passivation layer 114b, a first planarizing layer 115a, a second planarizing layer 115b, a third planarizing layer 115c, an adhesive layer 116, a bank BB, a protective layer 117, a light shielding layer LS, a plurality of transistors, a plurality of capacitors, a plurality of wirings, a plurality of reflective electrodes RE, a plurality of connecting electrodes CE, and a plurality of light emitting diodes LED.

[0111] First, the substrate 110 is a component for supporting various components included in the display device 100, and the substrate 110 may be formed of an insulating material. For example, the substrate 110 may be formed of glass or resin. In addition, the substrate 110 may be configured to include a polymer or plastic, or may be formed of a material having flexibility.

[0112] The light shielding layer LS is disposed in each of the plurality of sub-pixels SP on the substrate 110. The light shielding layer LS blocks light incident on the driving active layer DACT of the driving transistor DT under the substrate 110, which will be described below. The light incident on the driving active layer DACT of the driving transistor DT is blocked by the light shielding layer LS to minimize leakage current. The light shielding layer LS may be configured of an opaque conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but is not limited thereto.

[0113] The buffer layer 111 is disposed on the substrate 110 and the light shielding layer LS. The buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. The buffer layer 111 can be configured by a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. However, depending on the type of the substrate 110 or the type of the transistor, the buffer layer 111 can be omitted, but is not limited thereto.

[0114] The driving transistor DT is disposed on the buffer layer 111. The driving transistor DT includes a driving active layer DACT, a driving gate electrode DGE, a driving source electrode DSE, and a driving drain electrode DDE.

[0115] The driving active layer DACT is disposed on the buffer layer 111. The driving active layer DACT may be formed of a semiconductor material, such as an oxide semiconductor, amorphous silicon, or polysilicon, but is not limited thereto.

[0116] The gate insulating layer 112 is disposed on the driving active layer DACT. The gate insulating layer 112 is an insulating layer that electrically insulates the driving active layer DACT from the driving gate electrode DGE and may be composed of a single or double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0117] The driving gate electrode DEG is disposed on the gate insulating layer 112. The driving gate electrode DEG may be configured of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but is not limited thereto.

[0118] The first interlayer insulating layer 113a and the second interlayer insulating layer 113b are disposed on the driving gate electrode DEG. In the first interlayer insulating layer 113a and the second interlayer insulating layer 113b, contact holes are formed, through which the driving source electrode DSE and the driving drain electrode DDE are connected to the driving active layer DACT. The first interlayer insulating layer 113a and the second interlayer insulating layer 113b are insulating layers that protect components below the first interlayer insulating layer 113a and the second interlayer insulating layer 113b. In addition, the first interlayer insulating layer 113a and the second interlayer insulating layer 113b may be composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but are not limited thereto.

[0119] A driving source electrode DSE and a driving drain electrode DDE electrically connected to the driving active layer DACT are disposed on the second interlayer insulating layer 113b. The driving source electrode DSE and the driving drain electrode DDE may be configured of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but are not limited thereto.

[0120] The first transistor T1 is disposed on the buffer layer 111. The first transistor T1 includes a first active layer ACT1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1.

[0121] The first active layer ACT1 is disposed on the buffer layer 111. The first active layer ACT1 may be formed of a semiconductor material, such as an oxide semiconductor, amorphous silicon, or polysilicon, but is not limited thereto.

[0122] The gate insulating layer 112 is disposed on the first active layer ACT1, and the first gate electrode GE1 is disposed on the gate insulating layer 112. The first gate electrode GE1 is integrally formed with the first scan line SL1 to be electrically connected to the first scan line SL1. The first gate electrode GE1 may be configured of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0123] The first interlayer insulating layer 113a and the second interlayer insulating layer 113b are disposed on the first gate electrode GE1. In addition, the first source electrode SE1 and the first drain electrode DE1 electrically connected to the first active layer ACT1 are disposed on the second interlayer insulating layer 113b. The first source electrode SE1 is formed integrally with the data line DL to be electrically connected to the data line DL. The first drain electrode DE1 may be electrically connected to the 1-2 capacitor electrode C1b of the first capacitor C1 through a contact hole of the second interlayer insulating layer 113b, and the first capacitor C1 will be described below. The first source electrode SE1 and the first drain electrode DE1 may be configured of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but is not limited thereto.

[0124] The second transistor T2 is disposed on the buffer layer 111. The second transistor T2 includes a second active layer ACT2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2.

[0125] The second active layer ACT2 is disposed on the buffer layer 111. The second active layer ACT2 may be formed of a semiconductor material, such as an oxide semiconductor, amorphous silicon, or polysilicon, but is not limited thereto.

[0126] The gate insulating layer 112 is disposed on the second active layer ACT2, and the second gate electrode GE2 is disposed on the gate insulating layer 112. The second gate electrode GE2 is integrally formed with the first scan line SL1 to be electrically connected to the first scan line SL1. The second gate electrode GE2 may be configured of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0127] The first interlayer insulating layer 113a and the second interlayer insulating layer 113b are disposed on the second gate electrode GE2. In addition, the second source electrode SE2 and the second drain electrode DE2 electrically connected to the second active layer ACT2 are disposed on the second interlayer insulating layer 113b. The second source electrode SE2 is electrically connected to the driving gate electrode DGE of the 1-1 capacitor electrode C1a as the first capacitor C1. The second drain electrode DE2 is electrically connected to the fourth source electrode SE4 of the fourth transistor T4, the fifth drain electrode DE5 of the fifth transistor T5, and the driving drain electrode DDE of the driving transistor DT. The second source electrode SE2 and the second drain electrode DE2 may be configured of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but is not limited thereto.

[0128] The third transistor T3 is disposed on the buffer layer 111. The third transistor T3 includes a third active layer ACT3, a third gate electrode GE3, a third source electrode SE3, and a third drain electrode DE3.

[0129] The third active layer ACT3 is disposed on the buffer layer 111. The third active layer ACT3 may be formed of a semiconductor material, such as an oxide semiconductor, amorphous silicon, or polysilicon, but is not limited thereto.

[0130] The gate insulating layer 112 is disposed on the third active layer ACT3, and the third gate electrode GE3 is disposed on the gate insulating layer 112. The third gate electrode GE3 is formed integrally with the emission control line EML to be electrically connected to the emission control line EML. The third gate electrode GE3 may be configured of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but is not limited thereto.

[0131] The first interlayer insulating layer 113a and the second interlayer insulating layer 113b are disposed on the third gate electrode GE3. In addition, the third source electrode SE3 and the third drain electrode DE3 electrically connected to the third active layer ACT3 are disposed on the second interlayer insulating layer 113b. The third source electrode SE3 is electrically connected to the fifth source electrode SE5 and the reference line RL. In addition, the third drain electrode DE3 is electrically connected to the 1-2 capacitor electrode C1b of the first capacitor C1 and the first drain electrode DE1 of the first transistor T1. The third source electrode SE3 and the third drain electrode DE3 may be configured of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but are not limited thereto.

[0132] The fourth transistor T4 is disposed on the buffer layer 111. The fourth charging transistor T4 includes a fourth active layer ACT4, a fourth gate electrode GE4, a fourth source electrode SE4, and a fourth drain electrode DE4.

[0133] The fourth active layer ACT4 is disposed on the buffer layer 111. The fourth active layer ACT4 may be formed of a semiconductor material, such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon, but is not limited thereto.

[0134] The gate insulating layer 112 is disposed on the fourth active layer ACT4, and the fourth gate electrode GE4 is disposed on the gate insulating layer 112. The fourth gate electrode GE4 is integrally formed with the emission control line EML to be electrically connected to the emission control line EML. The fourth gate electrode GE4 may be configured of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but is not limited thereto.

[0135] The first interlayer insulating layer 113a and the second interlayer insulating layer 113b are disposed on the fourth gate electrode GE4. In addition, the fourth source electrode SE4 and the fourth drain electrode DE4 electrically connected to the fourth active layer ACT4 are disposed on the second interlayer insulating layer 113b. The fourth source electrode SE4 is electrically connected to the driving drain electrode DDE of the driving transistor DT, the fifth drain electrode DE5 of the fifth transistor T5, and the second drain electrode DE2 of the second transistor T2. In addition, the fourth drain electrode DE4 is electrically connected to the low potential power line VSS. At this time, the low potential power line VSS and the fourth drain electrode DE4 are integrally formed on the same layer with the same material. The fourth source electrode SE4 and the fourth drain electrode DE4 can be configured of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but are not limited thereto.

[0136] The fifth transistor T5 is disposed on the buffer layer 111. The fifth transistor T5 includes a fifth active layer ACT5, a fifth gate electrode GE5, a fifth source electrode SE5, and a fifth drain electrode DE5.

[0137] The fifth active layer ACT5 is disposed on the buffer layer 111. The fifth active layer ACT5 may be formed of a semiconductor material, such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon, but is not limited thereto.

[0138] The gate insulating layer 112 is disposed on the fifth active layer ACT5, and the fifth gate electrode GE5 is disposed on the gate insulating layer 112. The fifth gate electrode GE5 may be electrically connected to the second scan line SL2. The fifth gate electrode GE5 and the second scan line SL2 may be integrally formed on the same layer with the same material. The fifth gate electrode GE5 may be configured of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but is not limited thereto.

[0139] The first interlayer insulating layer 113a and the second interlayer insulating layer 113b are disposed on the fifth gate electrode GE5. In addition, the fifth source electrode SE5 and the fifth drain electrode DE5 electrically connected to the fifth active layer ACT5 are disposed on the second interlayer insulating layer 113b. The fifth source electrode SE5 is electrically connected to the reference line RL and the third source electrode SE3. In addition, the fifth drain electrode DE5 is connected to the driving drain electrode DDE, the fourth source electrode SE4, and the second drain electrode DE2. The fifth source electrode SE5 and the fifth drain electrode DE5 may be configured of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but are not limited thereto.

[0140] The first control transistor LET1 is disposed on the buffer layer 111. The first control transistor LET1 includes a first control active layer EACT1, a first control gate electrode EGE1, a first control source electrode ESE1, and a first control drain electrode EDE1.

[0141] The first control active layer EACT1 is disposed on the buffer layer 111. The first control active layer EACT1 may be formed of a semiconductor material, such as an oxide semiconductor, amorphous silicon, or polysilicon, but is not limited thereto.

[0142] A gate insulating layer 112 is disposed on the first control active layer EACT1, and a first control gate electrode EGE1 is disposed on the gate insulating layer 112. The first control gate electrode EGE1 is integrally formed with the first control line LEL1 to be electrically connected to the first control line LEL1. The first control gate electrode EGE1 may be configured of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0143] The first interlayer insulating layer 113a and the second interlayer insulating layer 113b are disposed on the first control gate electrode EGE1. In addition, the first control source electrode ESE1 and the first control drain electrode EDE1 electrically connected to the first control active layer EACT1 are disposed on the second interlayer insulating layer 113b. The first control source electrode ESE1 is electrically connected to the high potential power line VDD, and the first control drain electrode EDE1 is electrically connected to the second control source electrode ESE2 of the second control transistor LET2. In addition, the first control source electrode ESE1 and the first drain electrode DE1 may be connected in parallel with the first light emitting diode LED1 through the first reflective electrode RE1 and the second reflective electrode RE2, which will be described below. The first control source electrode ESE1 and the first control drain electrode EDE1 may be configured of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but are not limited thereto.

[0144] The second control transistor LET2 is disposed on the buffer layer 111. The second control transistor LET2 includes a second control active layer EACT2, a second control gate electrode EGE2, a second control source electrode ESE2, and a second control drain electrode EDE2.

[0145] The second control active layer EACT2 is disposed on the buffer layer 111. The second control active layer EACT2 may be formed of a semiconductor material, such as an oxide semiconductor, amorphous silicon, or polysilicon, but is not limited thereto.

[0146] The gate insulating layer 112 is disposed on the second control active layer EACT2, and the second control gate electrode EGE2 is disposed on the gate insulating layer 112. The second control gate electrode EGE2 is integrally formed with the second control line LEL2 to be electrically connected to the second control line LEL2. The second control gate electrode EGE2 may be configured of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0147] The first interlayer insulating layer 113a and the second interlayer insulating layer 113b are disposed on the second control gate electrode EGE2. In addition, the second control source electrode ESE2 and the second control drain electrode EDE2 electrically connected to the second control active layer EACT2 are disposed on the second interlayer insulating layer 113b. The second control source electrode ESE2 is formed integrally with the first control drain electrode EDE1 to be electrically connected to the first control drain electrode EDE1. The second control source electrode ESE2 may be electrically connected to the second anode AD2 of the second light emitting diode LED2 through the second reflective electrode RE2, which will be described below. The second control drain electrode EDE2 extends from the second control active layer EACT2 to the driving active layer DACT to be connected to the driving active layer DACT. In addition, the second control drain electrode EDE2 may be electrically connected to the driving source electrode DSE through the driving active layer DACT. In addition, the second control drain electrode EDE2 may be electrically connected to the second cathode CD2 of the second light emitting diode LED2 through the driving source electrode DSE and the third reflective electrode RE3. Therefore, the second control source electrode ESE2 and the second control drain electrode EDE2 are connected in parallel with the second light emitting diode LED2 through the second reflective electrode RE2 and the third reflective electrode RE3. The second control source electrode ESE2 and the second control drain electrode EDE2 can be configured of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but is not limited thereto.

[0148] Next, a first capacitor C1 is disposed on the gate insulating layer 112. The first capacitor C1 includes a 1-1 capacitor electrode C1a and a 1-2 capacitor electrode C1b. The 1-1 capacitor electrode C1a and the 1-2 capacitor electrode C1b may be configured of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0149] The 1-1st capacitor electrode C1a is disposed on the gate insulating layer 112. The 1-1st capacitor electrode C1a is formed integrally with the driving gate electrode DGE. Therefore, the 1-1st capacitor electrode C1a may be electrically connected to the driving gate electrode DGE and the second source electrode SE2 connected to the driving gate electrode DGE.

[0150] The 1-2 capacitor electrode C1b is disposed on the first interlayer insulating layer 113a. The 1-2 capacitor electrode C1b is disposed to overlap the 1-1 capacitor electrode C1a so that the first interlayer insulating layer 113a is located between the 1-2 capacitor electrode C1b and the 1-1 capacitor electrode C1a. In addition, the 1-2 capacitor electrode C1b may be electrically connected to the first drain electrode DE1 and the third drain electrode DE3.

[0151] The second capacitor C2 is disposed on the substrate 110. The second capacitor C2 includes a 2-1st capacitor electrode C2a, a 2-2nd capacitor electrode C2b, and a 2-3rd capacitor electrode C2c. The 2-1st capacitor electrode C2a, the 2-2nd capacitor electrode C2b, and the 2-3rd capacitor electrode C2c may be configured of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0152] The 2-1st capacitor electrode C2a is disposed on the substrate 110. The 2-1st capacitor electrode C2a extends from the light shielding layer LS and is formed integrally with the light shielding layer LS. At this time, the 2-1st capacitor electrode C2a may be electrically connected to the driving source electrode DSE through the auxiliary electrode AE. The auxiliary electrode AE ​​is disposed on the gate insulating layer 112 to electrically connect the driving source electrode DSE and the 2-1st capacitor electrode C2a to each other.

[0153] The 2-2nd capacitor electrode C2b is disposed on the buffer layer 111 and the gate insulating layer 112. The 2-2nd capacitor electrode C2b may be formed integrally with the driving gate electrode DGE and the 1-1st capacitor electrode C1a. Therefore, the 2-1st capacitor electrode C2a may be electrically connected to the driving gate electrode DGE, the 1-1st capacitor electrode C1a, and the second source electrode SE2.

[0154] The 2-3rd capacitor electrode C2c is disposed on the first interlayer insulating layer 113a. The 2-3rd capacitor electrode C2c may be configured by a first electrode layer C2c1 and a second electrode layer C2c2. The first electrode layer C2c1 of the 2-3rd capacitor electrode C2c is located on the same layer with the 1-2nd capacitor electrode C1b with the same material, and is spaced apart from the 1-2nd capacitor electrode C1b to form an island pattern. The first electrode layer C2c1 may be disposed to overlap the 2-1st capacitor electrode C2a and the 2-2nd capacitor electrode C2b so that the first interlayer insulating layer 113a is located between the first electrode layer C2c1 and the 2-1st capacitor electrode C2a and the 2-2nd capacitor electrode C2b.

[0155] The second electrode layer C2c2 of the 2-3 capacitor electrode C2c is disposed on the second interlayer insulating layer 113b. The second electrode layer C2c2 may be formed integrally with the driving source electrode DSE. The second electrode layer C2c2 may be electrically connected to the first electrode layer C2c1 through a contact hole of the second interlayer insulating layer 113b.

[0156] Next, a plurality of wirings are disposed on the substrate 110. The plurality of wirings include first and second scan lines SL1 and SL2, emission control lines EML, first and second control lines LEL1 and LEL2, reference lines RL, data lines DL, high potential power lines VDD, and low potential power lines VSS.

[0157] First, the first scan line SL1, the second scan line SL2, the emission control line EML, the first control line LEL1 and the second control line LEL2 are disposed on the gate insulating layer 112. The first scan line SL1, the second scan line SL2, the emission control line EML, the first control line LEL1 and the second control line LEL2 extend in a row direction and may be electrically connected to other configurations of the sub-pixel SP. For example, the first scan line SL1 is connected to the first transistor T1 and the second transistor T2, and the second scan line SL2 may be connected to the fifth transistor T5. The emission control line EML is connected to the third transistor T3 and the fourth transistor T4, and the first control line LEL1 and the second control line LEL2 may be connected to the first control transistor LET1 and the second control transistor LET2. The first scan line SL1, the second scan line SL2, the emission control line EML, the first control line LEL1 and the second control line LEL2 are configured of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti) and chromium (Cr) or alloys thereof, but are not limited thereto.

[0158] Next, a reference line RL and a high potential power line VDD are disposed on the first interlayer insulating layer 113a. The reference line RL and the high potential power line VDD extend in the row direction and may be electrically connected to other configurations of the sub-pixel SP. For example, the reference line RL is connected to the fifth transistor T5, and the high potential power line VDD may be connected to the first control transistor LET1. The reference line RL and the high potential power line VDD may be configured of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but are not limited thereto.

[0159] The data line DL and the low potential power line VSS are arranged on the second interlayer insulating layer 113b. The data line DL and the low potential power line VSS extend in the column direction and may cross other wirings extending in the row direction. In addition, the data line DL and the low potential power line VSS may be electrically connected to other configurations of the sub-pixel SP. For example, the data line DL is connected to the first transistor T1, and the low potential power line VSS may be connected to the fourth transistor T4. The data line DL and the low potential power line VSS may be configured by a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but are not limited thereto.

[0160] Next, a first passivation layer 114a is disposed on the driving transistor DT, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the first control transistor LET1, the second control transistor LET2, the first capacitor C1, and the second capacitor C2. The first passivation layer 114a is an insulating layer that protects components below the first passivation layer 114a, and may be configured of an inorganic material, such as silicon oxide SiOx or silicon nitride SiNx, but is not limited thereto.

[0161] The first planarization layer 115a is disposed on the first passivation layer 114a. The first planarization layer 115a may planarize an upper portion of the substrate 110 including the driving transistor DT. The first planarization layer 115a may be configured of a single layer or a double layer and, for example, of a photoresist, benzocyclobutene, or acrylic-based organic material, but is not limited thereto.

[0162] A plurality of reflective electrodes RE are disposed on the first planarization layer 115a. The plurality of reflective electrodes RE are structures that reflect light emitted from the plurality of light emitting diodes LED to above the substrate 110, and may be disposed to cover most areas of the plurality of sub-pixels SP. In addition, the plurality of reflective electrodes RE reflect light emitted from the light emitting diodes LED, and may also be used as electrodes of other structures that electrically connect the plurality of light emitting diodes LED and the sub-pixels SP. Taking into account light reflection efficiency and resistance, the plurality of reflective electrodes RE may include various conductive layers. For example, the reflective electrode RE may be formed of an opaque conductive layer having a high reflectivity, such as silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti) or an alloy thereof. In addition, the reflective electrode RE may also include a transparent conductive layer, such as indium tin oxide (ITO), to improve resistance.

[0163] The plurality of reflective electrodes RE include a first reflective electrode RE1 , a second reflective electrode RE2 , and a third reflective electrode RE3 .

[0164] The first reflective electrode RE1 is an electrode electrically connecting the first control source electrode ESE1 and the first light emitting diode LED1. The first reflective electrode RE1 may be electrically connected to the first control source electrode ESE1 through a contact hole formed in the first planarization layer 115a and the first passivation layer 114a. The first reflective electrode RE1 may be electrically connected to the first anode AD1 of the first light emitting diode LED1 through a first anode AD1 connection electrode CE, which will be described below. Therefore, the first control source electrode ESE1 of the first control transistor LET1 and the first anode AD1 of the first light emitting diode LED1 may be electrically connected to each other through the first reflective electrode RE1.

[0165] The second reflective electrode RE2 is an electrode that electrically connects the first control drain electrode EDE1 and the first light emitting diode LED1 and electrically connects the second control source electrode ESE2 and the second light emitting diode LED2 at the same time. The second reflective electrode RE2 may be electrically connected to the first control drain electrode EDE1 and the second control source electrode ESE2 through contact holes formed in the first planarization layer 115a and the first passivation layer 114a. The second reflective electrode RE2 may be electrically connected to the first cathode CD1 of the first light emitting diode LED1 through the first cathode CD1 connection electrode CE, which will be described below. In addition, the second reflective electrode RE2 may be electrically connected to the second anode AD2 of the second light emitting diode LED2 through the second anode AD2 connection electrode CE, which will be described below. Therefore, the first control drain electrode EDE1 of the first control transistor LET1 and the first cathode CD1 of the first light emitting diode LED1 may be electrically connected to each other through the second reflective electrode RE2. In addition, the second control source electrode ESE2 of the second control transistor LET2 and the second anode AD2 of the second light emitting diode LED2 may be electrically connected to each other through the second reflective electrode RE2.

[0166] The third reflective electrode RE3 is an electrode electrically connecting the second light emitting diode LED2, the driving source electrode DSE, and the second control drain electrode EDE2. The third reflective electrode RE3 may be electrically connected to the driving source electrode DSE through a contact hole formed in the first planarization layer 115a and the first passivation layer 114a. At this time, the driving source electrode DSE and the second control drain electrode EDE2 of the second control transistor LET2 are electrically connected to each other through the driving active layer DACT. Therefore, the third reflective electrode RE3 may also be electrically connected to the second control drain electrode EDE2. In addition, the third reflective electrode RE3 may be electrically connected to the second cathode CD2 of the second light emitting diode LED2 through the second cathode CD2 connecting electrode CE, which will be described below. Therefore, the second control drain electrode EDE2 and the driving source electrode DSE and the second cathode CD2 of the second light emitting diode LED2 may be electrically connected to each other through the third reflective electrode RE3.

[0167] Next, a second passivation layer 114b is disposed on the plurality of reflective electrodes RE. The second passivation layer 114B is an insulating layer protecting components under the second passivation layer 114B, and may be configured of a single layer or double layer of silicon oxide SiOx or silicon nitride SiNx, but is not limited thereto.

[0168] The adhesive layer 116 is disposed on the second passivation layer 114B. The adhesive layer 116 is formed on the front surface of the substrate 110 to fix a plurality of light emitting diodes LED disposed on the adhesive layer 116. The adhesive layer 116 may be formed of a photocurable adhesive material that is cured by light. For example, the adhesive layer 116 may be formed of an acrylic-based material including a photoresist, but is not limited thereto.

[0169] A plurality of light emitting diodes LED are disposed on the adhesive layer 116. The plurality of light emitting diodes LED are elements that emit light by current, and may be, for example, light emitting diodes (LEDs) or micro LEDs. The plurality of light emitting diodes LED include a red light emitting diode LED that emits red light, a green light emitting diode LED that emits green light, and a blue light emitting diode LED that emits blue light, and light having various colors including white is realized by a combination thereof. The first light emitting diode LED1 and the second light emitting diode LED2 disposed on the same sub-pixel SP to be connected in series may be light emitting diodes that emit light having the same color.

[0170] The first light emitting diode LED1 and the second light emitting diode LED2 may be formed to have substantially the same structure. The first semiconductor layer NL, the emission layer EL, the second semiconductor layer PL, the first anode AD1, the first cathode CD1, and the packaging film PAS of the first light emitting diode LED1 may have substantially the same configuration as the first semiconductor layer NL, the emission layer EL, the second semiconductor layer PL, the second anode AD2, the second cathode CD2, and the packaging film PAS of the second light emitting diode LED2.

[0171] First, the first light emitting diode LED1 includes a first semiconductor layer NL, an emission layer EL, a second semiconductor layer PL, a first anode AD1, a first cathode CD1, and a packaging film PAS.

[0172] The first semiconductor layer NL is disposed on the adhesive layer 116, and the second semiconductor layer PL is disposed on the first semiconductor layer NL. The first semiconductor layer NL and the second semiconductor layer PL may be layers formed by doping n-type and p-type impurities into a specific material. For example, the first semiconductor layer NL and the second semiconductor layer PL may be layers doped with n-type and p-type impurities in a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs). The p-type impurity may be magnesium (Mg), zinc (Zn), beryllium (Be), etc., and the n-type impurity may be silicon (Si), germanium, tin (Sn), etc., but is not limited thereto.

[0173] The emission layer EL is disposed between the first semiconductor layer NL and the second semiconductor layer PL. Holes and electrons are provided to the emission layer EL from the first semiconductor layer NL and the second semiconductor layer PL to emit light. The emission layer EL may be formed of a single layer or a multi-quantum well (MQW) structure, for example, may be formed of indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0174] The first cathode CD1 is disposed on the first semiconductor layer NL. The first cathode CD1 may be disposed on the top surface of the first semiconductor layer NL exposed from the emission layer EL and the second semiconductor layer PL. In this case, the first semiconductor layer NL electrically connected to the first cathode CD1 may be a semiconductor layer doped with n-type impurities. The first cathode CD1 may be electrically connected to the second anode AD2 of the second light emitting diode LED2, the first control drain electrode EDE1 of the first control transistor LET1, and the second control source electrode ESE2 of the second control transistor LET2 through the first cathode CD1 connection electrode CE and the second reflective electrode RE2. The first cathode CD1 may be configured of a conductive material, such as a transparent conductive material (such as indium tin oxide (ITO) or indium zinc oxide (IZO)) or an opaque conductive material (such as titanium (Ti), gold (Au), silver (Ag), copper (Cu) or an alloy thereof), but is not limited thereto.

[0175] The first anode AD1 is disposed on the second semiconductor layer PL. The first anode AD1 may be disposed on the top surface of the second semiconductor layer PL. The second semiconductor layer PL electrically connected to the first anode AD1 is a semiconductor layer doped with p-type impurities. The first anode AD1 may be electrically connected to the high potential power line VDD and the first control source electrode ESE1 of the first control transistor LET1 through the first anode AD1 connecting electrode CE and the first reflective electrode RE1. The first anode AD1 may be configured of a conductive material, such as a transparent conductive material (such as indium tin oxide (ITO) or indium zinc oxide (IZO)) or an opaque conductive material (such as titanium (Ti), gold (Au), silver (Ag), copper (Cu) or an alloy thereof), but is not limited thereto.

[0176] Next, a packaging film PAS encapsulating the first semiconductor layer NL, the emission layer EL, the second semiconductor layer PL, the first anode AD1, and the first cathode CD1 is provided. The packaging film PAS is formed of an insulating material to protect the first semiconductor layer NL, the emission layer EL, and the second semiconductor layer PL. In addition, a contact hole through which the first anode AD1 and the first cathode CD1 are exposed is formed in the packaging film PAS so that the first anode AD1 and the first cathode CD1 can be electrically connected to the first anode AD1 connecting electrode CE and the first cathode CD1 connecting electrode CE.

[0177] At the same time, a portion of the side surface of the first semiconductor layer NL may be exposed from the encapsulation film PAS. The light emitting diode LED manufactured on the wafer is separated from the wafer to be transferred to the display panel PN. However, during the process of separating the light emitting diode LED from the wafer, a portion of the encapsulation film PAS may be torn. For example, during the process of separating the light emitting diode LED from the wafer, a portion of the encapsulation layer PAS adjacent to the lower edge of the first semiconductor layer NL of the light emitting diode LED is torn. Therefore, a portion of the lower side surface of the first semiconductor layer NL may be exposed to the outside. However, even if the lower portion of the light emitting diode LED is exposed from the encapsulation film PAS, after forming the second planarization layer 115b and the third planarization layer 115c covering the side surface of the first semiconductor layer NL, the first anode AD1 connecting electrode CE and the first cathode CD1 connecting electrode CE are formed. Therefore, short circuit defects can be reduced.

[0178] Next, the second light emitting diode LED2 includes a first semiconductor layer NL, an emission layer EL, a second semiconductor layer PL, a second anode AD2, a second cathode CD2 and a packaging film PAS. The first semiconductor layer NL, the emission layer EL, the second semiconductor layer PL and the packaging film PAS of the second light emitting diode LED2 are formed of substantially the same structure and material as those of the first semiconductor layer NL, the emission layer EL, the second semiconductor layer PL and the packaging film PAS of the first light emitting diode LED1.

[0179] In addition, similar to the first cathode CD1 of the first light emitting diode LED1, the second cathode CD2 of the second light emitting diode LED2 is disposed on the first semiconductor layer NL and may be configured of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu) or an alloy thereof. In addition, the second cathode CD2 may be electrically connected to the driving source electrode DSE of the driving transistor DT and the second control drain electrode EDE2 of the second control transistor LET2 through the second cathode CD2 connecting electrode CE and the third reflective electrode RE3.

[0180] Similar to the first anode AD1 of the first light emitting diode LED1, the second anode AD2 of the second light emitting diode LED2 is disposed on the second semiconductor layer PL and may be configured of a transparent conductive material (such as indium tin oxide (ITO) or indium zinc oxide (IZO)) or an opaque conductive material (such as titanium (Ti), gold (Au), silver (Ag), copper (Cu) or an alloy thereof). The second anode AD2 may be electrically connected to the first cathode CD1 of the first light emitting diode LED1, the first control drain electrode EDE1 of the first control transistor LET1, and the second control source electrode ESE2 of the second control transistor LET2 through the second anode AD2 connecting electrode CE and the second reflective electrode RE2.

[0181] Next, the second planarization layer 115 b and the third planarization layer 115 c are disposed on the adhesive layer 116 and the light emitting diode LED.

[0182] The second planarization layer 115b overlaps a portion of the side surface of the plurality of light emitting diodes LED to fix and protect the plurality of light emitting diodes LED. The torn portion of the side surface of the first semiconductor layer NL of the packaging film PAS protecting the light emitting diode LED may be covered by the second planarization layer 115b. In this way, contact and short circuit defects of the connection electrode CE and the first semiconductor layer NL may be suppressed thereafter.

[0183] The third planarization layer 115c is formed to cover the upper portion of the second planarization layer 115b and the light emitting diode LED. A contact hole may be formed in the third planarization layer 115c, through which the first anode AD1 and the first cathode CD1 of the first light emitting diode LED1 and the second anode AD2 and the second cathode CD2 of the second light emitting diode LED2 are exposed. The first anode AD1, the first cathode CD1, the second anode AD2 and the second cathode CD2 are exposed from the third planarization layer 115c. However, the third planarization layer 115c is partially disposed in the region between the first anode AD1 and the first cathode CD1 of the first light emitting diode LED1 and the region between the second anode AD2 and the second cathode CD2 of the second light emitting diode LED2 to reduce short circuit defects. The second planarization layer 115b and the third planarization layer 115c may be configured by a single layer or a double layer, and are configured by, for example, a photoresist, a benzocyclobutene or an acrylic-based organic material, but are not limited thereto.

[0184] A plurality of connection electrodes CE are disposed on the third planarization layer 115c. The plurality of connection electrodes CE are electrodes that electrically connect the plurality of light emitting diodes LED and other structures of the sub-pixels SP. The plurality of connection electrodes CE include a first cathode CD1 connection electrode CE, a first anode AD1 connection electrode CE, a second cathode CD2 connection electrode CE, and a second anode AD2 connection electrode CE. The plurality of connection electrodes CE are formed of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), but are not limited thereto.

[0185] First, the first cathode CD1 connection electrode CE may be electrically connected to the second reflective electrode RE2 through a contact hole formed in the third planarization layer 115c, the second planarization layer 115b, and the second passivation layer 114B. In addition, the first cathode CD1 connection electrode CE may be electrically connected to the first cathode CD1 of the first light emitting diode LED1 through the contact hole of the third planarization layer 115c. Therefore, the first cathode CD1 and the second reflective electrode RE2 may be electrically connected through the first cathode CD1 connection electrode CE.

[0186] The first anode AD1 connection electrode CE may be electrically connected to the first reflective electrode RE1 through a contact hole formed in the third planarization layer 115c, the second planarization layer 115b, and the second passivation layer 114B. The first anode AD1 connection electrode CE may be electrically connected to the first anode AD1 of the first light emitting diode LED1 through the contact hole of the third planarization layer 115c. Therefore, the first anode AD1 and the first reflective electrode RE1 may be electrically connected through the first anode AD1 connection electrode CE.

[0187] The second cathode CD2 connection electrode CE may be electrically connected to the third reflective electrode RE3 through a contact hole formed in the third planarization layer 115c, the second planarization layer 115b, and the second passivation layer 114b. In addition, the second cathode CD2 connection electrode CE may be electrically connected to the second cathode CD2 of the second light emitting diode LED2 through the contact hole of the third planarization layer 115c. Therefore, the second cathode CD2 and the third reflective electrode RE3 may be electrically connected through the second cathode CD2 connection electrode CE.

[0188] The second anode AD2 connection electrode CE may be electrically connected to the second reflective electrode RE2 through a contact hole formed in the third planarization layer 115c, the second planarization layer 115b, and the second passivation layer 114B. The second anode AD2 connection electrode CE may be electrically connected to the second anode AD2 of the second light emitting diode LED2 through the contact hole of the third planarization layer 115c. Therefore, the second anode AD2 and the second reflective electrode RE2 may be electrically connected through the second anode AD2 connection electrode CE.

[0189] Meanwhile, both the first cathode CD1 connection electrode CE and the second anode AD2 connection electrode CE may be connected to the second reflective electrode RE2. Although the first cathode CD1 connection electrode CE and the second anode AD2 connection electrode CE are shown in the drawings as being spaced apart from each other on the second reflective electrode RE2, the first cathode CD1 connection electrode CE and the second anode AD2 connection electrode CE are connected as one body, but are not limited thereto.

[0190] Next, the bank BB is disposed on the second planarization layer 115b. The bank BB is disposed to be spaced apart from the light emitting diode LED by a predetermined interval and at least partially overlap the plurality of reflective electrodes RE. In addition, the bank BB may be disposed to cover at least a portion of the plurality of connection electrodes CE. The bank BB may be formed of an opaque material to reduce color mixing between the plurality of sub-pixels SP, and may be formed of a black resin, for example, but is not limited thereto.

[0191] The protective layer 117 is disposed on the plurality of connection electrodes CE and the bank BB. The protective layer 117 is a layer for protecting the structure below the protective layer 117. The protective layer 117 may be configured by a single layer or a double layer, and is composed of, for example, benzocyclobutene, a light-transmitting epoxy resin, a photoresist, or an acrylic-based organic material, but is not limited thereto.

[0192] Meanwhile, the display device 100 according to an exemplary embodiment of the present disclosure includes the gate driver GD and the data driver DD as described above to drive the plurality of sub-pixels SP of the display panel PN. At this time, the gate driver GD generates the first scan signal SCAN1, the second scan signal SCAN2, and the emission control signal EM to apply the signals to the first scan line SL1, the second scan line SL2, and the emission control line EML. In addition, the gate driver GD also generates the first control signal LE1 and the second control signal LE2 to apply the signals to the first control line LEL1 and the second control line LEL2. Specifically, any one of the first control signal LE1 and the second control signal LE2 has the same waveform as the first scan signal SCAN1, so that the first scan signal SCAN1 generated in the gate driver GD can be used for any one of the first control signal LE1 and the second control signal LE2. Therefore, the display device 100 according to an exemplary embodiment of the present disclosure further includes a control signal generating circuit LEC, which additionally generates the first control signal LE1 and the second control signal LE2 to the gate driver GD including the plurality of first stages ST1, which generates the first scan signal SCAN1.

[0193] In the following, reference will be made to Figure 8 and Fig. 9 The control signal generating circuit LEC is described in detail.

[0194] Figure 8 is a diagram of a gate driver of a display device according to an exemplary embodiment of the present disclosure. Fig. 9 is a circuit diagram of a control signal generating circuit of a display device according to an exemplary embodiment of the present disclosure. Fig.10 is a driving timing diagram of a control signal generating circuit of a display device according to an exemplary embodiment of the present disclosure.

[0195] First, the gate driver GD includes a plurality of first stages ST1 to generate a first scan signal SCAN1. The plurality of first stages ST1 are connected in relation and may generate the first scan signal SCAN1 based on a start signal VST or a first scan signal SCAN1 output from a first stage ST1 of a previous stage. For example, the first stage ST1 at the top receives the start signal VST to output the first scan signal SCAN1 to the first scan line SL1 at the top. The nth first stage ST1 receives the first scan signal SCAN1 from the n-1th first stage ST1 of the previous stage to output the first scan signal SCAN1 to the nth first scan line SL1.

[0196] In addition, the control signal generating circuit LEC is connected to the output terminal of each of the plurality of first stages ST1. The control signal generating circuit LEC includes a first circuit LEC1 and a second circuit LEC2, and each of the first circuit LEC1 and the second circuit LEC2 receives the first scan signal SCAN1 output from the first stage ST1 to generate a first control signal LE1 and a second control signal LE2.

[0197] refer to Fig. 9 , the first circuit LEC1 is a circuit that generates a first control signal LE1 and a second control signal LE2 when the first light emitting diode LED1 emits light. The first circuit LEC1 can generate a first control signal LE1 having the same waveform as the first scan signal SCAN1 and a second control signal LE2 of a conduction level. The first circuit LEC1 includes a first connection transistor CT1, a second connection transistor CT2, a first auxiliary transistor Tbv1, and a first boosting capacitor Cb1.

[0198] First, the first connection transistor CT1 is a transistor that selectively connects the output terminal of the first stage ST1 and the first control line LEL1. The gate electrode of the first connection transistor CT1 is connected to the drain electrode of the first auxiliary transistor Tbv1 and the Q1 node Q1, the source electrode is connected to the output terminal of the first stage ST1, and the drain electrode can be connected to the first control line LEL1. The first connection transistor CT1 can be turned on or off based on the first enable signal EN1 transmitted through the first auxiliary transistor Tbv1. The turned-on first connection transistor CT1 can connect the output terminal of the first stage ST1 and the first control line LEL1, and the first scan signal SCAN1 from the first stage ST1 can be transmitted to the first control line LEL1 through the first connection transistor CT1. Therefore, the first scan signal SCAN1 is transmitted to the first control line LEL1 as it is, so that the first scan signal SCAN1 and the first control signal LE1 can have the same waveform.

[0199] The second connection transistor CT2 is a transistor that selectively connects the gate low line and the second control line LEL2. The gate electrode of the second connection transistor CT2 is connected to the drain electrode of the first auxiliary transistor Tbv1 and the Q1 node Q1, the source electrode is connected to the gate low line, and the drain electrode can be connected to the second control line LEL2. The second connection transistor CT2 can be turned on or off based on the first enable signal EN1 transmitted through the first auxiliary transistor Tbv1. The turned-on second connection transistor CT2 can connect the gate low line and the second control line LEL2, and the gate low voltage VGL of the gate low line can be transmitted to the second control line LEL2 through the second connection transistor CT2. Therefore, the gate low voltage VGL is used as a low level of the second control signal LE2 to be output to the second control line LEL2.

[0200] The first auxiliary transistor Tbv1 is connected between the first enable line and the Q1 node Q1. The gate electrode of the first auxiliary transistor Tbv1 is connected to the gate low line, the source electrode is connected to the first enable line, and the drain electrode is connected to the Q1 node Q1. The first auxiliary transistor Tbv1 whose gate electrode is connected to the gate low line is always turned on and can electrically connect the first enable line and the Q1 node Q1.

[0201] The first boost capacitor Cb1 is connected between the Q1 node Q1 and the first control line LEL1. The voltage of the Q1 node Q1 can be instantaneously lower than the first enable voltage, and the first connection transistor CT1 stably maintains the on state through the bootstrap of the first boost capacitor Cb1. Therefore, the first boost capacitor Cb1 can assist the first scan signal SCAN1 to be output as the first control signal LE1 without distortion and delay.

[0202] Next, the second circuit LEC2 is a circuit that generates a first control signal LE1 and a second control signal LE2 when the second light emitting diode LED2 emits light. The second circuit LEC2 can generate a first control signal LE1 and a second control signal LE2 having a conduction level with the same waveform as the first scan signal SCAN1. The second circuit LEC2 includes a third connection transistor CT3, a fourth connection transistor CT4, a second auxiliary transistor Tbv2, and a second boost capacitor Cb2.

[0203] The third connection transistor CT3 is a transistor that selectively connects the output terminal of the first stage ST1 and the second control line LEL2. The gate electrode of the third connection transistor CT3 is connected to the drain electrode of the second auxiliary transistor Tbv2 and the Q2 node Q2, the source electrode is connected to the output terminal of the first stage ST1, and the drain electrode can be connected to the second control line LEL2. The third connection transistor CT3 can be turned on or off based on the second enable signal EN2 transmitted through the second auxiliary transistor Tbv2. The turned-on third connection transistor CT3 can connect the output terminal of the first stage ST1 and the second control line LEL2, and the first scan signal SCAN1 from the first stage ST1 can be transmitted to the second control line LEL2 through the third connection transistor CT3. Therefore, the first scan signal SCAN1 is transmitted to the second control line LEL2 as it is, so that the first scan signal SCAN1 and the second control signal LE2 can have the same waveform.

[0204] The fourth connection transistor CT4 is a transistor that selectively connects the gate low line and the first control line LEL1. The gate electrode of the fourth connection transistor CT4 is connected to the drain electrode of the second auxiliary transistor Tbv2 and the Q2 node Q2, the source electrode is connected to the gate low line, and the drain electrode can be connected to the first control line LEL1. The fourth connection transistor CT4 can be turned on or off based on the second enable signal EN2 transmitted through the second auxiliary transistor Tbv2. The turned-on fourth connection transistor CT4 can connect the gate low line and the first control line LEL1, and the gate low voltage VGL of the gate low line can be transmitted to the first control line LEL1 through the fourth connection transistor CT4. Therefore, the gate low voltage VGL is used as a low level of the first control signal LE1 to be output to the first control line LEL1.

[0205] The second auxiliary transistor Tbv2 is connected between the second enable line and the Q2 node Q2. The gate electrode of the second auxiliary transistor Tbv2 is connected to the gate low line, the source electrode is connected to the second enable line, and the drain electrode is connected to the Q2 node Q2. The second auxiliary transistor Tbv2 whose gate electrode is connected to the gate low line is always turned on and can electrically connect the second enable line and the Q2 node Q2.

[0206] The second boost capacitor Cb2 is connected between the Q2 node Q2 and the second control line LEL2. The voltage of the Q2 node Q2 can be lower than the second enable voltage, and the third connection transistor CT3 stably maintains the on state through the bootstrap of the second boost capacitor Cb2. Therefore, the second boost capacitor Cb2 can assist the first scan signal SCAN1 to be output as the second control signal LE2 without distortion and delay.

[0207] Next, let’s refer to Fig. 9 and Fig.10 , the period between time A and time B is the period during which the first light emitting diode LED1 is driven, and the period between time C and time D is the period during which the second light emitting diode LED2 is driven.

[0208] First, in a period between time A and time B, the first circuit LEC1 may generate and output the first control signal LE1 and the second control signal LE2 to allow only the first light emitting diode LED1 to emit light.

[0209] In the period between time A and time B, the first enable signal EN1 of low level is output to the first enable line, and the second enable signal EN2 of high level is output to the second enable line. At this time, the first enable signal EN1 and the second enable signal EN2 are signals with opposite phases. For example, when the first enable signal EN1 is high level, the second enable signal EN2 may be low level, and when the first enable signal EN1 is low level, the second enable signal EN2 may be high level. Therefore, the conduction period of the first connection transistor CT1 and the second connection transistor CT2 in which the first enable signal EN1 is applied to the gate electrode and the conduction period of the third connection transistor CT3 and the fourth connection transistor CT4 in which the second enable signal EN2 is applied to the gate electrode can be configured in turn.

[0210] In addition, in the first circuit LEC1, a low-level first enable signal EN1 may be applied to the Q1 node Q1 through the first auxiliary transistor Tbv1. The first connection transistor CT1 and the second connection transistor CT2 may be turned on by the low-level first enable signal EN1 applied to the Q1 node Q1. The turned-on first connection transistor CT1 may connect the output terminal of the first stage ST1 and the first control line LEL1, and the first control signal LE1 having the same waveform as the first scan signal SCAN1 may be output to the first control line LEL1. The turned-on second connection transistor CT2 may connect the gate low line and the second control line LEL2, and output a low-level second control signal LE2, which is the same voltage as the gate low voltage VGL. Therefore, the first control signal LE1 having the same waveform as the first scan signal SCAN1 is output to the first control line LEL1, and the low-level second control signal LE2 may be output to the second control line LEL2. Therefore, during the period in which the first light emitting diode LED1 emits light, the second control transistor LET2 maintains a turn-on phase, so that the second light emitting diode LED2 does not emit light.

[0211] In addition, in the period between time A and time B, the high-level second enable signal EN2 output to the second enable line may be transmitted to the Q2 node Q2 of the second circuit LEC2. Therefore, the third connection transistor CT3 and the fourth connection transistor CT4 of the second circuit LEC2 may be turned off by the high-level second enable signal EN2. In addition, the first scan signal SCAN1 is not output to the second control line LEL2, or the gate low voltage VGL is not output to the first control line LEL1.

[0212] Next, in a period between time C and time D, a high-level first enable signal EN1 is output to the first enable line, and a low-level second enable signal EN2 is output to the second enable line.

[0213] In the first circuit LEC1, a high-level first enable signal EN1 may be applied to the Q1 node Q1 through the first auxiliary transistor Tbv1. The first connection transistor CT1 and the second connection transistor CT2 may be turned off by the high-level first enable signal EN1 applied to the Q1 node Q1. Therefore, no signal may be output from the first circuit LEC1 to the first control line LEL1 and the second control line LEL2.

[0214] In the second circuit LEC2, the second enable signal EN2 of low level may be applied to the Q2 node Q2 through the second auxiliary transistor Tbv2. The third connection transistor CT3 and the fourth connection transistor CT4 may be turned on by the second enable signal EN2 of low level applied to the Q2 node Q2. The turned-on third connection transistor CT3 may connect the output terminal of the first stage ST1 and the second control line LEL2, and the second control signal LE2 having the same waveform as the first scan signal SCAN1 may be output to the second control line LEL2. The turned-on fourth connection transistor CT4 may connect the gate low line and the first control line LEL1, and output the first control signal LE1 of low level, which is the same voltage as the gate low voltage VGL. Therefore, the first control signal LE1 of low level is output to the first control line LEL1, and the second control signal LE2 having the same waveform as the first scan signal SCAN1 may be output to the second control line LEL2. Therefore, during the period in which the second light emitting diode LED2 emits light, the first control transistor LET1 maintains the conduction stage, so that the first light emitting diode LED1 does not emit light.

[0215] Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, the control signal generating circuit LEC is connected to the output terminals of the plurality of first stages ST1 of the gate driver GD to easily generate the first control signal LE1 and the second control signal LE2. First, the control signal generating circuit LEC includes the first circuit LEC1 and the second circuit LEC2. When the first light emitting diode LED1 emits light, the first circuit LEC1 generates the first control signal LE1 having the same waveform as the first scan signal SCAN1 to apply the first control signal to the first control line LEL1. When the first light emitting diode LED1 emits light, the first circuit LEC1 generates the second control signal LE2 of the conduction level that turns on the second control transistor LET2 so as not to allow the second light emitting diode LED2 to emit light, thereby applying the second control signal of the conduction level to the second control line LEL2. For example, the first circuit LEC1 outputs the first scan signal SCAN1 received from the first stage ST1 to the first control line LEL1 as the first control signal LE1, and may output the second control signal LE2 of the low level to the second control line LEL2. Therefore, in a frame or a horizontal period in which the first light emitting diode LED1 emits light, the first circuit LEC1 may be used to generate the first control signal LE1 and the second control signal LE2.

[0216] In addition, when the second light emitting diode LED2 emits light, the second circuit LEC2 generates a first control signal LE1 of a conduction level that turns on the first control transistor LET1 so as not to allow the first light emitting diode LED1 to emit light, thereby applying the first control signal of the conduction level to the first control line LEL1. When the second light emitting diode LED2 emits light, the second circuit LEC2 generates a second control signal LE2 having the same waveform as the first scan signal SCAN1 to apply the second control signal to the second control line LEL2. For example, the second circuit LEC2 outputs the first scan signal SCAN1 received from the first stage ST1 to the second control line LEL2 as the second control signal LE1, and can output the low-level first control signal LE1 to the first control line LEL1. Therefore, in a frame or horizontal period in which the second light emitting diode LED2 emits light, the first control signal LE1 and the second control signal LE2 can be generated using the second circuit LEC2. Therefore, the existing first scan signal SCAN1 and the gate low voltage VGL are used as the first control signal LE1 and the second control signal LE2 as they are, so that the structure of the gate driver GD can be simplified.

[0217] Exemplary embodiments of the present disclosure may also be described as follows:

[0218] According to one aspect of the present disclosure, a display device includes: a display panel, in which a plurality of sub-pixels are defined; a first light-emitting diode arranged in each of the plurality of sub-pixels; a second light-emitting diode connected in series with the first light-emitting diode; a first control transistor, which is connected in parallel with the first light-emitting diode and is turned on by a first control signal; and a second control transistor, which is connected in parallel with the second light-emitting diode and is turned on by a second control signal.

[0219] The first light emitting diode and the second light emitting diode may emit light in turn.

[0220] When the first light emitting diode emits light, the first control transistor may be turned off, and the second control transistor may be turned on.

[0221] When the first light emitting diode emits light, a driving current may flow from the first light emitting diode to the second control transistor.

[0222] When the second light emitting diode emits light, the first control transistor may be turned on, and the second control transistor may be turned off.

[0223] When the second light emitting diode emits light, a driving current may flow from the first control transistor to the second light emitting diode.

[0224] The display device may further include: a gate driver electrically connected to the display panel and outputting a first scan signal, the first control signal, and the second control signal to the plurality of sub-pixels. The gate driver may include: a plurality of first stages generating the first scan signal; and a plurality of control signal generating circuits connected to output terminals of the plurality of first stages and generating the first control signal and the second control signal to output the first control signal and the second control signal to a first control line and a second control line.

[0225] Each of the multiple control signal generating circuits may include: a first circuit, which outputs the first control signal and the second control signal to the first control line and the second control line when the first light-emitting diode emits light; and a second circuit, which outputs the first control signal and the second control signal to the first control line and the second control line when the second light-emitting diode emits light, and the first circuit can output the first scan signal as the first control signal and output a gate low voltage as the second control signal, and the second circuit can output the gate low voltage as the first control signal and output the first scan signal as the second control signal.

[0226] The first circuit may include: a first connecting transistor, the first connecting transistor having a gate electrode connected to the Q1 node and a source electrode and a drain electrode connected between the output terminals of the multiple first stages and the first control line; a second connecting transistor, the second connecting transistor having a gate electrode connected to the Q1 node and a source electrode and a drain electrode connected between a gate low line and the second control line; and a first auxiliary transistor, the first auxiliary transistor transmitting a first enable signal to the first node, and the second circuit includes: a third connecting transistor, the third connecting transistor having a gate electrode connected to the Q2 node and a source electrode and a drain electrode connected between the output terminals of the multiple first stages and the second control line; a fourth connecting transistor, the fourth connecting transistor having a gate electrode connected to the Q2 node and a source electrode and a drain electrode connected between the gate low line and the first control line; and a second auxiliary transistor, the second auxiliary transistor transmitting a second enable signal to the Q2 node.

[0227] The first enable signal and the second enable signal may be signals having opposite phases.

[0228] The on-periods of the first connection transistor and the second connection transistor and the on-periods of the third connection transistor and the fourth connection transistor may be configured in turn.

[0229] According to another aspect of the present disclosure, a display device includes: a substrate; an adhesive layer disposed on the substrate; a first light-emitting diode disposed on the adhesive layer and including a first anode and a first cathode; a second light-emitting diode disposed on the adhesive layer and including a second anode and a second cathode; and a plurality of reflective electrodes disposed between the substrate and the adhesive layer. The plurality of reflective electrodes include: a first reflective electrode electrically connected to the first anode; a second reflective electrode electrically connected to the first cathode and the second anode; and a third reflective electrode electrically connected to the second cathode.

[0230] The display device may further include: a first control transistor, the first control transistor being disposed between the substrate and the plurality of reflective electrodes and including a first control source electrode electrically connected to a high potential power line; a second control transistor, the second control transistor being disposed between the substrate and the plurality of reflective electrodes and including a second control source electrode electrically connected to a first control drain electrode of the first control transistor; and a drive transistor, the drive transistor being disposed between the substrate and the plurality of reflective electrodes and including a drive source electrode electrically connected to a second control drain electrode of the second control transistor. The first reflective electrode may be electrically connected to the first control source electrode and the high potential power line, the second reflective electrode is electrically connected to the first control drain electrode and the second control source electrode, and the third reflective electrode is electrically connected to the second control drain electrode and the drive source electrode.

[0231] The display device may further include: a planarization layer, the planarization layer covering the first light emitting diode and the second light emitting diode; and a plurality of connection electrodes, the plurality of connection electrodes being disposed on the planarization layer and electrically connecting the first light emitting diode and the second light emitting diode to the plurality of reflective electrodes through contact holes of the planarization layer. The plurality of connection electrodes may include: a first anode connection electrode, the first anode connection electrode electrically connecting the first anode and the first reflective electrode; a first cathode connection electrode, the first cathode connection electrode electrically connecting the first cathode and the second reflective electrode; a second anode connection electrode, the second anode connection electrode electrically connecting the second anode and the second reflective electrode; and a second cathode connection electrode, the second cathode connection electrode electrically connecting the second cathode and the third reflective electrode.

[0232] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all aspects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be interpreted as falling within the scope of the present disclosure.

Claims

1. A display device, comprising: a display panel, wherein a plurality of sub-pixels are defined in the display panel; a first light emitting diode disposed in each of the plurality of sub-pixels; a second light emitting diode connected in series with the first light emitting diode; a first control transistor, the first control transistor being connected in parallel with the first light emitting diode and being turned on by a first control signal; as well as A second control transistor is connected in parallel with the second light emitting diode and is turned on by a second control signal.

2. The display device according to claim 1, characterized in that The first light emitting diode and the second light emitting diode emit light in turn.

3. The display device according to claim 2, characterized in that: When the first light emitting diode emits light, the first control transistor is turned off and the second control transistor is turned on.

4. The display device according to claim 3, characterized in that: When the first light emitting diode emits light, a driving current flows from the first light emitting diode to the second control transistor.

5. The display device according to claim 2, characterized in that: When the second light emitting diode emits light, the first control transistor is turned on and the second control transistor is turned off.

6. The display device according to claim 5, characterized in that: When the second light emitting diode emits light, a driving current flows from the first control transistor to the second light emitting diode.

7. The display device according to claim 2, characterized in that: The display device further includes: a gate driver electrically connected to the display panel and outputting a first scan signal, the first control signal, and the second control signal to the plurality of sub-pixels, Wherein, the gate driver comprises: a plurality of first stages, the plurality of first stages generating the first scanning signal; and A plurality of control signal generating circuits, each of which is connected to an output terminal of a corresponding one of the plurality of first stages, and generates the first control signal and the second control signal to output the first control signal and the second control signal to a first control line and a second control line.

8. The display device according to claim 7, characterized in that: Each of the plurality of control signal generating circuits comprises: a first circuit that outputs the first control signal and the second control signal to the first control line and the second control line when the first light emitting diode emits light; and a second circuit that outputs the first control signal and the second control signal to the first control line and the second control line when the second light emitting diode emits light, and The first circuit outputs the first scan signal as the first control signal and outputs a gate low voltage as the second control signal, and the second circuit outputs the gate low voltage as the first control signal and outputs the first scan signal as the second control signal.

9. The display device according to claim 8, characterized in that: The first circuit comprises: a first connection transistor having a gate electrode connected to a first node (Q1) and a source electrode and a drain electrode connected between an output terminal of a corresponding one of the plurality of first stages and the first control line; a second connection transistor having a gate electrode connected to the first node and source and drain electrodes connected between a gate low line and the second control line; and a first auxiliary transistor, the first auxiliary transistor transmitting a first enable signal to the first node, and The second circuit comprises: a third connection transistor having a gate electrode connected to the second node (Q2) and a source electrode and a drain electrode connected between the output terminal of the corresponding one of the plurality of first stages and the second control line; a fourth connection transistor having a gate electrode connected to the second node and source and drain electrodes connected between the gate low line and the first control line; and A second auxiliary transistor is provided, wherein the second auxiliary transistor transmits a second enable signal to the second node.

10. The display device according to claim 9, characterized in that: The first enable signal and the second enable signal are signals having opposite phases.

11. The display device according to claim 10, characterized in that: The conduction periods of the first connection transistor and the second connection transistor and the conduction periods of the third connection transistor and the fourth connection transistor are configured in turn.

12. The display device according to claim 9, characterized in that: The first circuit also includes a first boost capacitor connected between the first node and the first control line; and The second circuit also includes a second boost capacitor connected between the second node and the second control line.

13. A display device, comprising: substrate; an adhesive layer, the adhesive layer being disposed on the substrate; a first light emitting diode disposed on the adhesive layer and comprising a first anode and a first cathode; a second light emitting diode disposed on the adhesive layer and comprising a second anode and a second cathode; as well as a plurality of reflective electrodes, wherein the plurality of reflective electrodes are disposed between the substrate and the adhesive layer, Wherein, the plurality of reflective electrodes include: a first reflective electrode, the first reflective electrode being electrically connected to the first anode; a second reflective electrode electrically connected to the first cathode and the second anode; and A third reflective electrode is electrically connected to the second cathode.

14. The display device according to claim 13, characterized in that: The display device further includes: a first control transistor disposed between the substrate and the plurality of reflective electrodes and including a first control source electrode electrically connected to a high potential power line; a second control transistor disposed between the substrate and the plurality of reflective electrodes and comprising a second control source electrode electrically connected to the first control drain electrode of the first control transistor; and a driving transistor disposed between the substrate and the plurality of reflective electrodes and comprising a driving source electrode electrically connected to a second control drain electrode of the second control transistor, The first reflective electrode is electrically connected to the first control source electrode and the high potential power line, the second reflective electrode is electrically connected to the first control drain electrode and the second control source electrode, and the third reflective electrode is electrically connected to the second control drain electrode and the driving source electrode.

15. The display device according to claim 14, characterized in that: The display device further includes: a planarization layer, the planarization layer covering the first light emitting diode and the second light emitting diode; and A plurality of connecting electrodes, the plurality of connecting electrodes are arranged on the planarization layer and connected through the planarization layer F24-1007CN001_23PD5080CN The contact holes electrically connect the first light emitting diode and the second light emitting diode to the plurality of reflective electrodes, Wherein, the plurality of connecting electrodes include: a first anode connection electrode, the first anode connection electrode electrically connecting the first anode and the first reflective electrode; a first cathode connecting electrode, the first cathode connecting electrode electrically connecting the first cathode and the second reflective electrode; a second anode connection electrode, the second anode connection electrode electrically connecting the second anode and the second reflective electrode; and A second cathode connecting electrode is provided, wherein the second cathode connecting electrode is electrically connected to the second cathode and the third reflective electrode.

Images