Semiconductor device manufacturing method based on glass adapter plate and semiconductor device

Abstract

The invention provides a semiconductor device manufacturing method based on a glass adapter plate and a semiconductor device, and the method comprises the steps: S1, forming a plurality of metal pattern layers on a silicon substrate in a stacking manner, the plurality of metal pattern layers are electrically connected with each other, and the thickness of the metal pattern layers is in a range of 0.05-15 [mu] m; step S2, bonding one surface, with the plurality of metal pattern layers, of the silicon substrate with a TGV glass sheet in a face-to-face manner, wherein the thickness of the TGV glass sheet is in a range of 20-2000 [mu] m; and S3, the silicon substrate is removed, and the thickness of the glass layer of the TGV glass sheet is reduced to 15 [mu] m to 1900 [mu] m. By utilizing the manufacturing method, the manufacturing of the high-density metal interconnected glass adapter plate can be completed, a characteristic structure of glass, a silicon layer and a dielectric layer is obtained, and all processes can be compatible with a silicon-based Fab, so that a finer metal interconnected structure on the glass adapter plate is completed.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor device manufacturing, and in particular relates to a semiconductor device manufacturing method based on a glass transfer plate and a semiconductor device. Background Art

[0002] In 2.5D CoWoS (Chip-on-Wafer-on-Substrate), wafers are mainly made of Si material. Si Wafer belongs to the front-end process of the entire semiconductor and is currently widely used. Glass material is also widely considered as a candidate material to replace silicon chips. However, the current glass processing technology is incompatible with the silicon-based circuit process. The line width that can be achieved by the glass substrate is at the level of tens of μm, which is too large to meet the relatively fine size requirements of the adapter board. Summary of the invention

[0003] To this end, the present invention provides a method for manufacturing a semiconductor device based on a glass transfer plate, the method comprising: step S1, stacking a plurality of metal graphic layers on a silicon substrate, the plurality of metal graphic layers being electrically connected to each other and having a thickness in the range of 0.05 μm to 15 μm; step S2, face-to-face bonding of one side of the silicon substrate having the plurality of metal graphic layers to a TGV glass sheet, the thickness of the TGV glass sheet being in the range of 20 μm to 2000 μm; step S3, removing the silicon substrate and thinning the glass layer thickness of the TGV glass sheet to 15 μm to 1900 μm.

[0004] Furthermore, preferably, in the semiconductor device manufacturing method of the present invention, when forming the plurality of metal pattern layers on the silicon substrate, the Damascus process is used to form them in order from large to small critical dimensions.

[0005] In addition, preferably, in the semiconductor device manufacturing method of the present invention, in the step S1, each metal graphic layer in the plurality of metal graphic layers is formed in the order of TM2, TM1, M5, M4, M3, M2, and M1.

[0006] Furthermore, preferably, in the semiconductor device manufacturing method of the present invention, in the step S2, the silicon substrate and the TGV glass sheet are bonded by anodic bonding or hybrid bonding.

[0007] Furthermore, preferably, in the semiconductor device manufacturing method of the present invention, the silicon substrate is connected to the positive pole of the power supply, the TGV glass sheet is connected to the negative pole of the power supply, a voltage of 500V to 1000V is applied, and the heating temperature is maintained at 300°C to 500°C.

[0008] In addition, preferably, in the semiconductor device manufacturing method of the present invention, when voltage is applied, the Na ions in the TGV glass sheet will drift toward the negative electrode and form a depletion layer with a thickness of 1 μm to 10 μm on the glass surface adjacent to the silicon wafer until the current between each of the multiple graphic circuit layers is reduced to near zero.

[0009] Furthermore, preferably, in the method for manufacturing a semiconductor device of the present invention, a silicon layer having a thickness ranging from 0.05 μm to 300 μm is pre-grown on the surface of the TGV glass sheet.

[0010] Furthermore, preferably, in the semiconductor device manufacturing method of the present invention, before the face-to-face bonding is performed, silicon layers are grown on the front and back surfaces of the TGV glass sheet using low pressure chemical vapor deposition or silicon epitaxial chemical vapor deposition.

[0011] Furthermore, preferably, in the semiconductor device manufacturing method of the present invention, a Damascus copper process or a silicon-based process is used to realize electrical connection of the plurality of metal pattern layers.

[0012] In addition, preferably, the present invention provides a semiconductor device manufactured using any of the semiconductor device manufacturing methods described above.

[0013] The present invention significantly increases the contact area between the mixed bonding metals by utilizing the above process method, thereby increasing the bonding force of the metal-to-metal bonding, and ultimately significantly increasing the bonding strength of the semiconductor device. Therefore, by utilizing the present invention, it is possible to complete the production of a glass transfer board with high-density metal interconnection, obtain a characteristic structure of glass + silicon layer + dielectric layer, and achieve that all processes are compatible with silicon-based Fab, thereby completing a more sophisticated metal interconnection structure on the glass transfer board. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a diagram showing the insertion loss versus frequency for a transmission line on glass and a standard silicon substrate according to one embodiment of the present invention.

[0015] Figure 2 is a schematic diagram showing that the CTE of glass according to one embodiment of the present invention is between the bottom organic material and the top silicon to improve the shape management effect.

[0016] Figure 3 Schematic diagram showing a process flow of a glass substrate electrical circuit array according to one embodiment of the present invention.

[0017] Figure 4 Schematic diagram showing a glass transfer plate process flow of a silicon wafer-to-wafer process according to one embodiment of the present invention.

[0018] Figure 5 Schematic diagram showing the principle of glass-silicon wafer anodic bonding according to one embodiment of the present invention.

[0019] Figure 6 Schematic diagram showing the principle of glass-silicon wafer anodic bonding according to one embodiment of the present invention.

[0020] Figure 7 FIG. 4 is a schematic diagram showing a process flow of covering a glass substrate with silicon according to an embodiment of the present invention.

[0021] Figure 8 is a schematic diagram illustrating furnace tube polysilicon deposition according to one embodiment of the present invention.

[0022] Fig. 9 is a schematic diagram illustrating a silicon vapor phase epitaxy process according to one embodiment of the present invention.

[0023] Fig.10 is a schematic diagram showing a characteristic structure of a semiconductor device according to one embodiment of the present invention. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Other embodiments or variations obtained based on the embodiments in the present application by ordinary technicians in this field without creative work are all within the scope of protection of this application.

[0025] In 2.5D CoWoS (Chip-on-Wafer-on-Substrate), wafers are mainly made of Si material. The reason is that Si wafer belongs to the front-end process of the entire semiconductor, the process flow is more mature, the line width can be smaller, and the circuit density is higher, so it is currently widely used.

[0026] Glass is currently widely considered as a candidate material to replace silicon chips. Glass has the following advantages over silicon:

[0027] 1. Lower electrical loss: Since glass has better insulation performance than silicon, the loss of electrical signals in its high-frequency oscillation circuit is less. The relationship between signal loss and frequency is as follows: Figure 1 shown.

[0028] 2. Adjustable CTE: The thermal expansion coefficient of glass can be adjusted by adjusting the composition of glass. Currently, the CTE can be adjusted within the range of 2.7-12.4, so it can better adapt to different organic substrates, carrier wafers and other materials; based on the same considerations, its TTV / warpage and other parameters can also be better than silicon, and the shape management effect is as follows: Figure 2 shown.

[0029] 3. Cost advantage: The cost of glass is lower than that of silicon, and its size can be made larger and its shapes more diverse.

[0030] However, the current glass processing technology is incompatible with the silicon-based circuit technology. The line width that can ultimately be achieved by the glass-based substrate is at the level of tens of μm, which is too large to meet the relatively fine size requirements of the adapter board.

[0031] Figure 3 Schematic diagram showing the process flow of glass substrate electrical circuit array according to one embodiment of the present invention. The density of electrical interconnection in this solution is relatively low, and the electrical performance cannot meet the requirements of high-performance adapter boards.

[0032] If you want to use a glass adapter board instead of a silicon adapter board, you need to shrink the circuit size. The metal interconnection above the TSV of the currently commonly used silicon adapter board uses the copper Damascus process. Therefore, we want to use the silicon-based Damascus process and the glass TGV process to realize the production of the glass adapter board.

[0033] To achieve the interconnection density of silicon adapter boards. The existing technology is to directly perform metallization interconnection on glass by imitating the Damascus process of silicon. The existing processes are all developed based on silicon wafers, so the entire set of process parameters are set and debugged for silicon materials. Switching the material to glass involves a large number of recipe debugging due to the different material properties, which is a huge workload; for example, the original photolithography process determines the mask layer, photoresist thickness, alignment, paving, development and other parameters based on the reflective characteristics of silicon. Now the material is replaced with glass. Since the light transmittance of glass and silicon is very different, all the above parameters need to be changed accordingly. A lot of experimental debugging work is required to determine the final series of delivery conditions.

[0034] Some aspects cannot be covered by the recipe software and need to be implemented through hardware modification, which is more expensive. For example, PVD, ETCH and other machines fix the wafer by ECHUCK electrostatic adsorption. Due to the insulating nature of glass material, it is necessary to change the way the suction cup grabs the wafer, such as changing to vacuum adsorption.

[0035] At this time, the design requires the cooperation of multiple departments such as manufacturers, equipment engineers, process engineers and even factory affairs, which requires a huge amount of resources.

[0036] In summary, there are currently two main solutions:

[0037] 1. The common method of the original glass panel is used for electrical interconnection. The line width can be reduced and the interconnection density can be increased through recipe optimization. However, due to the limitation of the overall process flow principle, the interconnection density of this method is low and cannot meet the requirements of high-performance adapter boards;

[0038] 2. For glass materials, the Damascus process is used for electrical interconnection. However, due to the difference in materials between glass and silicon, a large amount of recipe debugging and machine hardware modification is involved, which is a huge workload. It is incompatible with the existing silicon adapter board production line and requires the establishment of a new production line.

[0039] The present invention has two process flows:

[0040] 1. Glass transfer plate process of silicon wafer-carrier process:

[0041] (1) Using Damascus structure on conventional silicon wafers for metal layer interconnection.

[0042] (2) Bond the completed silicon wafer face-to-face to the glass on which the TGV is completed.

[0043] (3) Remove the silicon wafer and continue to thin the glass transfer plate from the back if necessary.

[0044] The specific process flow diagram is as follows Figure 4 shown.

[0045] In addition, it should be noted that:

[0046] When silicon and wafer are bonded, they are face-to-face, so the order of making Damascus circuits on silicon is in reverse order, such as TM2, TM1, M5, M4, ... M1. That is, the order of CD from large to small.

[0047] Silicon wafers can be bonded to glass using anodic bonding or hybrid bonding.

[0048] Anodic bonding technology was proposed by Wallis and Pomerantz in 1969. It can bond glass to metal, alloy or semiconductor without any adhesive. This bonding temperature is low, the bonding interface is firm and the long-term stability is good.

[0049] Using the anodic bonding device, connect the silicon wafer to be bonded to the positive pole of the power supply, and the glass to the negative pole, with a voltage of 500-1000V. Heat the glass-silicon wafer to 300-500℃. When the voltage is applied, the Na ions in the glass will drift toward the negative pole, forming a depletion layer on the glass surface next to the silicon wafer, with a width of about several μm. The depletion layer carries a negative charge, and the silicon wafer carries a positive charge. There is a large electrostatic attraction between the silicon wafer and the glass, which makes the two in close contact. In this way, the external voltage is mainly applied to the depletion layer. The change in the current in the circuit can reflect the process of anodic bonding. When the voltage is just applied, there is a large current pulse, then the current decreases, and finally it is almost zero, indicating that the bonding has been completed at this time.

[0050] The closely contacted silicon / glass interface will undergo a chemical reaction to form strong chemical bonds, such as Si-O-Si bonds, forming a strong bonding interface.

[0051] The principle of silicon wafer-glass anodic bonding is as follows Figure 5 shown.

[0052] Hybrid bonding is a conventional process: since silicon is made of a dielectric layer and the main component of glass is also SiO2, conventional chemical mechanical polishing, ion activation, cleaning, bonding, annealing and other processes can be used to bond silicon wafers to glass to achieve electrical and structural connectivity.

[0053] This solution uses face-to-face bonding. If back-to-face bonding is used, Figure 6 As shown. The disadvantage of back-to-face bonding is the addition of a TSV process and a wafer bonding / debonding process. The advantage is that the Damascus process on the silicon wafer is in the normal order of M1, M2…TM1, TM2.

[0054] The bonding between glass and silicon is an alignment bonding, which requires ensuring that the TGV is electrically connected to the metal layer of the silicon wafer while being structurally connected.

[0055] 2. Glass substrate covered with silicon process:

[0056] (1) Silicon is grown on both the front and back sides of the glass transfer plate after TGV is completed.

[0057] (2) Perform TSV process on the silicon on the front side of the glass transfer board.

[0058] (3) Continue to use Damascus process on TSV.

[0059] (4) Remove the silicon on the back of the glass substrate and continue to thin the glass transfer plate from the back if necessary.

[0060] Process flow diagram Figure 7 As shown;

[0061] In addition, it should be noted that:

[0062] The idea of ​​this method is to grow a certain thickness of silicon material on both sides of the glass. At this time, the glass wafer is wrapped in silicon and thus exhibits the characteristics of a silicon wafer. All Damascus processes on the front side are equivalent to being made on a silicon wafer, which is fully compatible with conventional processes. The suction cup device on the back and a variety of sensing devices all detect silicon materials that are consistent with conventional silicon wafers and are also compatible with the original process.

[0063] The silicon growth process of this solution can use a furnace tube process to grow silicon on both the front and back sides at the same time, or can use silicon epitaxial chemical vapor deposition.

[0064] The furnace tube process is a low-pressure chemical vapor deposition (LPCVD) process, which is usually carried out in a vacuum furnace tube. Its characteristic is that the front and back sides can be covered with silicon material at the same time. The detailed schematic diagram is as follows Figure 8 shown.

[0065] Schematic diagram of silicon epitaxial growth Fig. 9 As shown, in order to ensure that both the front and back sides are covered with silicon, deposition is required once on the front side and once on the back side.

[0066] In addition to the Damascus copper process, the subsequent processes of this solution can also use any silicon-based metal interconnection process, such as the metal RDL process commonly used in packaging and testing factories, to achieve metal interconnection.

[0067] remove Figure 4 In addition to the glass transfer plate process of the face-to-face silicon wafer-carrier process shown in Fig.10 The glass shown has a characteristic structure with a layer of silicon material between it and the circuit.

[0068] From the above, it can be seen that the existing technology is mainly an electrical interconnection process for glass materials. This process is mostly used in the production of TFT LCD Array in panel factories. The line width of this process is relatively large, usually tens of μm, which cannot meet the electrical interconnection density requirements of the adapter board. Therefore, one technical route is to achieve it by miniaturizing the line width, but it is difficult to do so due to the glass material and the existing process flow. If a new process flow is developed, the cost is too high and the feasibility remains to be verified.

[0069] The existing silicon adapter board process is very mature. It is relatively difficult to directly apply the silicon adapter board process (mainly copper Damascus process) to glass wafers because the materials are quite different. It involves a lot of recipe software debugging and hardware modification, and it cannot be mixed and run with existing silicon machines. It is necessary to build a separate production line, which is too costly.

[0070] The advantage of the present invention is that almost all processes are completed on silicon materials, and the existing silicon copper Damascus process can be directly applied, and can be mixed and run with conventional silicon wafers; at the same time, both the silicon-glass bonding process and the silicon growth process on glass (furnace tube, silicon epitaxy, etc.) are mature processes. Therefore, this solution can greatly reduce the R&D cost, achieve the same interconnection density on the glass adapter board as the silicon adapter board, and also have the advantages of glass materials as mentioned above.

[0071] In addition, the present invention also has the following effects:

[0072] Option 1: Perform the Damascus metal interconnection process on silicon, then bond it to a glass substrate with TGV, and then remove the silicon to complete the production of a glass transfer board with high-density metal interconnection.

[0073] Option 2: Use furnace tube polysilicon deposition, silicon vapor phase epitaxy and other processes to deposit silicon on both sides of the glass sheet, disguising it as a common silicon wafer in the Fab factory, compatible with all silicon-based processes in the Fab, and then remove the silicon on the back of the crystal to complete the production of a glass transfer board with high-density metal interconnection.

[0074] Taking option 2, we can obtain Fig.10 The characteristic structure of the present invention is shown as glass + silicon layer + dielectric layer.

[0075] Copper is generated inside the glass through-holes, but as for how to make more sophisticated circuits on glass, the current processes similar to glass processing Fab are not sophisticated enough, while the process of silicon-based Fab can meet the needs. However, if the glass is processed directly in the silicon-based Fab using the silicon-based Fab process, there will be process incompatibility issues, which will ultimately make it impossible to achieve. Therefore, silicon is grown on both the front and back sides of the glass in advance. In this way, the silicon-based Fab machine can determine that the object being processed is a silicon wafer, so all processes are compatible with the silicon-based Fab, thereby completing a more sophisticated metal interconnect structure on the glass transfer board.

[0076] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0077] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0078] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

[0079] The above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A method for manufacturing a semiconductor device based on a glass transfer plate, characterized in that: The method includes: Step S1, stacking a plurality of metal pattern layers on a silicon substrate, wherein the plurality of metal pattern layers are electrically connected to each other and have a thickness in a range of 0.05 μm to 15 μm; Step S2, bonding one side of the silicon substrate having the plurality of metal pattern layers to a TGV glass sheet face to face, wherein the thickness of the TGV glass sheet is in a range of 20 μm to 2000 μm; Step S3, removing the silicon substrate and thinning the glass layer of the TGV glass sheet to a thickness of 15 μm to 1900 μm.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: When forming the plurality of metal pattern layers on the silicon substrate, the Damascus process is used to form them in a descending order of critical dimensions.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: In the step S1, each of the plurality of metal pattern layers is formed in the order of TM2, TM1, M5, M4, M3, M2, and M1.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: In the step S2, the silicon substrate and the TGV glass sheet are bonded by anodic bonding or hybrid bonding.

5. The method for manufacturing a semiconductor device according to claim 4, characterized in that: The silicon substrate is connected to the positive electrode of a power source, the TGV glass sheet is connected to the negative electrode of a power source, a voltage of 500 V to 1000 V is applied, and the heating temperature is maintained at 300° C. to 500° C.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: When voltage is applied, Na ions in the TGV glass sheet will drift toward the cathode and form a depletion layer with a thickness of 1 μm to 10 μm on the glass surface adjacent to the silicon sheet until the current between each of the multiple graphic circuit layers is reduced to near zero.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: A silicon layer with a thickness ranging from 0.05 μm to 300 μm is pre-grown on the surface of the TGV glass sheet.

8. The method for manufacturing a semiconductor device according to claim 1, wherein: Before the face-to-face bonding is performed, silicon layers are grown on the front and back surfaces of the TGV glass sheet by using a low-pressure chemical vapor deposition method or a silicon epitaxial chemical vapor deposition method.

9. The method for manufacturing a semiconductor device according to claim 1, wherein: The electrical connection of the multiple metal pattern layers is achieved by using a Damascus copper process or a silicon-based process.

10. A semiconductor device manufactured by the semiconductor device manufacturing method according to any one of claims 1 to 9.

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